?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / mtd / nand / pxa3xx_nand.c
blob4d01cda6884463daa844c02fde951970854e972a
1 /*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/io.h>
23 #include <linux/irq.h>
24 #include <linux/slab.h>
25
26 #include <mach/dma.h>
27 #include <plat/pxa3xx_nand.h>
28
29 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
30
31 /* registers and bit definitions */
32 #define NDCR (0x00) /* Control register */
33 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
34 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
35 #define NDSR (0x14) /* Status Register */
36 #define NDPCR (0x18) /* Page Count Register */
37 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
38 #define NDBDR1 (0x20) /* Bad Block Register 1 */
39 #define NDDB (0x40) /* Data Buffer */
40 #define NDCB0 (0x48) /* Command Buffer0 */
41 #define NDCB1 (0x4C) /* Command Buffer1 */
42 #define NDCB2 (0x50) /* Command Buffer2 */
43
44 #define NDCR_SPARE_EN (0x1 << 31)
45 #define NDCR_ECC_EN (0x1 << 30)
46 #define NDCR_DMA_EN (0x1 << 29)
47 #define NDCR_ND_RUN (0x1 << 28)
48 #define NDCR_DWIDTH_C (0x1 << 27)
49 #define NDCR_DWIDTH_M (0x1 << 26)
50 #define NDCR_PAGE_SZ (0x1 << 24)
51 #define NDCR_NCSX (0x1 << 23)
52 #define NDCR_ND_MODE (0x3 << 21)
53 #define NDCR_NAND_MODE (0x0)
54 #define NDCR_CLR_PG_CNT (0x1 << 20)
55 #define NDCR_CLR_ECC (0x1 << 19)
56 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
57 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
58
59 #define NDCR_RA_START (0x1 << 15)
60 #define NDCR_PG_PER_BLK (0x1 << 14)
61 #define NDCR_ND_ARB_EN (0x1 << 12)
62
63 #define NDSR_MASK (0xfff)
64 #define NDSR_RDY (0x1 << 11)
65 #define NDSR_CS0_PAGED (0x1 << 10)
66 #define NDSR_CS1_PAGED (0x1 << 9)
67 #define NDSR_CS0_CMDD (0x1 << 8)
68 #define NDSR_CS1_CMDD (0x1 << 7)
69 #define NDSR_CS0_BBD (0x1 << 6)
70 #define NDSR_CS1_BBD (0x1 << 5)
71 #define NDSR_DBERR (0x1 << 4)
72 #define NDSR_SBERR (0x1 << 3)
73 #define NDSR_WRDREQ (0x1 << 2)
74 #define NDSR_RDDREQ (0x1 << 1)
75 #define NDSR_WRCMDREQ (0x1)
76
77 #define NDCB0_AUTO_RS (0x1 << 25)
78 #define NDCB0_CSEL (0x1 << 24)
79 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
80 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
81 #define NDCB0_NC (0x1 << 20)
82 #define NDCB0_DBC (0x1 << 19)
83 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
84 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
85 #define NDCB0_CMD2_MASK (0xff << 8)
86 #define NDCB0_CMD1_MASK (0xff)
87 #define NDCB0_ADDR_CYC_SHIFT (16)
88
89 /* macros for registers read/write */
90 #define nand_writel(info, off, val) \
91 __raw_writel((val), (info)->mmio_base + (off))
92
93 #define nand_readl(info, off) \
94 __raw_readl((info)->mmio_base + (off))
95
96 /* error code and state */
97 enum {
98 ERR_NONE = 0,
99 ERR_DMABUSERR = -1,
100 ERR_SENDCMD = -2,
101 ERR_DBERR = -3,
102 ERR_BBERR = -4,
103 ERR_SBERR = -5,
104 };
105
106 enum {
107 STATE_READY = 0,
108 STATE_CMD_HANDLE,
109 STATE_DMA_READING,
110 STATE_DMA_WRITING,
111 STATE_DMA_DONE,
112 STATE_PIO_READING,
113 STATE_PIO_WRITING,
114 };
115
116 struct pxa3xx_nand_info {
117 struct nand_chip nand_chip;
118
119 struct platform_device *pdev;
120 const struct pxa3xx_nand_flash *flash_info;
121
122 struct clk *clk;
123 void __iomem *mmio_base;
124 unsigned long mmio_phys;
125
126 unsigned int buf_start;
127 unsigned int buf_count;
128
129 /* DMA information */
130 int drcmr_dat;
131 int drcmr_cmd;
132
133 unsigned char *data_buff;
134 dma_addr_t data_buff_phys;
135 size_t data_buff_size;
136 int data_dma_ch;
137 struct pxa_dma_desc *data_desc;
138 dma_addr_t data_desc_addr;
139
140 uint32_t reg_ndcr;
141
142 /* saved column/page_addr during CMD_SEQIN */
143 int seqin_column;
144 int seqin_page_addr;
145
146 /* relate to the command */
147 unsigned int state;
148
149 int use_ecc; /* use HW ECC ? */
150 int use_dma; /* use DMA ? */
151
152 size_t data_size; /* data size in FIFO */
153 int retcode;
154 struct completion cmd_complete;
155
156 /* generated NDCBx register values */
157 uint32_t ndcb0;
158 uint32_t ndcb1;
159 uint32_t ndcb2;
160
161 /* calculated from pxa3xx_nand_flash data */
162 size_t oob_size;
163 size_t read_id_bytes;
164
165 unsigned int col_addr_cycles;
166 unsigned int row_addr_cycles;
167 };
168
169 static int use_dma = 1;
170 module_param(use_dma, bool, 0444);
171 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
172
173 /*
174 * Default NAND flash controller configuration setup by the
175 * bootloader. This configuration is used only when pdata->keep_config is set
176 */
177 static struct pxa3xx_nand_timing default_timing;
178 static struct pxa3xx_nand_flash default_flash;
179
180 static struct pxa3xx_nand_cmdset smallpage_cmdset = {
181 .read1 = 0x0000,
182 .read2 = 0x0050,
183 .program = 0x1080,
184 .read_status = 0x0070,
185 .read_id = 0x0090,
186 .erase = 0xD060,
187 .reset = 0x00FF,
188 .lock = 0x002A,
189 .unlock = 0x2423,
190 .lock_status = 0x007A,
191 };
192
193 static struct pxa3xx_nand_cmdset largepage_cmdset = {
194 .read1 = 0x3000,
195 .read2 = 0x0050,
196 .program = 0x1080,
197 .read_status = 0x0070,
198 .read_id = 0x0090,
199 .erase = 0xD060,
200 .reset = 0x00FF,
201 .lock = 0x002A,
202 .unlock = 0x2423,
203 .lock_status = 0x007A,
204 };
205
206 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
207 static struct pxa3xx_nand_timing samsung512MbX16_timing = {
208 .tCH = 10,
209 .tCS = 0,
210 .tWH = 20,
211 .tWP = 40,
212 .tRH = 30,
213 .tRP = 40,
214 .tR = 11123,
215 .tWHR = 110,
216 .tAR = 10,
217 };
218
219 static struct pxa3xx_nand_flash samsung512MbX16 = {
220 .timing = &samsung512MbX16_timing,
221 .cmdset = &smallpage_cmdset,
222 .page_per_block = 32,
223 .page_size = 512,
224 .flash_width = 16,
225 .dfc_width = 16,
226 .num_blocks = 4096,
227 .chip_id = 0x46ec,
228 };
229
230 static struct pxa3xx_nand_flash samsung2GbX8 = {
231 .timing = &samsung512MbX16_timing,
232 .cmdset = &smallpage_cmdset,
233 .page_per_block = 64,
234 .page_size = 2048,
235 .flash_width = 8,
236 .dfc_width = 8,
237 .num_blocks = 2048,
238 .chip_id = 0xdaec,
239 };
240
241 static struct pxa3xx_nand_flash samsung32GbX8 = {
242 .timing = &samsung512MbX16_timing,
243 .cmdset = &smallpage_cmdset,
244 .page_per_block = 128,
245 .page_size = 4096,
246 .flash_width = 8,
247 .dfc_width = 8,
248 .num_blocks = 8192,
249 .chip_id = 0xd7ec,
250 };
251
252 static struct pxa3xx_nand_timing micron_timing = {
253 .tCH = 10,
254 .tCS = 25,
255 .tWH = 15,
256 .tWP = 25,
257 .tRH = 15,
258 .tRP = 30,
259 .tR = 25000,
260 .tWHR = 60,
261 .tAR = 10,
262 };
263
264 static struct pxa3xx_nand_flash micron1GbX8 = {
265 .timing = &micron_timing,
266 .cmdset = &largepage_cmdset,
267 .page_per_block = 64,
268 .page_size = 2048,
269 .flash_width = 8,
270 .dfc_width = 8,
271 .num_blocks = 1024,
272 .chip_id = 0xa12c,
273 };
274
275 static struct pxa3xx_nand_flash micron1GbX16 = {
276 .timing = &micron_timing,
277 .cmdset = &largepage_cmdset,
278 .page_per_block = 64,
279 .page_size = 2048,
280 .flash_width = 16,
281 .dfc_width = 16,
282 .num_blocks = 1024,
283 .chip_id = 0xb12c,
284 };
285
286 static struct pxa3xx_nand_flash micron4GbX8 = {
287 .timing = &micron_timing,
288 .cmdset = &largepage_cmdset,
289 .page_per_block = 64,
290 .page_size = 2048,
291 .flash_width = 8,
292 .dfc_width = 8,
293 .num_blocks = 4096,
294 .chip_id = 0xdc2c,
295 };
296
297 static struct pxa3xx_nand_flash micron4GbX16 = {
298 .timing = &micron_timing,
299 .cmdset = &largepage_cmdset,
300 .page_per_block = 64,
301 .page_size = 2048,
302 .flash_width = 16,
303 .dfc_width = 16,
304 .num_blocks = 4096,
305 .chip_id = 0xcc2c,
306 };
307
308 static struct pxa3xx_nand_timing stm2GbX16_timing = {
309 .tCH = 10,
310 .tCS = 35,
311 .tWH = 15,
312 .tWP = 25,
313 .tRH = 15,
314 .tRP = 25,
315 .tR = 25000,
316 .tWHR = 60,
317 .tAR = 10,
318 };
319
320 static struct pxa3xx_nand_flash stm2GbX16 = {
321 .timing = &stm2GbX16_timing,
322 .cmdset = &largepage_cmdset,
323 .page_per_block = 64,
324 .page_size = 2048,
325 .flash_width = 16,
326 .dfc_width = 16,
327 .num_blocks = 2048,
328 .chip_id = 0xba20,
329 };
330
331 static struct pxa3xx_nand_flash *builtin_flash_types[] = {
332 &samsung512MbX16,
333 &samsung2GbX8,
334 &samsung32GbX8,
335 &micron1GbX8,
336 &micron1GbX16,
337 &micron4GbX8,
338 &micron4GbX16,
339 &stm2GbX16,
340 };
341 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
342
343 #define NDTR0_tCH(c) (min((c), 7) << 19)
344 #define NDTR0_tCS(c) (min((c), 7) << 16)
345 #define NDTR0_tWH(c) (min((c), 7) << 11)
346 #define NDTR0_tWP(c) (min((c), 7) << 8)
347 #define NDTR0_tRH(c) (min((c), 7) << 3)
348 #define NDTR0_tRP(c) (min((c), 7) << 0)
349
350 #define NDTR1_tR(c) (min((c), 65535) << 16)
351 #define NDTR1_tWHR(c) (min((c), 15) << 4)
352 #define NDTR1_tAR(c) (min((c), 15) << 0)
353
354 #define tCH_NDTR0(r) (((r) >> 19) & 0x7)
355 #define tCS_NDTR0(r) (((r) >> 16) & 0x7)
356 #define tWH_NDTR0(r) (((r) >> 11) & 0x7)
357 #define tWP_NDTR0(r) (((r) >> 8) & 0x7)
358 #define tRH_NDTR0(r) (((r) >> 3) & 0x7)
359 #define tRP_NDTR0(r) (((r) >> 0) & 0x7)
360
361 #define tR_NDTR1(r) (((r) >> 16) & 0xffff)
362 #define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
363 #define tAR_NDTR1(r) (((r) >> 0) & 0xf)
364
365 /* convert nano-seconds to nand flash controller clock cycles */
366 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
367
368 /* convert nand flash controller clock cycles to nano-seconds */
369 #define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
370
371 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
372 const struct pxa3xx_nand_timing *t)
373 {
374 unsigned long nand_clk = clk_get_rate(info->clk);
375 uint32_t ndtr0, ndtr1;
376
377 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
378 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
379 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
380 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
381 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
382 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
383
384 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
385 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
386 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
387
388 nand_writel(info, NDTR0CS0, ndtr0);
389 nand_writel(info, NDTR1CS0, ndtr1);
390 }
391
392 #define WAIT_EVENT_TIMEOUT 10
393
394 static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
395 {
396 int timeout = WAIT_EVENT_TIMEOUT;
397 uint32_t ndsr;
398
399 while (timeout--) {
400 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
401 if (ndsr & event) {
402 nand_writel(info, NDSR, ndsr);
403 return 0;
404 }
405 udelay(10);
406 }
407
408 return -ETIMEDOUT;
409 }
410
411 static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
412 uint16_t cmd, int column, int page_addr)
413 {
414 const struct pxa3xx_nand_flash *f = info->flash_info;
415 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
416
417 /* calculate data size */
418 switch (f->page_size) {
419 case 2048:
420 info->data_size = (info->use_ecc) ? 2088 : 2112;
421 break;
422 case 512:
423 info->data_size = (info->use_ecc) ? 520 : 528;
424 break;
425 default:
426 return -EINVAL;
427 }
428
429 /* generate values for NDCBx registers */
430 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
431 info->ndcb1 = 0;
432 info->ndcb2 = 0;
433 info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
434
435 if (info->col_addr_cycles == 2) {
436 /* large block, 2 cycles for column address
437 * row address starts from 3rd cycle
438 */
439 info->ndcb1 |= page_addr << 16;
440 if (info->row_addr_cycles == 3)
441 info->ndcb2 = (page_addr >> 16) & 0xff;
442 } else
443 /* small block, 1 cycles for column address
444 * row address starts from 2nd cycle
445 */
446 info->ndcb1 = page_addr << 8;
447
448 if (cmd == cmdset->program)
449 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
450
451 return 0;
452 }
453
454 static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
455 uint16_t cmd, int page_addr)
456 {
457 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
458 info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
459 info->ndcb1 = page_addr;
460 info->ndcb2 = 0;
461 return 0;
462 }
463
464 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
465 {
466 const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
467
468 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
469 info->ndcb1 = 0;
470 info->ndcb2 = 0;
471
472 if (cmd == cmdset->read_id) {
473 info->ndcb0 |= NDCB0_CMD_TYPE(3);
474 info->data_size = 8;
475 } else if (cmd == cmdset->read_status) {
476 info->ndcb0 |= NDCB0_CMD_TYPE(4);
477 info->data_size = 8;
478 } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
479 cmd == cmdset->unlock) {
480 info->ndcb0 |= NDCB0_CMD_TYPE(5);
481 } else
482 return -EINVAL;
483
484 return 0;
485 }
486
487 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
488 {
489 uint32_t ndcr;
490
491 ndcr = nand_readl(info, NDCR);
492 nand_writel(info, NDCR, ndcr & ~int_mask);
493 }
494
495 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
496 {
497 uint32_t ndcr;
498
499 ndcr = nand_readl(info, NDCR);
500 nand_writel(info, NDCR, ndcr | int_mask);
501 }
502
503 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
504 * otherwise, it does not work
505 */
506 static int write_cmd(struct pxa3xx_nand_info *info)
507 {
508 uint32_t ndcr;
509
510 /* clear status bits and run */
511 nand_writel(info, NDSR, NDSR_MASK);
512
513 ndcr = info->reg_ndcr;
514
515 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
516 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
517 ndcr |= NDCR_ND_RUN;
518
519 nand_writel(info, NDCR, ndcr);
520
521 if (wait_for_event(info, NDSR_WRCMDREQ)) {
522 printk(KERN_ERR "timed out writing command\n");
523 return -ETIMEDOUT;
524 }
525
526 nand_writel(info, NDCB0, info->ndcb0);
527 nand_writel(info, NDCB0, info->ndcb1);
528 nand_writel(info, NDCB0, info->ndcb2);
529 return 0;
530 }
531
532 static int handle_data_pio(struct pxa3xx_nand_info *info)
533 {
534 int ret, timeout = CHIP_DELAY_TIMEOUT;
535
536 switch (info->state) {
537 case STATE_PIO_WRITING:
538 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
539 DIV_ROUND_UP(info->data_size, 4));
540
541 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
542
543 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
544 if (!ret) {
545 printk(KERN_ERR "program command time out\n");
546 return -1;
547 }
548 break;
549 case STATE_PIO_READING:
550 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
551 DIV_ROUND_UP(info->data_size, 4));
552 break;
553 default:
554 printk(KERN_ERR "%s: invalid state %d\n", __func__,
555 info->state);
556 return -EINVAL;
557 }
558
559 info->state = STATE_READY;
560 return 0;
561 }
562
563 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
564 {
565 struct pxa_dma_desc *desc = info->data_desc;
566 int dma_len = ALIGN(info->data_size, 32);
567
568 desc->ddadr = DDADR_STOP;
569 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
570
571 if (dir_out) {
572 desc->dsadr = info->data_buff_phys;
573 desc->dtadr = info->mmio_phys + NDDB;
574 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
575 } else {
576 desc->dtadr = info->data_buff_phys;
577 desc->dsadr = info->mmio_phys + NDDB;
578 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
579 }
580
581 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
582 DDADR(info->data_dma_ch) = info->data_desc_addr;
583 DCSR(info->data_dma_ch) |= DCSR_RUN;
584 }
585
586 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
587 {
588 struct pxa3xx_nand_info *info = data;
589 uint32_t dcsr;
590
591 dcsr = DCSR(channel);
592 DCSR(channel) = dcsr;
593
594 if (dcsr & DCSR_BUSERR) {
595 info->retcode = ERR_DMABUSERR;
596 complete(&info->cmd_complete);
597 }
598
599 if (info->state == STATE_DMA_WRITING) {
600 info->state = STATE_DMA_DONE;
601 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
602 } else {
603 info->state = STATE_READY;
604 complete(&info->cmd_complete);
605 }
606 }
607
608 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
609 {
610 struct pxa3xx_nand_info *info = devid;
611 unsigned int status;
612
613 status = nand_readl(info, NDSR);
614
615 if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
616 if (status & NDSR_DBERR)
617 info->retcode = ERR_DBERR;
618 else if (status & NDSR_SBERR)
619 info->retcode = ERR_SBERR;
620
621 disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
622
623 if (info->use_dma) {
624 info->state = STATE_DMA_READING;
625 start_data_dma(info, 0);
626 } else {
627 info->state = STATE_PIO_READING;
628 complete(&info->cmd_complete);
629 }
630 } else if (status & NDSR_WRDREQ) {
631 disable_int(info, NDSR_WRDREQ);
632 if (info->use_dma) {
633 info->state = STATE_DMA_WRITING;
634 start_data_dma(info, 1);
635 } else {
636 info->state = STATE_PIO_WRITING;
637 complete(&info->cmd_complete);
638 }
639 } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
640 if (status & NDSR_CS0_BBD)
641 info->retcode = ERR_BBERR;
642
643 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
644 info->state = STATE_READY;
645 complete(&info->cmd_complete);
646 }
647 nand_writel(info, NDSR, status);
648 return IRQ_HANDLED;
649 }
650
651 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
652 {
653 uint32_t ndcr;
654 int ret, timeout = CHIP_DELAY_TIMEOUT;
655
656 if (write_cmd(info)) {
657 info->retcode = ERR_SENDCMD;
658 goto fail_stop;
659 }
660
661 info->state = STATE_CMD_HANDLE;
662
663 enable_int(info, event);
664
665 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
666 if (!ret) {
667 printk(KERN_ERR "command execution timed out\n");
668 info->retcode = ERR_SENDCMD;
669 goto fail_stop;
670 }
671
672 if (info->use_dma == 0 && info->data_size > 0)
673 if (handle_data_pio(info))
674 goto fail_stop;
675
676 return 0;
677
678 fail_stop:
679 ndcr = nand_readl(info, NDCR);
680 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
681 udelay(10);
682 return -ETIMEDOUT;
683 }
684
685 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
686 {
687 struct pxa3xx_nand_info *info = mtd->priv;
688 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
689 }
690
691 static inline int is_buf_blank(uint8_t *buf, size_t len)
692 {
693 for (; len > 0; len--)
694 if (*buf++ != 0xff)
695 return 0;
696 return 1;
697 }
698
699 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
700 int column, int page_addr)
701 {
702 struct pxa3xx_nand_info *info = mtd->priv;
703 const struct pxa3xx_nand_flash *flash_info = info->flash_info;
704 const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
705 int ret;
706
707 info->use_dma = (use_dma) ? 1 : 0;
708 info->use_ecc = 0;
709 info->data_size = 0;
710 info->state = STATE_READY;
711
712 init_completion(&info->cmd_complete);
713
714 switch (command) {
715 case NAND_CMD_READOOB:
716 /* disable HW ECC to get all the OOB data */
717 info->buf_count = mtd->writesize + mtd->oobsize;
718 info->buf_start = mtd->writesize + column;
719 memset(info->data_buff, 0xFF, info->buf_count);
720
721 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
722 break;
723
724 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
725
726 /* We only are OOB, so if the data has error, does not matter */
727 if (info->retcode == ERR_DBERR)
728 info->retcode = ERR_NONE;
729 break;
730
731 case NAND_CMD_READ0:
732 info->use_ecc = 1;
733 info->retcode = ERR_NONE;
734 info->buf_start = column;
735 info->buf_count = mtd->writesize + mtd->oobsize;
736 memset(info->data_buff, 0xFF, info->buf_count);
737
738 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
739 break;
740
741 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
742
743 if (info->retcode == ERR_DBERR) {
744 /* for blank page (all 0xff), HW will calculate its ECC as
745 * 0, which is different from the ECC information within
746 * OOB, ignore such double bit errors
747 */
748 if (is_buf_blank(info->data_buff, mtd->writesize))
749 info->retcode = ERR_NONE;
750 }
751 break;
752 case NAND_CMD_SEQIN:
753 info->buf_start = column;
754 info->buf_count = mtd->writesize + mtd->oobsize;
755 memset(info->data_buff, 0xff, info->buf_count);
756
757 /* save column/page_addr for next CMD_PAGEPROG */
758 info->seqin_column = column;
759 info->seqin_page_addr = page_addr;
760 break;
761 case NAND_CMD_PAGEPROG:
762 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
763
764 if (prepare_read_prog_cmd(info, cmdset->program,
765 info->seqin_column, info->seqin_page_addr))
766 break;
767
768 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
769 break;
770 case NAND_CMD_ERASE1:
771 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
772 break;
773
774 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
775 break;
776 case NAND_CMD_ERASE2:
777 break;
778 case NAND_CMD_READID:
779 case NAND_CMD_STATUS:
780 info->use_dma = 0; /* force PIO read */
781 info->buf_start = 0;
782 info->buf_count = (command == NAND_CMD_READID) ?
783 info->read_id_bytes : 1;
784
785 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
786 cmdset->read_id : cmdset->read_status))
787 break;
788
789 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
790 break;
791 case NAND_CMD_RESET:
792 if (prepare_other_cmd(info, cmdset->reset))
793 break;
794
795 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
796 if (ret == 0) {
797 int timeout = 2;
798 uint32_t ndcr;
799
800 while (timeout--) {
801 if (nand_readl(info, NDSR) & NDSR_RDY)
802 break;
803 msleep(10);
804 }
805
806 ndcr = nand_readl(info, NDCR);
807 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
808 }
809 break;
810 default:
811 printk(KERN_ERR "non-supported command.\n");
812 break;
813 }
814
815 if (info->retcode == ERR_DBERR) {
816 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
817 info->retcode = ERR_NONE;
818 }
819 }
820
821 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
822 {
823 struct pxa3xx_nand_info *info = mtd->priv;
824 char retval = 0xFF;
825
826 if (info->buf_start < info->buf_count)
827 /* Has just send a new command? */
828 retval = info->data_buff[info->buf_start++];
829
830 return retval;
831 }
832
833 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
834 {
835 struct pxa3xx_nand_info *info = mtd->priv;
836 u16 retval = 0xFFFF;
837
838 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
839 retval = *((u16 *)(info->data_buff+info->buf_start));
840 info->buf_start += 2;
841 }
842 return retval;
843 }
844
845 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
846 {
847 struct pxa3xx_nand_info *info = mtd->priv;
848 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
849
850 memcpy(buf, info->data_buff + info->buf_start, real_len);
851 info->buf_start += real_len;
852 }
853
854 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
855 const uint8_t *buf, int len)
856 {
857 struct pxa3xx_nand_info *info = mtd->priv;
858 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
859
860 memcpy(info->data_buff + info->buf_start, buf, real_len);
861 info->buf_start += real_len;
862 }
863
864 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
865 const uint8_t *buf, int len)
866 {
867 return 0;
868 }
869
870 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
871 {
872 return;
873 }
874
875 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
876 {
877 struct pxa3xx_nand_info *info = mtd->priv;
878
879 /* pxa3xx_nand_send_command has waited for command complete */
880 if (this->state == FL_WRITING || this->state == FL_ERASING) {
881 if (info->retcode == ERR_NONE)
882 return 0;
883 else {
884 /*
885 * any error make it return 0x01 which will tell
886 * the caller the erase and write fail
887 */
888 return 0x01;
889 }
890 }
891
892 return 0;
893 }
894
895 static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
896 {
897 return;
898 }
899
900 static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
901 const uint8_t *dat, uint8_t *ecc_code)
902 {
903 return 0;
904 }
905
906 static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
907 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
908 {
909 struct pxa3xx_nand_info *info = mtd->priv;
910 /*
911 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
912 * consider it as a ecc error which will tell the caller the
913 * read fail We have distinguish all the errors, but the
914 * nand_read_ecc only check this function return value
915 *
916 * Corrected (single-bit) errors must also be noted.
917 */
918 if (info->retcode == ERR_SBERR)
919 return 1;
920 else if (info->retcode != ERR_NONE)
921 return -1;
922
923 return 0;
924 }
925
926 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
927 {
928 const struct pxa3xx_nand_flash *f = info->flash_info;
929 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
930 uint32_t ndcr;
931 uint8_t id_buff[8];
932
933 if (prepare_other_cmd(info, cmdset->read_id)) {
934 printk(KERN_ERR "failed to prepare command\n");
935 return -EINVAL;
936 }
937
938 /* Send command */
939 if (write_cmd(info))
940 goto fail_timeout;
941
942 /* Wait for CMDDM(command done successfully) */
943 if (wait_for_event(info, NDSR_RDDREQ))
944 goto fail_timeout;
945
946 __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
947 *id = id_buff[0] | (id_buff[1] << 8);
948 return 0;
949
950 fail_timeout:
951 ndcr = nand_readl(info, NDCR);
952 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
953 udelay(10);
954 return -ETIMEDOUT;
955 }
956
957 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
958 const struct pxa3xx_nand_flash *f)
959 {
960 struct platform_device *pdev = info->pdev;
961 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
962 uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
963
964 if (f->page_size != 2048 && f->page_size != 512)
965 return -EINVAL;
966
967 if (f->flash_width != 16 && f->flash_width != 8)
968 return -EINVAL;
969
970 /* calculate flash information */
971 info->oob_size = (f->page_size == 2048) ? 64 : 16;
972 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
973
974 /* calculate addressing information */
975 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
976
977 if (f->num_blocks * f->page_per_block > 65536)
978 info->row_addr_cycles = 3;
979 else
980 info->row_addr_cycles = 2;
981
982 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
983 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
984 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
985 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
986 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
987 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
988
989 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
990 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
991
992 info->reg_ndcr = ndcr;
993
994 pxa3xx_nand_set_timing(info, f->timing);
995 info->flash_info = f;
996 return 0;
997 }
998
999 static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
1000 struct pxa3xx_nand_timing *t)
1001 {
1002 unsigned long nand_clk = clk_get_rate(info->clk);
1003 uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
1004 uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
1005
1006 t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
1007 t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
1008 t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
1009 t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
1010 t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
1011 t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
1012
1013 t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
1014 t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
1015 t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
1016 }
1017
1018 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1019 {
1020 uint32_t ndcr = nand_readl(info, NDCR);
1021 struct nand_flash_dev *type = NULL;
1022 uint32_t id = -1;
1023 int i;
1024
1025 default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
1026 default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
1027 default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
1028 default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
1029
1030 if (default_flash.page_size == 2048)
1031 default_flash.cmdset = &largepage_cmdset;
1032 else
1033 default_flash.cmdset = &smallpage_cmdset;
1034
1035 /* set info fields needed to __readid */
1036 info->flash_info = &default_flash;
1037 info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
1038 info->reg_ndcr = ndcr;
1039
1040 if (__readid(info, &id))
1041 return -ENODEV;
1042
1043 /* Lookup the flash id */
1044 id = (id >> 8) & 0xff; /* device id is byte 2 */
1045 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
1046 if (id == nand_flash_ids[i].id) {
1047 type = &nand_flash_ids[i];
1048 break;
1049 }
1050 }
1051
1052 if (!type)
1053 return -ENODEV;
1054
1055 /* fill the missing flash information */
1056 i = __ffs(default_flash.page_per_block * default_flash.page_size);
1057 default_flash.num_blocks = type->chipsize << (20 - i);
1058
1059 info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
1060
1061 /* calculate addressing information */
1062 info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
1063
1064 if (default_flash.num_blocks * default_flash.page_per_block > 65536)
1065 info->row_addr_cycles = 3;
1066 else
1067 info->row_addr_cycles = 2;
1068
1069 pxa3xx_nand_detect_timing(info, &default_timing);
1070 default_flash.timing = &default_timing;
1071
1072 return 0;
1073 }
1074
1075 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1076 const struct pxa3xx_nand_platform_data *pdata)
1077 {
1078 const struct pxa3xx_nand_flash *f;
1079 uint32_t id = -1;
1080 int i;
1081
1082 if (pdata->keep_config)
1083 if (pxa3xx_nand_detect_config(info) == 0)
1084 return 0;
1085
1086 for (i = 0; i<pdata->num_flash; ++i) {
1087 f = pdata->flash + i;
1088
1089 if (pxa3xx_nand_config_flash(info, f))
1090 continue;
1091
1092 if (__readid(info, &id))
1093 continue;
1094
1095 if (id == f->chip_id)
1096 return 0;
1097 }
1098
1099 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
1100 for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
1101
1102 f = builtin_flash_types[i];
1103
1104 if (pxa3xx_nand_config_flash(info, f))
1105 continue;
1106
1107 if (__readid(info, &id))
1108 continue;
1109
1110 if (id == f->chip_id)
1111 return 0;
1112 }
1113 #endif
1114
1115 dev_warn(&info->pdev->dev,
1116 "failed to detect configured nand flash; found %04x instead of\n",
1117 id);
1118 return -ENODEV;
1119 }
1120
1121 /* the maximum possible buffer size for large page with OOB data
1122 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
1123 * data buffer and the DMA descriptor
1124 */
1125 #define MAX_BUFF_SIZE PAGE_SIZE
1126
1127 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1128 {
1129 struct platform_device *pdev = info->pdev;
1130 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
1131
1132 if (use_dma == 0) {
1133 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
1134 if (info->data_buff == NULL)
1135 return -ENOMEM;
1136 return 0;
1137 }
1138
1139 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
1140 &info->data_buff_phys, GFP_KERNEL);
1141 if (info->data_buff == NULL) {
1142 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1143 return -ENOMEM;
1144 }
1145
1146 info->data_buff_size = MAX_BUFF_SIZE;
1147 info->data_desc = (void *)info->data_buff + data_desc_offset;
1148 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1149
1150 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1151 pxa3xx_nand_data_dma_irq, info);
1152 if (info->data_dma_ch < 0) {
1153 dev_err(&pdev->dev, "failed to request data dma\n");
1154 dma_free_coherent(&pdev->dev, info->data_buff_size,
1155 info->data_buff, info->data_buff_phys);
1156 return info->data_dma_ch;
1157 }
1158
1159 return 0;
1160 }
1161
1162 static struct nand_ecclayout hw_smallpage_ecclayout = {
1163 .eccbytes = 6,
1164 .eccpos = {8, 9, 10, 11, 12, 13 },
1165 .oobfree = { {2, 6} }
1166 };
1167
1168 static struct nand_ecclayout hw_largepage_ecclayout = {
1169 .eccbytes = 24,
1170 .eccpos = {
1171 40, 41, 42, 43, 44, 45, 46, 47,
1172 48, 49, 50, 51, 52, 53, 54, 55,
1173 56, 57, 58, 59, 60, 61, 62, 63},
1174 .oobfree = { {2, 38} }
1175 };
1176
1177 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1178 struct pxa3xx_nand_info *info)
1179 {
1180 const struct pxa3xx_nand_flash *f = info->flash_info;
1181 struct nand_chip *this = &info->nand_chip;
1182
1183 this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1184
1185 this->waitfunc = pxa3xx_nand_waitfunc;
1186 this->select_chip = pxa3xx_nand_select_chip;
1187 this->dev_ready = pxa3xx_nand_dev_ready;
1188 this->cmdfunc = pxa3xx_nand_cmdfunc;
1189 this->read_word = pxa3xx_nand_read_word;
1190 this->read_byte = pxa3xx_nand_read_byte;
1191 this->read_buf = pxa3xx_nand_read_buf;
1192 this->write_buf = pxa3xx_nand_write_buf;
1193 this->verify_buf = pxa3xx_nand_verify_buf;
1194
1195 this->ecc.mode = NAND_ECC_HW;
1196 this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
1197 this->ecc.calculate = pxa3xx_nand_ecc_calculate;
1198 this->ecc.correct = pxa3xx_nand_ecc_correct;
1199 this->ecc.size = f->page_size;
1200
1201 if (f->page_size == 2048)
1202 this->ecc.layout = &hw_largepage_ecclayout;
1203 else
1204 this->ecc.layout = &hw_smallpage_ecclayout;
1205
1206 this->chip_delay = 25;
1207 }
1208
1209 static int pxa3xx_nand_probe(struct platform_device *pdev)
1210 {
1211 struct pxa3xx_nand_platform_data *pdata;
1212 struct pxa3xx_nand_info *info;
1213 struct nand_chip *this;
1214 struct mtd_info *mtd;
1215 struct resource *r;
1216 int ret = 0, irq;
1217
1218 pdata = pdev->dev.platform_data;
1219
1220 if (!pdata) {
1221 dev_err(&pdev->dev, "no platform data defined\n");
1222 return -ENODEV;
1223 }
1224
1225 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1226 GFP_KERNEL);
1227 if (!mtd) {
1228 dev_err(&pdev->dev, "failed to allocate memory\n");
1229 return -ENOMEM;
1230 }
1231
1232 info = (struct pxa3xx_nand_info *)(&mtd[1]);
1233 info->pdev = pdev;
1234
1235 this = &info->nand_chip;
1236 mtd->priv = info;
1237 mtd->owner = THIS_MODULE;
1238
1239 info->clk = clk_get(&pdev->dev, NULL);
1240 if (IS_ERR(info->clk)) {
1241 dev_err(&pdev->dev, "failed to get nand clock\n");
1242 ret = PTR_ERR(info->clk);
1243 goto fail_free_mtd;
1244 }
1245 clk_enable(info->clk);
1246
1247 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1248 if (r == NULL) {
1249 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1250 ret = -ENXIO;
1251 goto fail_put_clk;
1252 }
1253 info->drcmr_dat = r->start;
1254
1255 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1256 if (r == NULL) {
1257 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1258 ret = -ENXIO;
1259 goto fail_put_clk;
1260 }
1261 info->drcmr_cmd = r->start;
1262
1263 irq = platform_get_irq(pdev, 0);
1264 if (irq < 0) {
1265 dev_err(&pdev->dev, "no IRQ resource defined\n");
1266 ret = -ENXIO;
1267 goto fail_put_clk;
1268 }
1269
1270 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1271 if (r == NULL) {
1272 dev_err(&pdev->dev, "no IO memory resource defined\n");
1273 ret = -ENODEV;
1274 goto fail_put_clk;
1275 }
1276
1277 r = request_mem_region(r->start, resource_size(r), pdev->name);
1278 if (r == NULL) {
1279 dev_err(&pdev->dev, "failed to request memory resource\n");
1280 ret = -EBUSY;
1281 goto fail_put_clk;
1282 }
1283
1284 info->mmio_base = ioremap(r->start, resource_size(r));
1285 if (info->mmio_base == NULL) {
1286 dev_err(&pdev->dev, "ioremap() failed\n");
1287 ret = -ENODEV;
1288 goto fail_free_res;
1289 }
1290 info->mmio_phys = r->start;
1291
1292 ret = pxa3xx_nand_init_buff(info);
1293 if (ret)
1294 goto fail_free_io;
1295
1296 /* initialize all interrupts to be disabled */
1297 disable_int(info, NDSR_MASK);
1298
1299 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1300 pdev->name, info);
1301 if (ret < 0) {
1302 dev_err(&pdev->dev, "failed to request IRQ\n");
1303 goto fail_free_buf;
1304 }
1305
1306 ret = pxa3xx_nand_detect_flash(info, pdata);
1307 if (ret) {
1308 dev_err(&pdev->dev, "failed to detect flash\n");
1309 ret = -ENODEV;
1310 goto fail_free_irq;
1311 }
1312
1313 pxa3xx_nand_init_mtd(mtd, info);
1314
1315 platform_set_drvdata(pdev, mtd);
1316
1317 if (nand_scan(mtd, 1)) {
1318 dev_err(&pdev->dev, "failed to scan nand\n");
1319 ret = -ENXIO;
1320 goto fail_free_irq;
1321 }
1322
1323 #ifdef CONFIG_MTD_PARTITIONS
1324 if (mtd_has_cmdlinepart()) {
1325 static const char *probes[] = { "cmdlinepart", NULL };
1326 struct mtd_partition *parts;
1327 int nr_parts;
1328
1329 nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
1330
1331 if (nr_parts)
1332 return add_mtd_partitions(mtd, parts, nr_parts);
1333 }
1334
1335 return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1336 #else
1337 return 0;
1338 #endif
1339
1340 fail_free_irq:
1341 free_irq(irq, info);
1342 fail_free_buf:
1343 if (use_dma) {
1344 pxa_free_dma(info->data_dma_ch);
1345 dma_free_coherent(&pdev->dev, info->data_buff_size,
1346 info->data_buff, info->data_buff_phys);
1347 } else
1348 kfree(info->data_buff);
1349 fail_free_io:
1350 iounmap(info->mmio_base);
1351 fail_free_res:
1352 release_mem_region(r->start, resource_size(r));
1353 fail_put_clk:
1354 clk_disable(info->clk);
1355 clk_put(info->clk);
1356 fail_free_mtd:
1357 kfree(mtd);
1358 return ret;
1359 }
1360
1361 static int pxa3xx_nand_remove(struct platform_device *pdev)
1362 {
1363 struct mtd_info *mtd = platform_get_drvdata(pdev);
1364 struct pxa3xx_nand_info *info = mtd->priv;
1365 struct resource *r;
1366 int irq;
1367
1368 platform_set_drvdata(pdev, NULL);
1369
1370 del_mtd_device(mtd);
1371 #ifdef CONFIG_MTD_PARTITIONS
1372 del_mtd_partitions(mtd);
1373 #endif
1374 irq = platform_get_irq(pdev, 0);
1375 if (irq >= 0)
1376 free_irq(irq, info);
1377 if (use_dma) {
1378 pxa_free_dma(info->data_dma_ch);
1379 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1380 info->data_buff, info->data_buff_phys);
1381 } else
1382 kfree(info->data_buff);
1383
1384 iounmap(info->mmio_base);
1385 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 release_mem_region(r->start, resource_size(r));
1387
1388 clk_disable(info->clk);
1389 clk_put(info->clk);
1390
1391 kfree(mtd);
1392 return 0;
1393 }
1394
1395 #ifdef CONFIG_PM
1396 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1397 {
1398 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1399 struct pxa3xx_nand_info *info = mtd->priv;
1400
1401 if (info->state != STATE_READY) {
1402 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1403 return -EAGAIN;
1404 }
1405
1406 return 0;
1407 }
1408
1409 static int pxa3xx_nand_resume(struct platform_device *pdev)
1410 {
1411 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1412 struct pxa3xx_nand_info *info = mtd->priv;
1413
1414 clk_enable(info->clk);
1415
1416 return pxa3xx_nand_config_flash(info, info->flash_info);
1417 }
1418 #else
1419 #define pxa3xx_nand_suspend NULL
1420 #define pxa3xx_nand_resume NULL
1421 #endif
1422
1423 static struct platform_driver pxa3xx_nand_driver = {
1424 .driver = {
1425 .name = "pxa3xx-nand",
1426 },
1427 .probe = pxa3xx_nand_probe,
1428 .remove = pxa3xx_nand_remove,
1429 .suspend = pxa3xx_nand_suspend,
1430 .resume = pxa3xx_nand_resume,
1431 };
1432
1433 static int __init pxa3xx_nand_init(void)
1434 {
1435 return platform_driver_register(&pxa3xx_nand_driver);
1436 }
1437 module_init(pxa3xx_nand_init);
1438
1439 static void __exit pxa3xx_nand_exit(void)
1440 {
1441 platform_driver_unregister(&pxa3xx_nand_driver);
1442 }
1443 module_exit(pxa3xx_nand_exit);
1444
1445 MODULE_LICENSE("GPL");
1446 MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Tomato firmware and modifications.