?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / mtd / nand / fsl_elbc_nand.c
blob01006c04f9e95ead1545af65dc78285bf28aa8a8
1 /* Freescale Enhanced Local Bus Controller NAND driver
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/ioport.h>
29 #include <linux/of_platform.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/nand_ecc.h>
36 #include <linux/mtd/partitions.h>
37
38 #include <asm/io.h>
39 #include <asm/fsl_lbc.h>
40
41 #define MAX_BANKS 8
42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
44
45 struct fsl_elbc_ctrl;
46
47 /* mtd information per set */
48
49 struct fsl_elbc_mtd {
50 struct mtd_info mtd;
51 struct nand_chip chip;
52 struct fsl_elbc_ctrl *ctrl;
53
54 struct device *dev;
55 int bank; /* Chip select bank number */
56 u8 __iomem *vbase; /* Chip select base virtual address */
57 int page_size; /* NAND page size (0=512, 1=2048) */
58 unsigned int fmr; /* FCM Flash Mode Register value */
59 };
60
61 /* overview of the fsl elbc controller */
62
63 struct fsl_elbc_ctrl {
64 struct nand_hw_control controller;
65 struct fsl_elbc_mtd *chips[MAX_BANKS];
66
67 /* device info */
68 struct device *dev;
69 struct fsl_lbc_regs __iomem *regs;
70 int irq;
71 wait_queue_head_t irq_wait;
72 unsigned int irq_status; /* status read from LTESR by irq handler */
73 u8 __iomem *addr; /* Address of assigned FCM buffer */
74 unsigned int page; /* Last page written to / read from */
75 unsigned int read_bytes; /* Number of bytes read during command */
76 unsigned int column; /* Saved column from SEQIN */
77 unsigned int index; /* Pointer to next byte to 'read' */
78 unsigned int status; /* status read from LTESR after last op */
79 unsigned int mdr; /* UPM/FCM Data Register value */
80 unsigned int use_mdr; /* Non zero if the MDR is to be set */
81 unsigned int oob; /* Non zero if operating on OOB data */
82 char *oob_poi; /* Place to write ECC after read back */
83 };
84
85 /* These map to the positions used by the FCM hardware ECC generator */
86
87 /* Small Page FLASH with FMR[ECCM] = 0 */
88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
89 .eccbytes = 3,
90 .eccpos = {6, 7, 8},
91 .oobfree = { {0, 5}, {9, 7} },
92 };
93
94 /* Small Page FLASH with FMR[ECCM] = 1 */
95 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
96 .eccbytes = 3,
97 .eccpos = {8, 9, 10},
98 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
99 };
100
101 /* Large Page FLASH with FMR[ECCM] = 0 */
102 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
103 .eccbytes = 12,
104 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
105 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
106 };
107
108 /* Large Page FLASH with FMR[ECCM] = 1 */
109 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
110 .eccbytes = 12,
111 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
112 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
113 };
114
115 /*
116 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
117 * 1, so we have to adjust bad block pattern. This pattern should be used for
118 * x8 chips only. So far hardware does not support x16 chips anyway.
119 */
120 static u8 scan_ff_pattern[] = { 0xff, };
121
122 static struct nand_bbt_descr largepage_memorybased = {
123 .options = 0,
124 .offs = 0,
125 .len = 1,
126 .pattern = scan_ff_pattern,
127 };
128
129 /*
130 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
131 * interfere with ECC positions, that's why we implement our own descriptors.
132 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
133 */
134 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
135 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
136
137 static struct nand_bbt_descr bbt_main_descr = {
138 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
139 NAND_BBT_2BIT | NAND_BBT_VERSION,
140 .offs = 11,
141 .len = 4,
142 .veroffs = 15,
143 .maxblocks = 4,
144 .pattern = bbt_pattern,
145 };
146
147 static struct nand_bbt_descr bbt_mirror_descr = {
148 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
149 NAND_BBT_2BIT | NAND_BBT_VERSION,
150 .offs = 11,
151 .len = 4,
152 .veroffs = 15,
153 .maxblocks = 4,
154 .pattern = mirror_pattern,
155 };
156
157 /*=================================*/
158
159 /*
160 * Set up the FCM hardware block and page address fields, and the fcm
161 * structure addr field to point to the correct FCM buffer in memory
162 */
163 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
164 {
165 struct nand_chip *chip = mtd->priv;
166 struct fsl_elbc_mtd *priv = chip->priv;
167 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
168 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
169 int buf_num;
170
171 ctrl->page = page_addr;
172
173 out_be32(&lbc->fbar,
174 page_addr >> (chip->phys_erase_shift - chip->page_shift));
175
176 if (priv->page_size) {
177 out_be32(&lbc->fpar,
178 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
179 (oob ? FPAR_LP_MS : 0) | column);
180 buf_num = (page_addr & 1) << 2;
181 } else {
182 out_be32(&lbc->fpar,
183 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
184 (oob ? FPAR_SP_MS : 0) | column);
185 buf_num = page_addr & 7;
186 }
187
188 ctrl->addr = priv->vbase + buf_num * 1024;
189 ctrl->index = column;
190
191 /* for OOB data point to the second half of the buffer */
192 if (oob)
193 ctrl->index += priv->page_size ? 2048 : 512;
194
195 dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
196 "index %x, pes %d ps %d\n",
197 buf_num, ctrl->addr, priv->vbase, ctrl->index,
198 chip->phys_erase_shift, chip->page_shift);
199 }
200
201 /*
202 * execute FCM command and wait for it to complete
203 */
204 static int fsl_elbc_run_command(struct mtd_info *mtd)
205 {
206 struct nand_chip *chip = mtd->priv;
207 struct fsl_elbc_mtd *priv = chip->priv;
208 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
209 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
210
211 /* Setup the FMR[OP] to execute without write protection */
212 out_be32(&lbc->fmr, priv->fmr | 3);
213 if (ctrl->use_mdr)
214 out_be32(&lbc->mdr, ctrl->mdr);
215
216 dev_vdbg(ctrl->dev,
217 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
218 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
219 dev_vdbg(ctrl->dev,
220 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
221 "fbcr=%08x bank=%d\n",
222 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
223 in_be32(&lbc->fbcr), priv->bank);
224
225 ctrl->irq_status = 0;
226 /* execute special operation */
227 out_be32(&lbc->lsor, priv->bank);
228
229 /* wait for FCM complete flag or timeout */
230 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
231 FCM_TIMEOUT_MSECS * HZ/1000);
232 ctrl->status = ctrl->irq_status;
233
234 /* store mdr value in case it was needed */
235 if (ctrl->use_mdr)
236 ctrl->mdr = in_be32(&lbc->mdr);
237
238 ctrl->use_mdr = 0;
239
240 if (ctrl->status != LTESR_CC) {
241 dev_info(ctrl->dev,
242 "command failed: fir %x fcr %x status %x mdr %x\n",
243 in_be32(&lbc->fir), in_be32(&lbc->fcr),
244 ctrl->status, ctrl->mdr);
245 return -EIO;
246 }
247
248 return 0;
249 }
250
251 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
252 {
253 struct fsl_elbc_mtd *priv = chip->priv;
254 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
255 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
256
257 if (priv->page_size) {
258 out_be32(&lbc->fir,
259 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
260 (FIR_OP_CA << FIR_OP1_SHIFT) |
261 (FIR_OP_PA << FIR_OP2_SHIFT) |
262 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
263 (FIR_OP_RBW << FIR_OP4_SHIFT));
264
265 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
266 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
267 } else {
268 out_be32(&lbc->fir,
269 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
270 (FIR_OP_CA << FIR_OP1_SHIFT) |
271 (FIR_OP_PA << FIR_OP2_SHIFT) |
272 (FIR_OP_RBW << FIR_OP3_SHIFT));
273
274 if (oob)
275 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
276 else
277 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
278 }
279 }
280
281 /* cmdfunc send commands to the FCM */
282 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
283 int column, int page_addr)
284 {
285 struct nand_chip *chip = mtd->priv;
286 struct fsl_elbc_mtd *priv = chip->priv;
287 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
288 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
289
290 ctrl->use_mdr = 0;
291
292 /* clear the read buffer */
293 ctrl->read_bytes = 0;
294 if (command != NAND_CMD_PAGEPROG)
295 ctrl->index = 0;
296
297 switch (command) {
298 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
299 case NAND_CMD_READ1:
300 column += 256;
301
302 /* fall-through */
303 case NAND_CMD_READ0:
304 dev_dbg(ctrl->dev,
305 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
306 " 0x%x, column: 0x%x.\n", page_addr, column);
307
308
309 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
310 set_addr(mtd, 0, page_addr, 0);
311
312 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
313 ctrl->index += column;
314
315 fsl_elbc_do_read(chip, 0);
316 fsl_elbc_run_command(mtd);
317 return;
318
319 /* READOOB reads only the OOB because no ECC is performed. */
320 case NAND_CMD_READOOB:
321 dev_vdbg(ctrl->dev,
322 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
323 " 0x%x, column: 0x%x.\n", page_addr, column);
324
325 out_be32(&lbc->fbcr, mtd->oobsize - column);
326 set_addr(mtd, column, page_addr, 1);
327
328 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
329
330 fsl_elbc_do_read(chip, 1);
331 fsl_elbc_run_command(mtd);
332 return;
333
334 /* READID must read all 5 possible bytes while CEB is active */
335 case NAND_CMD_READID:
336 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
337
338 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
339 (FIR_OP_UA << FIR_OP1_SHIFT) |
340 (FIR_OP_RBW << FIR_OP2_SHIFT));
341 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
342 /* 5 bytes for manuf, device and exts */
343 out_be32(&lbc->fbcr, 5);
344 ctrl->read_bytes = 5;
345 ctrl->use_mdr = 1;
346 ctrl->mdr = 0;
347
348 set_addr(mtd, 0, 0, 0);
349 fsl_elbc_run_command(mtd);
350 return;
351
352 /* ERASE1 stores the block and page address */
353 case NAND_CMD_ERASE1:
354 dev_vdbg(ctrl->dev,
355 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
356 "page_addr: 0x%x.\n", page_addr);
357 set_addr(mtd, 0, page_addr, 0);
358 return;
359
360 /* ERASE2 uses the block and page address from ERASE1 */
361 case NAND_CMD_ERASE2:
362 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
363
364 out_be32(&lbc->fir,
365 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
366 (FIR_OP_PA << FIR_OP1_SHIFT) |
367 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
369 (FIR_OP_RS << FIR_OP4_SHIFT));
370
371 out_be32(&lbc->fcr,
372 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
373 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
374 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
375
376 out_be32(&lbc->fbcr, 0);
377 ctrl->read_bytes = 0;
378 ctrl->use_mdr = 1;
379
380 fsl_elbc_run_command(mtd);
381 return;
382
383 /* SEQIN sets up the addr buffer and all registers except the length */
384 case NAND_CMD_SEQIN: {
385 __be32 fcr;
386 dev_vdbg(ctrl->dev,
387 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
388 "page_addr: 0x%x, column: 0x%x.\n",
389 page_addr, column);
390
391 ctrl->column = column;
392 ctrl->oob = 0;
393 ctrl->use_mdr = 1;
394
395 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
396 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
397 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
398
399 if (priv->page_size) {
400 out_be32(&lbc->fir,
401 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
402 (FIR_OP_CA << FIR_OP1_SHIFT) |
403 (FIR_OP_PA << FIR_OP2_SHIFT) |
404 (FIR_OP_WB << FIR_OP3_SHIFT) |
405 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
406 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
407 (FIR_OP_RS << FIR_OP6_SHIFT));
408 } else {
409 out_be32(&lbc->fir,
410 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
411 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
412 (FIR_OP_CA << FIR_OP2_SHIFT) |
413 (FIR_OP_PA << FIR_OP3_SHIFT) |
414 (FIR_OP_WB << FIR_OP4_SHIFT) |
415 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
416 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
417 (FIR_OP_RS << FIR_OP7_SHIFT));
418
419 if (column >= mtd->writesize) {
420 /* OOB area --> READOOB */
421 column -= mtd->writesize;
422 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
423 ctrl->oob = 1;
424 } else {
425 WARN_ON(column != 0);
426 /* First 256 bytes --> READ0 */
427 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
428 }
429 }
430
431 out_be32(&lbc->fcr, fcr);
432 set_addr(mtd, column, page_addr, ctrl->oob);
433 return;
434 }
435
436 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
437 case NAND_CMD_PAGEPROG: {
438 int full_page;
439 dev_vdbg(ctrl->dev,
440 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
441 "writing %d bytes.\n", ctrl->index);
442
443 /* if the write did not start at 0 or is not a full page
444 * then set the exact length, otherwise use a full page
445 * write so the HW generates the ECC.
446 */
447 if (ctrl->oob || ctrl->column != 0 ||
448 ctrl->index != mtd->writesize + mtd->oobsize) {
449 out_be32(&lbc->fbcr, ctrl->index);
450 full_page = 0;
451 } else {
452 out_be32(&lbc->fbcr, 0);
453 full_page = 1;
454 }
455
456 fsl_elbc_run_command(mtd);
457
458 /* Read back the page in order to fill in the ECC for the
459 * caller. Is this really needed?
460 */
461 if (full_page && ctrl->oob_poi) {
462 out_be32(&lbc->fbcr, 3);
463 set_addr(mtd, 6, page_addr, 1);
464
465 ctrl->read_bytes = mtd->writesize + 9;
466
467 fsl_elbc_do_read(chip, 1);
468 fsl_elbc_run_command(mtd);
469
470 memcpy_fromio(ctrl->oob_poi + 6,
471 &ctrl->addr[ctrl->index], 3);
472 ctrl->index += 3;
473 }
474
475 ctrl->oob_poi = NULL;
476 return;
477 }
478
479 /* CMD_STATUS must read the status byte while CEB is active */
480 /* Note - it does not wait for the ready line */
481 case NAND_CMD_STATUS:
482 out_be32(&lbc->fir,
483 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
484 (FIR_OP_RBW << FIR_OP1_SHIFT));
485 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
486 out_be32(&lbc->fbcr, 1);
487 set_addr(mtd, 0, 0, 0);
488 ctrl->read_bytes = 1;
489
490 fsl_elbc_run_command(mtd);
491
492 /* The chip always seems to report that it is
493 * write-protected, even when it is not.
494 */
495 setbits8(ctrl->addr, NAND_STATUS_WP);
496 return;
497
498 /* RESET without waiting for the ready line */
499 case NAND_CMD_RESET:
500 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
501 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
502 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
503 fsl_elbc_run_command(mtd);
504 return;
505
506 default:
507 dev_err(ctrl->dev,
508 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
509 command);
510 }
511 }
512
513 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
514 {
515 /* The hardware does not seem to support multiple
516 * chips per bank.
517 */
518 }
519
520 /*
521 * Write buf to the FCM Controller Data Buffer
522 */
523 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
524 {
525 struct nand_chip *chip = mtd->priv;
526 struct fsl_elbc_mtd *priv = chip->priv;
527 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
528 unsigned int bufsize = mtd->writesize + mtd->oobsize;
529
530 if (len <= 0) {
531 dev_err(ctrl->dev, "write_buf of %d bytes", len);
532 ctrl->status = 0;
533 return;
534 }
535
536 if ((unsigned int)len > bufsize - ctrl->index) {
537 dev_err(ctrl->dev,
538 "write_buf beyond end of buffer "
539 "(%d requested, %u available)\n",
540 len, bufsize - ctrl->index);
541 len = bufsize - ctrl->index;
542 }
543
544 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
545 in_8(&ctrl->addr[ctrl->index] + len - 1);
546
547 ctrl->index += len;
548 }
549
550 /*
551 * read a byte from either the FCM hardware buffer if it has any data left
552 * otherwise issue a command to read a single byte.
553 */
554 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
555 {
556 struct nand_chip *chip = mtd->priv;
557 struct fsl_elbc_mtd *priv = chip->priv;
558 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
559
560 /* If there are still bytes in the FCM, then use the next byte. */
561 if (ctrl->index < ctrl->read_bytes)
562 return in_8(&ctrl->addr[ctrl->index++]);
563
564 dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
565 return ERR_BYTE;
566 }
567
568 /*
569 * Read from the FCM Controller Data Buffer
570 */
571 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
572 {
573 struct nand_chip *chip = mtd->priv;
574 struct fsl_elbc_mtd *priv = chip->priv;
575 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
576 int avail;
577
578 if (len < 0)
579 return;
580
581 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
582 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
583 ctrl->index += avail;
584
585 if (len > avail)
586 dev_err(ctrl->dev,
587 "read_buf beyond end of buffer "
588 "(%d requested, %d available)\n",
589 len, avail);
590 }
591
592 /*
593 * Verify buffer against the FCM Controller Data Buffer
594 */
595 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
596 {
597 struct nand_chip *chip = mtd->priv;
598 struct fsl_elbc_mtd *priv = chip->priv;
599 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
600 int i;
601
602 if (len < 0) {
603 dev_err(ctrl->dev, "write_buf of %d bytes", len);
604 return -EINVAL;
605 }
606
607 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
608 dev_err(ctrl->dev,
609 "verify_buf beyond end of buffer "
610 "(%d requested, %u available)\n",
611 len, ctrl->read_bytes - ctrl->index);
612
613 ctrl->index = ctrl->read_bytes;
614 return -EINVAL;
615 }
616
617 for (i = 0; i < len; i++)
618 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
619 break;
620
621 ctrl->index += len;
622 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
623 }
624
625 /* This function is called after Program and Erase Operations to
626 * check for success or failure.
627 */
628 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
629 {
630 struct fsl_elbc_mtd *priv = chip->priv;
631 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
632
633 if (ctrl->status != LTESR_CC)
634 return NAND_STATUS_FAIL;
635
636 /* The chip always seems to report that it is
637 * write-protected, even when it is not.
638 */
639 return (ctrl->mdr & 0xff) | NAND_STATUS_WP;
640 }
641
642 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
643 {
644 struct nand_chip *chip = mtd->priv;
645 struct fsl_elbc_mtd *priv = chip->priv;
646 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
647 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
648 unsigned int al;
649
650 /* calculate FMR Address Length field */
651 al = 0;
652 if (chip->pagemask & 0xffff0000)
653 al++;
654 if (chip->pagemask & 0xff000000)
655 al++;
656
657 /* add to ECCM mode set in fsl_elbc_init */
658 priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
659 (al << FMR_AL_SHIFT);
660
661 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
662 chip->numchips);
663 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
664 chip->chipsize);
665 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
666 chip->pagemask);
667 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
668 chip->chip_delay);
669 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
670 chip->badblockpos);
671 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
672 chip->chip_shift);
673 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
674 chip->page_shift);
675 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
676 chip->phys_erase_shift);
677 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
678 chip->ecclayout);
679 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
680 chip->ecc.mode);
681 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
682 chip->ecc.steps);
683 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
684 chip->ecc.bytes);
685 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
686 chip->ecc.total);
687 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
688 chip->ecc.layout);
689 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
690 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
691 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
692 mtd->erasesize);
693 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
694 mtd->writesize);
695 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
696 mtd->oobsize);
697
698 /* adjust Option Register and ECC to match Flash page size */
699 if (mtd->writesize == 512) {
700 priv->page_size = 0;
701 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
702 } else if (mtd->writesize == 2048) {
703 priv->page_size = 1;
704 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
705 /* adjust ecc setup if needed */
706 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
707 BR_DECC_CHK_GEN) {
708 chip->ecc.size = 512;
709 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
710 &fsl_elbc_oob_lp_eccm1 :
711 &fsl_elbc_oob_lp_eccm0;
712 chip->badblock_pattern = &largepage_memorybased;
713 }
714 } else {
715 dev_err(ctrl->dev,
716 "fsl_elbc_init: page size %d is not supported\n",
717 mtd->writesize);
718 return -1;
719 }
720
721 return 0;
722 }
723
724 static int fsl_elbc_read_page(struct mtd_info *mtd,
725 struct nand_chip *chip,
726 uint8_t *buf,
727 int page)
728 {
729 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
730 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
731
732 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
733 mtd->ecc_stats.failed++;
734
735 return 0;
736 }
737
738 /* ECC will be calculated automatically, and errors will be detected in
739 * waitfunc.
740 */
741 static void fsl_elbc_write_page(struct mtd_info *mtd,
742 struct nand_chip *chip,
743 const uint8_t *buf)
744 {
745 struct fsl_elbc_mtd *priv = chip->priv;
746 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
747
748 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
749 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
750
751 ctrl->oob_poi = chip->oob_poi;
752 }
753
754 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
755 {
756 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
757 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
758 struct nand_chip *chip = &priv->chip;
759
760 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
761
762 /* Fill in fsl_elbc_mtd structure */
763 priv->mtd.priv = chip;
764 priv->mtd.owner = THIS_MODULE;
765
766 /* Set the ECCM according to the settings in bootloader.*/
767 priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
768
769 /* fill in nand_chip structure */
770 /* set up function call table */
771 chip->read_byte = fsl_elbc_read_byte;
772 chip->write_buf = fsl_elbc_write_buf;
773 chip->read_buf = fsl_elbc_read_buf;
774 chip->verify_buf = fsl_elbc_verify_buf;
775 chip->select_chip = fsl_elbc_select_chip;
776 chip->cmdfunc = fsl_elbc_cmdfunc;
777 chip->waitfunc = fsl_elbc_wait;
778
779 chip->bbt_td = &bbt_main_descr;
780 chip->bbt_md = &bbt_mirror_descr;
781
782 /* set up nand options */
783 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
784 NAND_USE_FLASH_BBT;
785
786 chip->controller = &ctrl->controller;
787 chip->priv = priv;
788
789 chip->ecc.read_page = fsl_elbc_read_page;
790 chip->ecc.write_page = fsl_elbc_write_page;
791
792 /* If CS Base Register selects full hardware ECC then use it */
793 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
794 BR_DECC_CHK_GEN) {
795 chip->ecc.mode = NAND_ECC_HW;
796 /* put in small page settings and adjust later if needed */
797 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
798 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
799 chip->ecc.size = 512;
800 chip->ecc.bytes = 3;
801 } else {
802 /* otherwise fall back to default software ECC */
803 chip->ecc.mode = NAND_ECC_SOFT;
804 }
805
806 return 0;
807 }
808
809 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
810 {
811 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
812
813 nand_release(&priv->mtd);
814
815 kfree(priv->mtd.name);
816
817 if (priv->vbase)
818 iounmap(priv->vbase);
819
820 ctrl->chips[priv->bank] = NULL;
821 kfree(priv);
822
823 return 0;
824 }
825
826 static int __devinit fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
827 struct device_node *node)
828 {
829 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
830 struct fsl_elbc_mtd *priv;
831 struct resource res;
832 #ifdef CONFIG_MTD_PARTITIONS
833 static const char *part_probe_types[]
834 = { "cmdlinepart", "RedBoot", NULL };
835 struct mtd_partition *parts;
836 #endif
837 int ret;
838 int bank;
839
840 /* get, allocate and map the memory resource */
841 ret = of_address_to_resource(node, 0, &res);
842 if (ret) {
843 dev_err(ctrl->dev, "failed to get resource\n");
844 return ret;
845 }
846
847 /* find which chip select it is connected to */
848 for (bank = 0; bank < MAX_BANKS; bank++)
849 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
850 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
851 (in_be32(&lbc->bank[bank].br) &
852 in_be32(&lbc->bank[bank].or) & BR_BA)
853 == res.start)
854 break;
855
856 if (bank >= MAX_BANKS) {
857 dev_err(ctrl->dev, "address did not match any chip selects\n");
858 return -ENODEV;
859 }
860
861 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
862 if (!priv)
863 return -ENOMEM;
864
865 ctrl->chips[bank] = priv;
866 priv->bank = bank;
867 priv->ctrl = ctrl;
868 priv->dev = ctrl->dev;
869
870 priv->vbase = ioremap(res.start, resource_size(&res));
871 if (!priv->vbase) {
872 dev_err(ctrl->dev, "failed to map chip region\n");
873 ret = -ENOMEM;
874 goto err;
875 }
876
877 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
878 if (!priv->mtd.name) {
879 ret = -ENOMEM;
880 goto err;
881 }
882
883 ret = fsl_elbc_chip_init(priv);
884 if (ret)
885 goto err;
886
887 ret = nand_scan_ident(&priv->mtd, 1, NULL);
888 if (ret)
889 goto err;
890
891 ret = fsl_elbc_chip_init_tail(&priv->mtd);
892 if (ret)
893 goto err;
894
895 ret = nand_scan_tail(&priv->mtd);
896 if (ret)
897 goto err;
898
899 #ifdef CONFIG_MTD_PARTITIONS
900 /* First look for RedBoot table or partitions on the command
901 * line, these take precedence over device tree information */
902 ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
903 if (ret < 0)
904 goto err;
905
906 #ifdef CONFIG_MTD_OF_PARTS
907 if (ret == 0) {
908 ret = of_mtd_parse_partitions(priv->dev, node, &parts);
909 if (ret < 0)
910 goto err;
911 }
912 #endif
913
914 if (ret > 0)
915 add_mtd_partitions(&priv->mtd, parts, ret);
916 else
917 #endif
918 add_mtd_device(&priv->mtd);
919
920 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
921 (unsigned long long)res.start, priv->bank);
922 return 0;
923
924 err:
925 fsl_elbc_chip_remove(priv);
926 return ret;
927 }
928
929 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
930 {
931 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
932
933 /*
934 * NAND transactions can tie up the bus for a long time, so set the
935 * bus timeout to max by clearing LBCR[BMT] (highest base counter
936 * value) and setting LBCR[BMTPS] to the highest prescaler value.
937 */
938 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
939
940 /* clear event registers */
941 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
942 out_be32(&lbc->lteatr, 0);
943
944 /* Enable interrupts for any detected events */
945 out_be32(&lbc->lteir, LTESR_NAND_MASK);
946
947 ctrl->read_bytes = 0;
948 ctrl->index = 0;
949 ctrl->addr = NULL;
950
951 return 0;
952 }
953
954 static int fsl_elbc_ctrl_remove(struct platform_device *ofdev)
955 {
956 struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
957 int i;
958
959 for (i = 0; i < MAX_BANKS; i++)
960 if (ctrl->chips[i])
961 fsl_elbc_chip_remove(ctrl->chips[i]);
962
963 if (ctrl->irq)
964 free_irq(ctrl->irq, ctrl);
965
966 if (ctrl->regs)
967 iounmap(ctrl->regs);
968
969 dev_set_drvdata(&ofdev->dev, NULL);
970 kfree(ctrl);
971 return 0;
972 }
973
974 /* NOTE: This interrupt is also used to report other localbus events,
975 * such as transaction errors on other chipselects. If we want to
976 * capture those, we'll need to move the IRQ code into a shared
977 * LBC driver.
978 */
979
980 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
981 {
982 struct fsl_elbc_ctrl *ctrl = data;
983 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
984 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
985
986 if (status) {
987 out_be32(&lbc->ltesr, status);
988 out_be32(&lbc->lteatr, 0);
989
990 ctrl->irq_status = status;
991 smp_wmb();
992 wake_up(&ctrl->irq_wait);
993
994 return IRQ_HANDLED;
995 }
996
997 return IRQ_NONE;
998 }
999
1000 /* fsl_elbc_ctrl_probe
1001 *
1002 * called by device layer when it finds a device matching
1003 * one our driver can handled. This code allocates all of
1004 * the resources needed for the controller only. The
1005 * resources for the NAND banks themselves are allocated
1006 * in the chip probe function.
1007 */
1008
1009 static int __devinit fsl_elbc_ctrl_probe(struct platform_device *ofdev,
1010 const struct of_device_id *match)
1011 {
1012 struct device_node *child;
1013 struct fsl_elbc_ctrl *ctrl;
1014 int ret;
1015
1016 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1017 if (!ctrl)
1018 return -ENOMEM;
1019
1020 dev_set_drvdata(&ofdev->dev, ctrl);
1021
1022 spin_lock_init(&ctrl->controller.lock);
1023 init_waitqueue_head(&ctrl->controller.wq);
1024 init_waitqueue_head(&ctrl->irq_wait);
1025
1026 ctrl->regs = of_iomap(ofdev->dev.of_node, 0);
1027 if (!ctrl->regs) {
1028 dev_err(&ofdev->dev, "failed to get memory region\n");
1029 ret = -ENODEV;
1030 goto err;
1031 }
1032
1033 ctrl->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
1034 if (ctrl->irq == NO_IRQ) {
1035 dev_err(&ofdev->dev, "failed to get irq resource\n");
1036 ret = -ENODEV;
1037 goto err;
1038 }
1039
1040 ctrl->dev = &ofdev->dev;
1041
1042 ret = fsl_elbc_ctrl_init(ctrl);
1043 if (ret < 0)
1044 goto err;
1045
1046 ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1047 if (ret != 0) {
1048 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1049 ctrl->irq);
1050 ret = ctrl->irq;
1051 goto err;
1052 }
1053
1054 for_each_child_of_node(ofdev->dev.of_node, child)
1055 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1056 fsl_elbc_chip_probe(ctrl, child);
1057
1058 return 0;
1059
1060 err:
1061 fsl_elbc_ctrl_remove(ofdev);
1062 return ret;
1063 }
1064
1065 static const struct of_device_id fsl_elbc_match[] = {
1066 {
1067 .compatible = "fsl,elbc",
1068 },
1069 {}
1070 };
1071
1072 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1073 .driver = {
1074 .name = "fsl-elbc",
1075 .owner = THIS_MODULE,
1076 .of_match_table = fsl_elbc_match,
1077 },
1078 .probe = fsl_elbc_ctrl_probe,
1079 .remove = fsl_elbc_ctrl_remove,
1080 };
1081
1082 static int __init fsl_elbc_init(void)
1083 {
1084 return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1085 }
1086
1087 static void __exit fsl_elbc_exit(void)
1088 {
1089 of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1090 }
1091
1092 module_init(fsl_elbc_init);
1093 module_exit(fsl_elbc_exit);
1094
1095 MODULE_LICENSE("GPL");
1096 MODULE_AUTHOR("Freescale");
1097 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
Tomato firmware and modifications.