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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / media / video / em28xx / em28xx-core.c
blob631496c02d504a442e77460553e0273cf5938d51
1 /*
2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
3
4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
6 Mauro Carvalho Chehab <mchehab@infradead.org>
7 Sascha Sommer <saschasommer@freenet.de>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/usb.h>
29 #include <linux/vmalloc.h>
30 #include <media/v4l2-common.h>
31
32 #include "em28xx.h"
33
34 /* #define ENABLE_DEBUG_ISOC_FRAMES */
35
36 static unsigned int core_debug;
37 module_param(core_debug, int, 0644);
38 MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
39
40 #define em28xx_coredbg(fmt, arg...) do {\
41 if (core_debug) \
42 printk(KERN_INFO "%s %s :"fmt, \
43 dev->name, __func__ , ##arg); } while (0)
44
45 static unsigned int reg_debug;
46 module_param(reg_debug, int, 0644);
47 MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
48
49 #define em28xx_regdbg(fmt, arg...) do {\
50 if (reg_debug) \
51 printk(KERN_INFO "%s %s :"fmt, \
52 dev->name, __func__ , ##arg); } while (0)
53
54 static int alt;
55 module_param(alt, int, 0644);
56 MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
57
58 static unsigned int disable_vbi;
59 module_param(disable_vbi, int, 0644);
60 MODULE_PARM_DESC(disable_vbi, "disable vbi support");
61
62 #define em28xx_isocdbg(fmt, arg...) do {\
63 if (core_debug) \
64 printk(KERN_INFO "%s %s :"fmt, \
65 dev->name, __func__ , ##arg); } while (0)
66
67 /*
68 * em28xx_read_reg_req()
69 * reads data from the usb device specifying bRequest
70 */
71 int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
72 char *buf, int len)
73 {
74 int ret;
75 int pipe = usb_rcvctrlpipe(dev->udev, 0);
76
77 if (dev->state & DEV_DISCONNECTED)
78 return -ENODEV;
79
80 if (len > URB_MAX_CTRL_SIZE)
81 return -EINVAL;
82
83 if (reg_debug) {
84 printk(KERN_DEBUG "(pipe 0x%08x): "
85 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
86 pipe,
87 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
88 req, 0, 0,
89 reg & 0xff, reg >> 8,
90 len & 0xff, len >> 8);
91 }
92
93 mutex_lock(&dev->ctrl_urb_lock);
94 ret = usb_control_msg(dev->udev, pipe, req,
95 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
96 0x0000, reg, dev->urb_buf, len, HZ);
97 if (ret < 0) {
98 if (reg_debug)
99 printk(" failed!\n");
100 mutex_unlock(&dev->ctrl_urb_lock);
101 return ret;
102 }
103
104 if (len)
105 memcpy(buf, dev->urb_buf, len);
106
107 mutex_unlock(&dev->ctrl_urb_lock);
108
109 if (reg_debug) {
110 int byte;
111
112 printk("<<<");
113 for (byte = 0; byte < len; byte++)
114 printk(" %02x", (unsigned char)buf[byte]);
115 printk("\n");
116 }
117
118 return ret;
119 }
120
121 /*
122 * em28xx_read_reg_req()
123 * reads data from the usb device specifying bRequest
124 */
125 int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
126 {
127 int ret;
128 u8 val;
129
130 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
131 if (ret < 0)
132 return ret;
133
134 return val;
135 }
136
137 int em28xx_read_reg(struct em28xx *dev, u16 reg)
138 {
139 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
140 }
141
142 /*
143 * em28xx_write_regs_req()
144 * sends data to the usb device, specifying bRequest
145 */
146 int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
147 int len)
148 {
149 int ret;
150 int pipe = usb_sndctrlpipe(dev->udev, 0);
151
152 if (dev->state & DEV_DISCONNECTED)
153 return -ENODEV;
154
155 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
156 return -EINVAL;
157
158 if (reg_debug) {
159 int byte;
160
161 printk(KERN_DEBUG "(pipe 0x%08x): "
162 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
163 pipe,
164 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
165 req, 0, 0,
166 reg & 0xff, reg >> 8,
167 len & 0xff, len >> 8);
168
169 for (byte = 0; byte < len; byte++)
170 printk(" %02x", (unsigned char)buf[byte]);
171 printk("\n");
172 }
173
174 mutex_lock(&dev->ctrl_urb_lock);
175 memcpy(dev->urb_buf, buf, len);
176 ret = usb_control_msg(dev->udev, pipe, req,
177 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
178 0x0000, reg, dev->urb_buf, len, HZ);
179 mutex_unlock(&dev->ctrl_urb_lock);
180
181 if (dev->wait_after_write)
182 msleep(dev->wait_after_write);
183
184 return ret;
185 }
186
187 int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
188 {
189 int rc;
190
191 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
192
193 /* Stores GPO/GPIO values at the cache, if changed
194 Only write values should be stored, since input on a GPIO
195 register will return the input bits.
196 Not sure what happens on reading GPO register.
197 */
198 if (rc >= 0) {
199 if (reg == dev->reg_gpo_num)
200 dev->reg_gpo = buf[0];
201 else if (reg == dev->reg_gpio_num)
202 dev->reg_gpio = buf[0];
203 }
204
205 return rc;
206 }
207
208 /* Write a single register */
209 int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
210 {
211 return em28xx_write_regs(dev, reg, &val, 1);
212 }
213
214 /*
215 * em28xx_write_reg_bits()
216 * sets only some bits (specified by bitmask) of a register, by first reading
217 * the actual value
218 */
219 int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
220 u8 bitmask)
221 {
222 int oldval;
223 u8 newval;
224
225 /* Uses cache for gpo/gpio registers */
226 if (reg == dev->reg_gpo_num)
227 oldval = dev->reg_gpo;
228 else if (reg == dev->reg_gpio_num)
229 oldval = dev->reg_gpio;
230 else
231 oldval = em28xx_read_reg(dev, reg);
232
233 if (oldval < 0)
234 return oldval;
235
236 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
237
238 return em28xx_write_regs(dev, reg, &newval, 1);
239 }
240
241 /*
242 * em28xx_is_ac97_ready()
243 * Checks if ac97 is ready
244 */
245 static int em28xx_is_ac97_ready(struct em28xx *dev)
246 {
247 int ret, i;
248
249 /* Wait up to 50 ms for AC97 command to complete */
250 for (i = 0; i < 10; i++, msleep(5)) {
251 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
252 if (ret < 0)
253 return ret;
254
255 if (!(ret & 0x01))
256 return 0;
257 }
258
259 em28xx_warn("AC97 command still being executed: not handled properly!\n");
260 return -EBUSY;
261 }
262
263 /*
264 * em28xx_read_ac97()
265 * write a 16 bit value to the specified AC97 address (LSB first!)
266 */
267 int em28xx_read_ac97(struct em28xx *dev, u8 reg)
268 {
269 int ret;
270 u8 addr = (reg & 0x7f) | 0x80;
271 u16 val;
272
273 ret = em28xx_is_ac97_ready(dev);
274 if (ret < 0)
275 return ret;
276
277 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
278 if (ret < 0)
279 return ret;
280
281 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
282 (u8 *)&val, sizeof(val));
283
284 if (ret < 0)
285 return ret;
286 return le16_to_cpu(val);
287 }
288
289 /*
290 * em28xx_write_ac97()
291 * write a 16 bit value to the specified AC97 address (LSB first!)
292 */
293 int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
294 {
295 int ret;
296 u8 addr = reg & 0x7f;
297 __le16 value;
298
299 value = cpu_to_le16(val);
300
301 ret = em28xx_is_ac97_ready(dev);
302 if (ret < 0)
303 return ret;
304
305 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
306 if (ret < 0)
307 return ret;
308
309 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
310 if (ret < 0)
311 return ret;
312
313 return 0;
314 }
315
316 struct em28xx_vol_table {
317 enum em28xx_amux mux;
318 u8 reg;
319 };
320
321 static struct em28xx_vol_table inputs[] = {
322 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
323 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
324 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
325 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
326 { EM28XX_AMUX_CD, AC97_CD_VOL },
327 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
328 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
329 };
330
331 static int set_ac97_input(struct em28xx *dev)
332 {
333 int ret, i;
334 enum em28xx_amux amux = dev->ctl_ainput;
335
336 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
337 em28xx should point to LINE IN, while AC97 should use VIDEO
338 */
339 if (amux == EM28XX_AMUX_VIDEO2)
340 amux = EM28XX_AMUX_VIDEO;
341
342 /* Mute all entres but the one that were selected */
343 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
344 if (amux == inputs[i].mux)
345 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
346 else
347 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
348
349 if (ret < 0)
350 em28xx_warn("couldn't setup AC97 register %d\n",
351 inputs[i].reg);
352 }
353 return 0;
354 }
355
356 static int em28xx_set_audio_source(struct em28xx *dev)
357 {
358 int ret;
359 u8 input;
360
361 if (dev->board.is_em2800) {
362 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
363 input = EM2800_AUDIO_SRC_TUNER;
364 else
365 input = EM2800_AUDIO_SRC_LINE;
366
367 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
368 if (ret < 0)
369 return ret;
370 }
371
372 if (dev->board.has_msp34xx)
373 input = EM28XX_AUDIO_SRC_TUNER;
374 else {
375 switch (dev->ctl_ainput) {
376 case EM28XX_AMUX_VIDEO:
377 input = EM28XX_AUDIO_SRC_TUNER;
378 break;
379 default:
380 input = EM28XX_AUDIO_SRC_LINE;
381 break;
382 }
383 }
384
385 if (dev->board.mute_gpio && dev->mute)
386 em28xx_gpio_set(dev, dev->board.mute_gpio);
387 else
388 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
389
390 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
391 if (ret < 0)
392 return ret;
393 msleep(5);
394
395 switch (dev->audio_mode.ac97) {
396 case EM28XX_NO_AC97:
397 break;
398 default:
399 ret = set_ac97_input(dev);
400 }
401
402 return ret;
403 }
404
405 static const struct em28xx_vol_table outputs[] = {
406 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
407 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
408 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
409 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
410 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
411 };
412
413 int em28xx_audio_analog_set(struct em28xx *dev)
414 {
415 int ret, i;
416 u8 xclk;
417
418 if (!dev->audio_mode.has_audio)
419 return 0;
420
421 /* It is assumed that all devices use master volume for output.
422 It would be possible to use also line output.
423 */
424 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
425 /* Mute all outputs */
426 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
427 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
428 if (ret < 0)
429 em28xx_warn("couldn't setup AC97 register %d\n",
430 outputs[i].reg);
431 }
432 }
433
434 xclk = dev->board.xclk & 0x7f;
435 if (!dev->mute)
436 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
437
438 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
439 if (ret < 0)
440 return ret;
441 msleep(10);
442
443 /* Selects the proper audio input */
444 ret = em28xx_set_audio_source(dev);
445
446 /* Sets volume */
447 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
448 int vol;
449
450 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
451 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
452 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
453
454 /* LSB: left channel - both channels with the same level */
455 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
456
457 /* Mute device, if needed */
458 if (dev->mute)
459 vol |= 0x8000;
460
461 /* Sets volume */
462 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
463 if (dev->ctl_aoutput & outputs[i].mux)
464 ret = em28xx_write_ac97(dev, outputs[i].reg,
465 vol);
466 if (ret < 0)
467 em28xx_warn("couldn't setup AC97 register %d\n",
468 outputs[i].reg);
469 }
470
471 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
472 int sel = ac97_return_record_select(dev->ctl_aoutput);
473
474 /* Use the same input for both left and right
475 channels */
476 sel |= (sel << 8);
477
478 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
479 }
480 }
481
482 return ret;
483 }
484 EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
485
486 int em28xx_audio_setup(struct em28xx *dev)
487 {
488 int vid1, vid2, feat, cfg;
489 u32 vid;
490
491 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
492 /* Digital only device - don't load any alsa module */
493 dev->audio_mode.has_audio = 0;
494 dev->has_audio_class = 0;
495 dev->has_alsa_audio = 0;
496 return 0;
497 }
498
499 /* If device doesn't support Usb Audio Class, use vendor class */
500 if (!dev->has_audio_class)
501 dev->has_alsa_audio = 1;
502
503 dev->audio_mode.has_audio = 1;
504
505 /* See how this device is configured */
506 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
507 em28xx_info("Config register raw data: 0x%02x\n", cfg);
508 if (cfg < 0) {
509 /* Register read error? */
510 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
511 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
512 /* The device doesn't have vendor audio at all */
513 dev->has_alsa_audio = 0;
514 dev->audio_mode.has_audio = 0;
515 return 0;
516 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
517 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
518 em28xx_info("I2S Audio (3 sample rates)\n");
519 dev->audio_mode.i2s_3rates = 1;
520 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
521 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
522 em28xx_info("I2S Audio (5 sample rates)\n");
523 dev->audio_mode.i2s_5rates = 1;
524 }
525
526 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
527 /* Skip the code that does AC97 vendor detection */
528 dev->audio_mode.ac97 = EM28XX_NO_AC97;
529 goto init_audio;
530 }
531
532 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
533
534 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
535 if (vid1 < 0) {
536 /*
537 * Device likely doesn't support AC97
538 * Note: (some) em2800 devices without eeprom reports 0x91 on
539 * CHIPCFG register, even not having an AC97 chip
540 */
541 em28xx_warn("AC97 chip type couldn't be determined\n");
542 dev->audio_mode.ac97 = EM28XX_NO_AC97;
543 dev->has_alsa_audio = 0;
544 dev->audio_mode.has_audio = 0;
545 goto init_audio;
546 }
547
548 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
549 if (vid2 < 0)
550 goto init_audio;
551
552 vid = vid1 << 16 | vid2;
553
554 dev->audio_mode.ac97_vendor_id = vid;
555 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
556
557 feat = em28xx_read_ac97(dev, AC97_RESET);
558 if (feat < 0)
559 goto init_audio;
560
561 dev->audio_mode.ac97_feat = feat;
562 em28xx_warn("AC97 features = 0x%04x\n", feat);
563
564 /* Try to identify what audio processor we have */
565 if ((vid == 0xffffffff) && (feat == 0x6a90))
566 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
567 else if ((vid >> 8) == 0x838476)
568 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
569
570 init_audio:
571 /* Reports detected AC97 processor */
572 switch (dev->audio_mode.ac97) {
573 case EM28XX_NO_AC97:
574 em28xx_info("No AC97 audio processor\n");
575 break;
576 case EM28XX_AC97_EM202:
577 em28xx_info("Empia 202 AC97 audio processor detected\n");
578 break;
579 case EM28XX_AC97_SIGMATEL:
580 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
581 dev->audio_mode.ac97_vendor_id & 0xff);
582 break;
583 case EM28XX_AC97_OTHER:
584 em28xx_warn("Unknown AC97 audio processor detected!\n");
585 break;
586 default:
587 break;
588 }
589
590 return em28xx_audio_analog_set(dev);
591 }
592 EXPORT_SYMBOL_GPL(em28xx_audio_setup);
593
594 int em28xx_colorlevels_set_default(struct em28xx *dev)
595 {
596 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
597 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
598 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
599 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
600 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
601 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
602
603 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
604 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
605 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
606 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
607 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
608 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
609 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
610 }
611
612 int em28xx_capture_start(struct em28xx *dev, int start)
613 {
614 int rc;
615
616 if (dev->chip_id == CHIP_ID_EM2874) {
617 /* The Transport Stream Enable Register moved in em2874 */
618 if (!start) {
619 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
620 0x00,
621 EM2874_TS1_CAPTURE_ENABLE);
622 return rc;
623 }
624
625 /* Enable Transport Stream */
626 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
627 EM2874_TS1_CAPTURE_ENABLE,
628 EM2874_TS1_CAPTURE_ENABLE);
629 return rc;
630 }
631
632
633 /* video registers are sampled by VREF */
634 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
635 start ? 0x10 : 0x00, 0x10);
636 if (rc < 0)
637 return rc;
638
639 if (!start) {
640 /* disable video capture */
641 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
642 return rc;
643 }
644
645 if (dev->board.is_webcam)
646 rc = em28xx_write_reg(dev, 0x13, 0x0c);
647
648 /* enable video capture */
649 rc = em28xx_write_reg(dev, 0x48, 0x00);
650
651 if (dev->mode == EM28XX_ANALOG_MODE)
652 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
653 else
654 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
655
656 msleep(6);
657
658 return rc;
659 }
660
661 int em28xx_vbi_supported(struct em28xx *dev)
662 {
663 /* Modprobe option to manually disable */
664 if (disable_vbi == 1)
665 return 0;
666
667 if (dev->chip_id == CHIP_ID_EM2860 ||
668 dev->chip_id == CHIP_ID_EM2883)
669 return 1;
670
671 /* Version of em28xx that does not support VBI */
672 return 0;
673 }
674
675 int em28xx_set_outfmt(struct em28xx *dev)
676 {
677 int ret;
678 u8 vinctrl;
679
680 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
681 dev->format->reg | 0x20, 0xff);
682 if (ret < 0)
683 return ret;
684
685 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
686 if (ret < 0)
687 return ret;
688
689 vinctrl = dev->vinctl;
690 if (em28xx_vbi_supported(dev) == 1) {
691 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
692 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
693 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
694 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
695 if (dev->norm & V4L2_STD_525_60) {
696 /* NTSC */
697 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
698 } else if (dev->norm & V4L2_STD_625_50) {
699 /* PAL */
700 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
701 }
702 }
703
704 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
705 }
706
707 static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
708 u8 ymin, u8 ymax)
709 {
710 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
711 xmin, ymin, xmax, ymax);
712
713 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
714 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
715 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
716 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
717 }
718
719 static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
720 u16 width, u16 height)
721 {
722 u8 cwidth = width;
723 u8 cheight = height;
724 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
725
726 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
727 (width | (overflow & 2) << 7),
728 (height | (overflow & 1) << 8));
729
730 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
731 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
732 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
733 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
734 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
735 }
736
737 static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
738 {
739 u8 mode;
740 /* the em2800 scaler only supports scaling down to 50% */
741
742 if (dev->board.is_em2800) {
743 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
744 } else {
745 u8 buf[2];
746
747 buf[0] = h;
748 buf[1] = h >> 8;
749 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
750
751 buf[0] = v;
752 buf[1] = v >> 8;
753 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
754 /* it seems that both H and V scalers must be active
755 to work correctly */
756 mode = (h || v) ? 0x30 : 0x00;
757 }
758 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
759 }
760
761 int em28xx_resolution_set(struct em28xx *dev)
762 {
763 int width, height;
764 width = norm_maxw(dev);
765 height = norm_maxh(dev);
766
767 /* Properly setup VBI */
768 dev->vbi_width = 720;
769 if (dev->norm & V4L2_STD_525_60)
770 dev->vbi_height = 12;
771 else
772 dev->vbi_height = 18;
773
774 if (!dev->progressive)
775 height >>= norm_maxh(dev);
776
777 em28xx_set_outfmt(dev);
778
779
780 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
781
782 /* If we don't set the start position to 2 in VBI mode, we end up
783 with line 20/21 being YUYV encoded instead of being in 8-bit
784 greyscale. The core of the issue is that line 21 (and line 23 for
785 PAL WSS) are inside of active video region, and as a result they
786 get the pixelformatting associated with that area. So by cropping
787 it out, we end up with the same format as the rest of the VBI
788 region */
789 if (em28xx_vbi_supported(dev) == 1)
790 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
791 else
792 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
793
794 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
795 }
796
797 int em28xx_set_alternate(struct em28xx *dev)
798 {
799 int errCode, prev_alt = dev->alt;
800 int i;
801 unsigned int min_pkt_size = dev->width * 2 + 4;
802
803 /*
804 * alt = 0 is used only for control messages, so, only values
805 * greater than 0 can be used for streaming.
806 */
807 if (alt && alt < dev->num_alt) {
808 em28xx_coredbg("alternate forced to %d\n", dev->alt);
809 dev->alt = alt;
810 goto set_alt;
811 }
812
813 /* When image size is bigger than a certain value,
814 the frame size should be increased, otherwise, only
815 green screen will be received.
816 */
817 if (dev->width * 2 * dev->height > 720 * 240 * 2)
818 min_pkt_size *= 2;
819
820 for (i = 0; i < dev->num_alt; i++) {
821 /* stop when the selected alt setting offers enough bandwidth */
822 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
823 dev->alt = i;
824 break;
825 /* otherwise make sure that we end up with the maximum bandwidth
826 because the min_pkt_size equation might be wrong...
827 */
828 } else if (dev->alt_max_pkt_size[i] >
829 dev->alt_max_pkt_size[dev->alt])
830 dev->alt = i;
831 }
832
833 set_alt:
834 if (dev->alt != prev_alt) {
835 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
836 min_pkt_size, dev->alt);
837 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
838 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
839 dev->alt, dev->max_pkt_size);
840 errCode = usb_set_interface(dev->udev, 0, dev->alt);
841 if (errCode < 0) {
842 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
843 dev->alt, errCode);
844 return errCode;
845 }
846 }
847 return 0;
848 }
849
850 int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
851 {
852 int rc = 0;
853
854 if (!gpio)
855 return rc;
856
857 if (dev->mode != EM28XX_SUSPEND) {
858 em28xx_write_reg(dev, 0x48, 0x00);
859 if (dev->mode == EM28XX_ANALOG_MODE)
860 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
861 else
862 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
863 msleep(6);
864 }
865
866 /* Send GPIO reset sequences specified at board entry */
867 while (gpio->sleep >= 0) {
868 if (gpio->reg >= 0) {
869 rc = em28xx_write_reg_bits(dev,
870 gpio->reg,
871 gpio->val,
872 gpio->mask);
873 if (rc < 0)
874 return rc;
875 }
876 if (gpio->sleep > 0)
877 msleep(gpio->sleep);
878
879 gpio++;
880 }
881 return rc;
882 }
883
884 int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
885 {
886 if (dev->mode == set_mode)
887 return 0;
888
889 if (set_mode == EM28XX_SUSPEND) {
890 dev->mode = set_mode;
891
892
893 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
894 }
895
896 dev->mode = set_mode;
897
898 if (dev->mode == EM28XX_DIGITAL_MODE)
899 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
900 else
901 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
902 }
903 EXPORT_SYMBOL_GPL(em28xx_set_mode);
904
905 /* ------------------------------------------------------------------
906 URB control
907 ------------------------------------------------------------------*/
908
909 /*
910 * IRQ callback, called by URB callback
911 */
912 static void em28xx_irq_callback(struct urb *urb)
913 {
914 struct em28xx *dev = urb->context;
915 int rc, i;
916
917 switch (urb->status) {
918 case 0: /* success */
919 case -ETIMEDOUT: /* NAK */
920 break;
921 case -ECONNRESET: /* kill */
922 case -ENOENT:
923 case -ESHUTDOWN:
924 return;
925 default: /* error */
926 em28xx_isocdbg("urb completition error %d.\n", urb->status);
927 break;
928 }
929
930 /* Copy data from URB */
931 spin_lock(&dev->slock);
932 rc = dev->isoc_ctl.isoc_copy(dev, urb);
933 spin_unlock(&dev->slock);
934
935 /* Reset urb buffers */
936 for (i = 0; i < urb->number_of_packets; i++) {
937 urb->iso_frame_desc[i].status = 0;
938 urb->iso_frame_desc[i].actual_length = 0;
939 }
940 urb->status = 0;
941
942 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
943 if (urb->status) {
944 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
945 urb->status);
946 }
947 }
948
949 /*
950 * Stop and Deallocate URBs
951 */
952 void em28xx_uninit_isoc(struct em28xx *dev)
953 {
954 struct urb *urb;
955 int i;
956
957 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
958
959 dev->isoc_ctl.nfields = -1;
960 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
961 urb = dev->isoc_ctl.urb[i];
962 if (urb) {
963 if (!irqs_disabled())
964 usb_kill_urb(urb);
965 else
966 usb_unlink_urb(urb);
967
968 if (dev->isoc_ctl.transfer_buffer[i]) {
969 usb_free_coherent(dev->udev,
970 urb->transfer_buffer_length,
971 dev->isoc_ctl.transfer_buffer[i],
972 urb->transfer_dma);
973 }
974 usb_free_urb(urb);
975 dev->isoc_ctl.urb[i] = NULL;
976 }
977 dev->isoc_ctl.transfer_buffer[i] = NULL;
978 }
979
980 kfree(dev->isoc_ctl.urb);
981 kfree(dev->isoc_ctl.transfer_buffer);
982
983 dev->isoc_ctl.urb = NULL;
984 dev->isoc_ctl.transfer_buffer = NULL;
985 dev->isoc_ctl.num_bufs = 0;
986
987 em28xx_capture_start(dev, 0);
988 }
989 EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
990
991 /*
992 * Allocate URBs and start IRQ
993 */
994 int em28xx_init_isoc(struct em28xx *dev, int max_packets,
995 int num_bufs, int max_pkt_size,
996 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
997 {
998 struct em28xx_dmaqueue *dma_q = &dev->vidq;
999 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1000 int i;
1001 int sb_size, pipe;
1002 struct urb *urb;
1003 int j, k;
1004 int rc;
1005
1006 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
1007
1008 /* De-allocates all pending stuff */
1009 em28xx_uninit_isoc(dev);
1010
1011 dev->isoc_ctl.isoc_copy = isoc_copy;
1012 dev->isoc_ctl.num_bufs = num_bufs;
1013
1014 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1015 if (!dev->isoc_ctl.urb) {
1016 em28xx_errdev("cannot alloc memory for usb buffers\n");
1017 return -ENOMEM;
1018 }
1019
1020 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1021 GFP_KERNEL);
1022 if (!dev->isoc_ctl.transfer_buffer) {
1023 em28xx_errdev("cannot allocate memory for usb transfer\n");
1024 kfree(dev->isoc_ctl.urb);
1025 return -ENOMEM;
1026 }
1027
1028 dev->isoc_ctl.max_pkt_size = max_pkt_size;
1029 dev->isoc_ctl.vid_buf = NULL;
1030 dev->isoc_ctl.vbi_buf = NULL;
1031
1032 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
1033
1034 /* allocate urbs and transfer buffers */
1035 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1036 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
1037 if (!urb) {
1038 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
1039 em28xx_uninit_isoc(dev);
1040 return -ENOMEM;
1041 }
1042 dev->isoc_ctl.urb[i] = urb;
1043
1044 dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev,
1045 sb_size, GFP_KERNEL, &urb->transfer_dma);
1046 if (!dev->isoc_ctl.transfer_buffer[i]) {
1047 em28xx_err("unable to allocate %i bytes for transfer"
1048 " buffer %i%s\n",
1049 sb_size, i,
1050 in_interrupt() ? " while in int" : "");
1051 em28xx_uninit_isoc(dev);
1052 return -ENOMEM;
1053 }
1054 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
1055
1056 pipe = usb_rcvisocpipe(dev->udev,
1057 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
1058
1059 usb_fill_int_urb(urb, dev->udev, pipe,
1060 dev->isoc_ctl.transfer_buffer[i], sb_size,
1061 em28xx_irq_callback, dev, 1);
1062
1063 urb->number_of_packets = max_packets;
1064 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
1065
1066 k = 0;
1067 for (j = 0; j < max_packets; j++) {
1068 urb->iso_frame_desc[j].offset = k;
1069 urb->iso_frame_desc[j].length =
1070 dev->isoc_ctl.max_pkt_size;
1071 k += dev->isoc_ctl.max_pkt_size;
1072 }
1073 }
1074
1075 init_waitqueue_head(&dma_q->wq);
1076 init_waitqueue_head(&vbi_dma_q->wq);
1077
1078 em28xx_capture_start(dev, 1);
1079
1080 /* submit urbs and enables IRQ */
1081 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1082 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1083 if (rc) {
1084 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1085 rc);
1086 em28xx_uninit_isoc(dev);
1087 return rc;
1088 }
1089 }
1090
1091 return 0;
1092 }
1093 EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1094
1095 /* Determine the packet size for the DVB stream for the given device
1096 (underlying value programmed into the eeprom) */
1097 int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
1098 {
1099 unsigned int chip_cfg2;
1100 unsigned int packet_size = 564;
1101
1102 if (dev->chip_id == CHIP_ID_EM2874) {
1103 packet_size = 564;
1104 } else {
1105 /* TS max packet size stored in bits 1-0 of R01 */
1106 chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
1107 switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
1108 case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
1109 packet_size = 188;
1110 break;
1111 case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
1112 packet_size = 376;
1113 break;
1114 case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
1115 packet_size = 564;
1116 break;
1117 case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
1118 packet_size = 752;
1119 break;
1120 }
1121 }
1122
1123 em28xx_coredbg("dvb max packet size=%d\n", packet_size);
1124 return packet_size;
1125 }
1126 EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
1127
1128 /*
1129 * em28xx_wake_i2c()
1130 * configure i2c attached devices
1131 */
1132 void em28xx_wake_i2c(struct em28xx *dev)
1133 {
1134 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1135 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1136 INPUT(dev->ctl_input)->vmux, 0, 0);
1137 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1138 }
1139
1140 /*
1141 * Device control list
1142 */
1143
1144 static LIST_HEAD(em28xx_devlist);
1145 static DEFINE_MUTEX(em28xx_devlist_mutex);
1146
1147 /*
1148 * em28xx_realease_resources()
1149 * unregisters the v4l2,i2c and usb devices
1150 * called when the device gets disconected or at module unload
1151 */
1152 void em28xx_remove_from_devlist(struct em28xx *dev)
1153 {
1154 mutex_lock(&em28xx_devlist_mutex);
1155 list_del(&dev->devlist);
1156 mutex_unlock(&em28xx_devlist_mutex);
1157 };
1158
1159 void em28xx_add_into_devlist(struct em28xx *dev)
1160 {
1161 mutex_lock(&em28xx_devlist_mutex);
1162 list_add_tail(&dev->devlist, &em28xx_devlist);
1163 mutex_unlock(&em28xx_devlist_mutex);
1164 };
1165
1166 /*
1167 * Extension interface
1168 */
1169
1170 static LIST_HEAD(em28xx_extension_devlist);
1171
1172 int em28xx_register_extension(struct em28xx_ops *ops)
1173 {
1174 struct em28xx *dev = NULL;
1175
1176 mutex_lock(&em28xx_devlist_mutex);
1177 list_add_tail(&ops->next, &em28xx_extension_devlist);
1178 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1179 ops->init(dev);
1180 }
1181 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1182 mutex_unlock(&em28xx_devlist_mutex);
1183 return 0;
1184 }
1185 EXPORT_SYMBOL(em28xx_register_extension);
1186
1187 void em28xx_unregister_extension(struct em28xx_ops *ops)
1188 {
1189 struct em28xx *dev = NULL;
1190
1191 mutex_lock(&em28xx_devlist_mutex);
1192 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1193 ops->fini(dev);
1194 }
1195 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1196 list_del(&ops->next);
1197 mutex_unlock(&em28xx_devlist_mutex);
1198 }
1199 EXPORT_SYMBOL(em28xx_unregister_extension);
1200
1201 void em28xx_init_extension(struct em28xx *dev)
1202 {
1203 struct em28xx_ops *ops = NULL;
1204
1205 mutex_lock(&em28xx_devlist_mutex);
1206 if (!list_empty(&em28xx_extension_devlist)) {
1207 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1208 if (ops->init)
1209 ops->init(dev);
1210 }
1211 }
1212 mutex_unlock(&em28xx_devlist_mutex);
1213 }
1214
1215 void em28xx_close_extension(struct em28xx *dev)
1216 {
1217 struct em28xx_ops *ops = NULL;
1218
1219 mutex_lock(&em28xx_devlist_mutex);
1220 if (!list_empty(&em28xx_extension_devlist)) {
1221 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1222 if (ops->fini)
1223 ops->fini(dev);
1224 }
1225 }
1226 mutex_unlock(&em28xx_devlist_mutex);
1227 }
Tomato firmware and modifications.