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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / media / video / cx23885 / cx23888-ir.c
blob52e3432bf244c3e32da89049f677d3cc0e7be234
1 /*
2 * Driver for the Conexant CX23885/7/8 PCIe bridge
3 *
4 * CX23888 Integrated Consumer Infrared Controller
5 *
6 * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA.
22 */
23
24 #include <linux/kfifo.h>
25 #include <linux/slab.h>
26
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-chip-ident.h>
29 #include <media/ir-core.h>
30
31 #include "cx23885.h"
32
33 static unsigned int ir_888_debug;
34 module_param(ir_888_debug, int, 0644);
35 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
36
37 #define CX23888_IR_REG_BASE 0x170000
38 /*
39 * These CX23888 register offsets have a straightforward one to one mapping
40 * to the CX23885 register offsets of 0x200 through 0x218
41 */
42 #define CX23888_IR_CNTRL_REG 0x170000
43 #define CNTRL_WIN_3_3 0x00000000
44 #define CNTRL_WIN_4_3 0x00000001
45 #define CNTRL_WIN_3_4 0x00000002
46 #define CNTRL_WIN_4_4 0x00000003
47 #define CNTRL_WIN 0x00000003
48 #define CNTRL_EDG_NONE 0x00000000
49 #define CNTRL_EDG_FALL 0x00000004
50 #define CNTRL_EDG_RISE 0x00000008
51 #define CNTRL_EDG_BOTH 0x0000000C
52 #define CNTRL_EDG 0x0000000C
53 #define CNTRL_DMD 0x00000010
54 #define CNTRL_MOD 0x00000020
55 #define CNTRL_RFE 0x00000040
56 #define CNTRL_TFE 0x00000080
57 #define CNTRL_RXE 0x00000100
58 #define CNTRL_TXE 0x00000200
59 #define CNTRL_RIC 0x00000400
60 #define CNTRL_TIC 0x00000800
61 #define CNTRL_CPL 0x00001000
62 #define CNTRL_LBM 0x00002000
63 #define CNTRL_R 0x00004000
64 /* CX23888 specific control flag */
65 #define CNTRL_IVO 0x00008000
66
67 #define CX23888_IR_TXCLK_REG 0x170004
68 #define TXCLK_TCD 0x0000FFFF
69
70 #define CX23888_IR_RXCLK_REG 0x170008
71 #define RXCLK_RCD 0x0000FFFF
72
73 #define CX23888_IR_CDUTY_REG 0x17000C
74 #define CDUTY_CDC 0x0000000F
75
76 #define CX23888_IR_STATS_REG 0x170010
77 #define STATS_RTO 0x00000001
78 #define STATS_ROR 0x00000002
79 #define STATS_RBY 0x00000004
80 #define STATS_TBY 0x00000008
81 #define STATS_RSR 0x00000010
82 #define STATS_TSR 0x00000020
83
84 #define CX23888_IR_IRQEN_REG 0x170014
85 #define IRQEN_RTE 0x00000001
86 #define IRQEN_ROE 0x00000002
87 #define IRQEN_RSE 0x00000010
88 #define IRQEN_TSE 0x00000020
89
90 #define CX23888_IR_FILTR_REG 0x170018
91 #define FILTR_LPF 0x0000FFFF
92
93 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
94 #define CX23888_IR_FIFO_REG 0x170040
95 #define FIFO_RXTX 0x0000FFFF
96 #define FIFO_RXTX_LVL 0x00010000
97 #define FIFO_RXTX_RTO 0x0001FFFF
98 #define FIFO_RX_NDV 0x00020000
99 #define FIFO_RX_DEPTH 8
100 #define FIFO_TX_DEPTH 8
101
102 /* CX23888 unique registers */
103 #define CX23888_IR_SEEDP_REG 0x17001C
104 #define CX23888_IR_TIMOL_REG 0x170020
105 #define CX23888_IR_WAKE0_REG 0x170024
106 #define CX23888_IR_WAKE1_REG 0x170028
107 #define CX23888_IR_WAKE2_REG 0x17002C
108 #define CX23888_IR_MASK0_REG 0x170030
109 #define CX23888_IR_MASK1_REG 0x170034
110 #define CX23888_IR_MAKS2_REG 0x170038
111 #define CX23888_IR_DPIPG_REG 0x17003C
112 #define CX23888_IR_LEARN_REG 0x170044
113
114 #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
115 #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
116
117 /*
118 * We use this union internally for convenience, but callers to tx_write
119 * and rx_read will be expecting records of type struct ir_raw_event.
120 * Always ensure the size of this union is dictated by struct ir_raw_event.
121 */
122 union cx23888_ir_fifo_rec {
123 u32 hw_fifo_data;
124 struct ir_raw_event ir_core_data;
125 };
126
127 #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
128 #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
129
130 struct cx23888_ir_state {
131 struct v4l2_subdev sd;
132 struct cx23885_dev *dev;
133 u32 id;
134 u32 rev;
135
136 struct v4l2_subdev_ir_parameters rx_params;
137 struct mutex rx_params_lock;
138 atomic_t rxclk_divider;
139 atomic_t rx_invert;
140
141 struct kfifo rx_kfifo;
142 spinlock_t rx_kfifo_lock;
143
144 struct v4l2_subdev_ir_parameters tx_params;
145 struct mutex tx_params_lock;
146 atomic_t txclk_divider;
147 };
148
149 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
150 {
151 return v4l2_get_subdevdata(sd);
152 }
153
154 /*
155 * IR register block read and write functions
156 */
157 static
158 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
159 {
160 cx_write(addr, value);
161 return 0;
162 }
163
164 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
165 {
166 return cx_read(addr);
167 }
168
169 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
170 u32 and_mask, u32 or_value)
171 {
172 cx_andor(addr, ~and_mask, or_value);
173 return 0;
174 }
175
176 /*
177 * Rx and Tx Clock Divider register computations
178 *
179 * Note the largest clock divider value of 0xffff corresponds to:
180 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
181 * which fits in 21 bits, so we'll use unsigned int for time arguments.
182 */
183 static inline u16 count_to_clock_divider(unsigned int d)
184 {
185 if (d > RXCLK_RCD + 1)
186 d = RXCLK_RCD;
187 else if (d < 2)
188 d = 1;
189 else
190 d--;
191 return (u16) d;
192 }
193
194 static inline u16 ns_to_clock_divider(unsigned int ns)
195 {
196 return count_to_clock_divider(
197 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
198 }
199
200 static inline unsigned int clock_divider_to_ns(unsigned int divider)
201 {
202 /* Period of the Rx or Tx clock in ns */
203 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
204 CX23888_IR_REFCLK_FREQ / 1000000);
205 }
206
207 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
208 {
209 return count_to_clock_divider(
210 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
211 }
212
213 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
214 {
215 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
216 }
217
218 static inline u16 freq_to_clock_divider(unsigned int freq,
219 unsigned int rollovers)
220 {
221 return count_to_clock_divider(
222 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
223 }
224
225 static inline unsigned int clock_divider_to_freq(unsigned int divider,
226 unsigned int rollovers)
227 {
228 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
229 (divider + 1) * rollovers);
230 }
231
232 /*
233 * Low Pass Filter register calculations
234 *
235 * Note the largest count value of 0xffff corresponds to:
236 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
237 * which fits in 21 bits, so we'll use unsigned int for time arguments.
238 */
239 static inline u16 count_to_lpf_count(unsigned int d)
240 {
241 if (d > FILTR_LPF)
242 d = FILTR_LPF;
243 else if (d < 4)
244 d = 0;
245 return (u16) d;
246 }
247
248 static inline u16 ns_to_lpf_count(unsigned int ns)
249 {
250 return count_to_lpf_count(
251 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
252 }
253
254 static inline unsigned int lpf_count_to_ns(unsigned int count)
255 {
256 /* Duration of the Low Pass Filter rejection window in ns */
257 return DIV_ROUND_CLOSEST(count * 1000,
258 CX23888_IR_REFCLK_FREQ / 1000000);
259 }
260
261 static inline unsigned int lpf_count_to_us(unsigned int count)
262 {
263 /* Duration of the Low Pass Filter rejection window in us */
264 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
265 }
266
267 /*
268 * FIFO register pulse width count compuations
269 */
270 static u32 clock_divider_to_resolution(u16 divider)
271 {
272 /*
273 * Resolution is the duration of 1 tick of the readable portion of
274 * of the pulse width counter as read from the FIFO. The two lsb's are
275 * not readable, hence the << 2. This function returns ns.
276 */
277 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
278 CX23888_IR_REFCLK_FREQ / 1000000);
279 }
280
281 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
282 {
283 u64 n;
284 u32 rem;
285
286 /*
287 * The 2 lsb's of the pulse width timer count are not readable, hence
288 * the (count << 2) | 0x3
289 */
290 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
291 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
292 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
293 n++;
294 return n;
295 }
296
297 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
298 {
299 u64 n;
300 u32 rem;
301
302 /*
303 * The 2 lsb's of the pulse width timer count are not readable, hence
304 * the (count << 2) | 0x3
305 */
306 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
307 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
308 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
309 n++;
310 return (unsigned int) n;
311 }
312
313 /*
314 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
315 *
316 * The total pulse clock count is an 18 bit pulse width timer count as the most
317 * significant part and (up to) 16 bit clock divider count as a modulus.
318 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
319 * width timer count's least significant bit.
320 */
321 static u64 ns_to_pulse_clocks(u32 ns)
322 {
323 u64 clocks;
324 u32 rem;
325 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
326 rem = do_div(clocks, 1000); /* /1000 = cycles */
327 if (rem >= 1000 / 2)
328 clocks++;
329 return clocks;
330 }
331
332 static u16 pulse_clocks_to_clock_divider(u64 count)
333 {
334 u32 rem;
335
336 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
337
338 /* net result needs to be rounded down and decremented by 1 */
339 if (count > RXCLK_RCD + 1)
340 count = RXCLK_RCD;
341 else if (count < 2)
342 count = 1;
343 else
344 count--;
345 return (u16) count;
346 }
347
348 /*
349 * IR Control Register helpers
350 */
351 enum tx_fifo_watermark {
352 TX_FIFO_HALF_EMPTY = 0,
353 TX_FIFO_EMPTY = CNTRL_TIC,
354 };
355
356 enum rx_fifo_watermark {
357 RX_FIFO_HALF_FULL = 0,
358 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
359 };
360
361 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
362 enum tx_fifo_watermark level)
363 {
364 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
365 }
366
367 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
368 enum rx_fifo_watermark level)
369 {
370 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
371 }
372
373 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
374 {
375 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
376 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
377 }
378
379 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
380 {
381 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
382 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
383 }
384
385 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
386 bool enable)
387 {
388 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
389 enable ? CNTRL_MOD : 0);
390 }
391
392 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
393 bool enable)
394 {
395 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
396 enable ? CNTRL_DMD : 0);
397 }
398
399 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
400 u32 edge_types)
401 {
402 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
403 edge_types & CNTRL_EDG_BOTH);
404 }
405
406 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
407 unsigned int carrier,
408 unsigned int *carrier_range_low,
409 unsigned int *carrier_range_high)
410 {
411 u32 v;
412 unsigned int c16 = carrier * 16;
413
414 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
415 v = CNTRL_WIN_3_4;
416 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
417 } else {
418 v = CNTRL_WIN_3_3;
419 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
420 }
421
422 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
423 v |= CNTRL_WIN_4_3;
424 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
425 } else {
426 v |= CNTRL_WIN_3_3;
427 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
428 }
429 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
430 }
431
432 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
433 bool invert)
434 {
435 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
436 invert ? CNTRL_CPL : 0);
437 }
438
439 static inline void control_tx_level_invert(struct cx23885_dev *dev,
440 bool invert)
441 {
442 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
443 invert ? CNTRL_IVO : 0);
444 }
445
446 /*
447 * IR Rx & Tx Clock Register helpers
448 */
449 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
450 unsigned int freq,
451 u16 *divider)
452 {
453 *divider = carrier_freq_to_clock_divider(freq);
454 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
455 return clock_divider_to_carrier_freq(*divider);
456 }
457
458 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
459 unsigned int freq,
460 u16 *divider)
461 {
462 *divider = carrier_freq_to_clock_divider(freq);
463 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
464 return clock_divider_to_carrier_freq(*divider);
465 }
466
467 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
468 u16 *divider)
469 {
470 u64 pulse_clocks;
471
472 if (ns > IR_MAX_DURATION)
473 ns = IR_MAX_DURATION;
474 pulse_clocks = ns_to_pulse_clocks(ns);
475 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
476 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
477 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
478 }
479
480 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
481 u16 *divider)
482 {
483 u64 pulse_clocks;
484
485 if (ns > IR_MAX_DURATION)
486 ns = IR_MAX_DURATION;
487 pulse_clocks = ns_to_pulse_clocks(ns);
488 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
489 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
490 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
491 }
492
493 /*
494 * IR Tx Carrier Duty Cycle register helpers
495 */
496 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
497 unsigned int duty_cycle)
498 {
499 u32 n;
500 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
501 if (n != 0)
502 n--;
503 if (n > 15)
504 n = 15;
505 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
506 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
507 }
508
509 /*
510 * IR Filter Register helpers
511 */
512 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
513 {
514 u32 count = ns_to_lpf_count(min_width_ns);
515 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
516 return lpf_count_to_ns(count);
517 }
518
519 /*
520 * IR IRQ Enable Register helpers
521 */
522 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
523 {
524 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
525 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
526 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
527 }
528
529 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
530 {
531 mask &= IRQEN_TSE;
532 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
533 }
534
535 /*
536 * V4L2 Subdevice IR Ops
537 */
538 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
539 bool *handled)
540 {
541 struct cx23888_ir_state *state = to_state(sd);
542 struct cx23885_dev *dev = state->dev;
543 unsigned long flags;
544
545 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
546 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
547 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
548
549 union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
550 unsigned int i, j, k;
551 u32 events, v;
552 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
553
554 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
555 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
556 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
557 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
558
559 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
560 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
561 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
562 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
563
564 *handled = false;
565 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
566 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
567 rto ? "rto" : " ", ror ? "ror" : " ",
568 stats & STATS_TBY ? "tby" : " ",
569 stats & STATS_RBY ? "rby" : " ");
570
571 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
572 tse ? "tse" : " ", rse ? "rse" : " ",
573 rte ? "rte" : " ", roe ? "roe" : " ");
574
575 /*
576 * Transmitter interrupt service
577 */
578 if (tse && tsr) {
579 /*
580 * TODO:
581 * Check the watermark threshold setting
582 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
583 * Push the data to the hardware FIFO.
584 * If there was nothing more to send in the tx_kfifo, disable
585 * the TSR IRQ and notify the v4l2_device.
586 * If there was something in the tx_kfifo, check the tx_kfifo
587 * level and notify the v4l2_device, if it is low.
588 */
589 /* For now, inhibit TSR interrupt until Tx is implemented */
590 irqenable_tx(dev, 0);
591 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
592 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
593 *handled = true;
594 }
595
596 /*
597 * Receiver interrupt service
598 */
599 kror = 0;
600 if ((rse && rsr) || (rte && rto)) {
601 /*
602 * Receive data on RSR to clear the STATS_RSR.
603 * Receive data on RTO, since we may not have yet hit the RSR
604 * watermark when we receive the RTO.
605 */
606 for (i = 0, v = FIFO_RX_NDV;
607 (v & FIFO_RX_NDV) && !kror; i = 0) {
608 for (j = 0;
609 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
610 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
611 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
612 i++;
613 }
614 if (i == 0)
615 break;
616 j = i * sizeof(union cx23888_ir_fifo_rec);
617 k = kfifo_in_locked(&state->rx_kfifo,
618 (unsigned char *) rx_data, j,
619 &state->rx_kfifo_lock);
620 if (k != j)
621 kror++; /* rx_kfifo over run */
622 }
623 *handled = true;
624 }
625
626 events = 0;
627 v = 0;
628 if (kror) {
629 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
630 v4l2_err(sd, "IR receiver software FIFO overrun\n");
631 }
632 if (roe && ror) {
633 /*
634 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
635 * the Rx FIFO Over Run status (STATS_ROR)
636 */
637 v |= CNTRL_RFE;
638 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
639 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
640 }
641 if (rte && rto) {
642 /*
643 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
644 * the Rx Pulse Width Timer Time Out (STATS_RTO)
645 */
646 v |= CNTRL_RXE;
647 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
648 }
649 if (v) {
650 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
651 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
652 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
653 *handled = true;
654 }
655
656 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
657 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
658 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
659 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
660
661 if (events)
662 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
663 return 0;
664 }
665
666 /* Receiver */
667 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
668 ssize_t *num)
669 {
670 struct cx23888_ir_state *state = to_state(sd);
671 bool invert = (bool) atomic_read(&state->rx_invert);
672 u16 divider = (u16) atomic_read(&state->rxclk_divider);
673
674 unsigned int i, n;
675 union cx23888_ir_fifo_rec *p;
676 unsigned u, v;
677
678 n = count / sizeof(union cx23888_ir_fifo_rec)
679 * sizeof(union cx23888_ir_fifo_rec);
680 if (n == 0) {
681 *num = 0;
682 return 0;
683 }
684
685 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
686
687 n /= sizeof(union cx23888_ir_fifo_rec);
688 *num = n * sizeof(union cx23888_ir_fifo_rec);
689
690 for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
691
692 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
693 /* Assume RTO was because of no IR light input */
694 u = 0;
695 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
696 } else {
697 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
698 if (invert)
699 u = u ? 0 : 1;
700 }
701
702 v = (unsigned) pulse_width_count_to_ns(
703 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
704 if (v > IR_MAX_DURATION)
705 v = IR_MAX_DURATION;
706
707 p->ir_core_data.pulse = u;
708 p->ir_core_data.duration = v;
709
710 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s\n",
711 v, u ? "mark" : "space");
712 }
713 return 0;
714 }
715
716 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
717 struct v4l2_subdev_ir_parameters *p)
718 {
719 struct cx23888_ir_state *state = to_state(sd);
720 mutex_lock(&state->rx_params_lock);
721 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
722 mutex_unlock(&state->rx_params_lock);
723 return 0;
724 }
725
726 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
727 {
728 struct cx23888_ir_state *state = to_state(sd);
729 struct cx23885_dev *dev = state->dev;
730
731 mutex_lock(&state->rx_params_lock);
732
733 /* Disable or slow down all IR Rx circuits and counters */
734 irqenable_rx(dev, 0);
735 control_rx_enable(dev, false);
736 control_rx_demodulation_enable(dev, false);
737 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
738 filter_rx_s_min_width(dev, 0);
739 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
740
741 state->rx_params.shutdown = true;
742
743 mutex_unlock(&state->rx_params_lock);
744 return 0;
745 }
746
747 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
748 struct v4l2_subdev_ir_parameters *p)
749 {
750 struct cx23888_ir_state *state = to_state(sd);
751 struct cx23885_dev *dev = state->dev;
752 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
753 u16 rxclk_divider;
754
755 if (p->shutdown)
756 return cx23888_ir_rx_shutdown(sd);
757
758 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
759 return -ENOSYS;
760
761 mutex_lock(&state->rx_params_lock);
762
763 o->shutdown = p->shutdown;
764
765 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
766
767 o->bytes_per_data_element = p->bytes_per_data_element
768 = sizeof(union cx23888_ir_fifo_rec);
769
770 /* Before we tweak the hardware, we have to disable the receiver */
771 irqenable_rx(dev, 0);
772 control_rx_enable(dev, false);
773
774 control_rx_demodulation_enable(dev, p->modulation);
775 o->modulation = p->modulation;
776
777 if (p->modulation) {
778 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
779 &rxclk_divider);
780
781 o->carrier_freq = p->carrier_freq;
782
783 o->duty_cycle = p->duty_cycle = 50;
784
785 control_rx_s_carrier_window(dev, p->carrier_freq,
786 &p->carrier_range_lower,
787 &p->carrier_range_upper);
788 o->carrier_range_lower = p->carrier_range_lower;
789 o->carrier_range_upper = p->carrier_range_upper;
790
791 p->max_pulse_width =
792 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
793 } else {
794 p->max_pulse_width =
795 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
796 &rxclk_divider);
797 }
798 o->max_pulse_width = p->max_pulse_width;
799 atomic_set(&state->rxclk_divider, rxclk_divider);
800
801 p->noise_filter_min_width =
802 filter_rx_s_min_width(dev, p->noise_filter_min_width);
803 o->noise_filter_min_width = p->noise_filter_min_width;
804
805 p->resolution = clock_divider_to_resolution(rxclk_divider);
806 o->resolution = p->resolution;
807
808 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
809
810 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
811
812 o->invert_level = p->invert_level;
813 atomic_set(&state->rx_invert, p->invert_level);
814
815 o->interrupt_enable = p->interrupt_enable;
816 o->enable = p->enable;
817 if (p->enable) {
818 unsigned long flags;
819
820 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
821 kfifo_reset(&state->rx_kfifo);
822 /* reset tx_fifo too if there is one... */
823 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
824 if (p->interrupt_enable)
825 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
826 control_rx_enable(dev, p->enable);
827 }
828
829 mutex_unlock(&state->rx_params_lock);
830 return 0;
831 }
832
833 /* Transmitter */
834 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
835 ssize_t *num)
836 {
837 struct cx23888_ir_state *state = to_state(sd);
838 struct cx23885_dev *dev = state->dev;
839 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
840 irqenable_tx(dev, IRQEN_TSE);
841 *num = count;
842 return 0;
843 }
844
845 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
846 struct v4l2_subdev_ir_parameters *p)
847 {
848 struct cx23888_ir_state *state = to_state(sd);
849 mutex_lock(&state->tx_params_lock);
850 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
851 mutex_unlock(&state->tx_params_lock);
852 return 0;
853 }
854
855 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
856 {
857 struct cx23888_ir_state *state = to_state(sd);
858 struct cx23885_dev *dev = state->dev;
859
860 mutex_lock(&state->tx_params_lock);
861
862 /* Disable or slow down all IR Tx circuits and counters */
863 irqenable_tx(dev, 0);
864 control_tx_enable(dev, false);
865 control_tx_modulation_enable(dev, false);
866 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
867
868 state->tx_params.shutdown = true;
869
870 mutex_unlock(&state->tx_params_lock);
871 return 0;
872 }
873
874 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
875 struct v4l2_subdev_ir_parameters *p)
876 {
877 struct cx23888_ir_state *state = to_state(sd);
878 struct cx23885_dev *dev = state->dev;
879 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
880 u16 txclk_divider;
881
882 if (p->shutdown)
883 return cx23888_ir_tx_shutdown(sd);
884
885 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
886 return -ENOSYS;
887
888 mutex_lock(&state->tx_params_lock);
889
890 o->shutdown = p->shutdown;
891
892 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
893
894 o->bytes_per_data_element = p->bytes_per_data_element
895 = sizeof(union cx23888_ir_fifo_rec);
896
897 /* Before we tweak the hardware, we have to disable the transmitter */
898 irqenable_tx(dev, 0);
899 control_tx_enable(dev, false);
900
901 control_tx_modulation_enable(dev, p->modulation);
902 o->modulation = p->modulation;
903
904 if (p->modulation) {
905 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
906 &txclk_divider);
907 o->carrier_freq = p->carrier_freq;
908
909 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
910 o->duty_cycle = p->duty_cycle;
911
912 p->max_pulse_width =
913 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
914 } else {
915 p->max_pulse_width =
916 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
917 &txclk_divider);
918 }
919 o->max_pulse_width = p->max_pulse_width;
920 atomic_set(&state->txclk_divider, txclk_divider);
921
922 p->resolution = clock_divider_to_resolution(txclk_divider);
923 o->resolution = p->resolution;
924
925 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
926
927 control_tx_polarity_invert(dev, p->invert_carrier_sense);
928 o->invert_carrier_sense = p->invert_carrier_sense;
929
930 control_tx_level_invert(dev, p->invert_level);
931 o->invert_level = p->invert_level;
932
933 o->interrupt_enable = p->interrupt_enable;
934 o->enable = p->enable;
935 if (p->enable) {
936 if (p->interrupt_enable)
937 irqenable_tx(dev, IRQEN_TSE);
938 control_tx_enable(dev, p->enable);
939 }
940
941 mutex_unlock(&state->tx_params_lock);
942 return 0;
943 }
944
945
946 /*
947 * V4L2 Subdevice Core Ops
948 */
949 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
950 {
951 struct cx23888_ir_state *state = to_state(sd);
952 struct cx23885_dev *dev = state->dev;
953 char *s;
954 int i, j;
955
956 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
957 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
958 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
959 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
960 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
961 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
962 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
963
964 v4l2_info(sd, "IR Receiver:\n");
965 v4l2_info(sd, "\tEnabled: %s\n",
966 cntrl & CNTRL_RXE ? "yes" : "no");
967 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
968 cntrl & CNTRL_DMD ? "enabled" : "disabled");
969 v4l2_info(sd, "\tFIFO: %s\n",
970 cntrl & CNTRL_RFE ? "enabled" : "disabled");
971 switch (cntrl & CNTRL_EDG) {
972 case CNTRL_EDG_NONE:
973 s = "disabled";
974 break;
975 case CNTRL_EDG_FALL:
976 s = "falling edge";
977 break;
978 case CNTRL_EDG_RISE:
979 s = "rising edge";
980 break;
981 case CNTRL_EDG_BOTH:
982 s = "rising & falling edges";
983 break;
984 default:
985 s = "??? edge";
986 break;
987 }
988 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
989 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
990 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
991 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
992 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
993 v4l2_info(sd, "\tLoopback mode: %s\n",
994 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
995 if (cntrl & CNTRL_DMD) {
996 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
997 clock_divider_to_carrier_freq(rxclk));
998 switch (cntrl & CNTRL_WIN) {
999 case CNTRL_WIN_3_3:
1000 i = 3;
1001 j = 3;
1002 break;
1003 case CNTRL_WIN_4_3:
1004 i = 4;
1005 j = 3;
1006 break;
1007 case CNTRL_WIN_3_4:
1008 i = 3;
1009 j = 4;
1010 break;
1011 case CNTRL_WIN_4_4:
1012 i = 4;
1013 j = 4;
1014 break;
1015 default:
1016 i = 0;
1017 j = 0;
1018 break;
1019 }
1020 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
1021 "-%1d/+%1d, %u to %u Hz\n", i, j,
1022 clock_divider_to_freq(rxclk, 16 + j),
1023 clock_divider_to_freq(rxclk, 16 - i));
1024 }
1025 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1026 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1027 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1028 v4l2_info(sd, "\tLow pass filter: %s\n",
1029 filtr ? "enabled" : "disabled");
1030 if (filtr)
1031 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1032 "%u ns\n",
1033 lpf_count_to_us(filtr),
1034 lpf_count_to_ns(filtr));
1035 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1036 stats & STATS_RTO ? "yes" : "no");
1037 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1038 irqen & IRQEN_RTE ? "enabled" : "disabled");
1039 v4l2_info(sd, "\tFIFO overrun: %s\n",
1040 stats & STATS_ROR ? "yes" : "no");
1041 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1042 irqen & IRQEN_ROE ? "enabled" : "disabled");
1043 v4l2_info(sd, "\tBusy: %s\n",
1044 stats & STATS_RBY ? "yes" : "no");
1045 v4l2_info(sd, "\tFIFO service requested: %s\n",
1046 stats & STATS_RSR ? "yes" : "no");
1047 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1048 irqen & IRQEN_RSE ? "enabled" : "disabled");
1049
1050 v4l2_info(sd, "IR Transmitter:\n");
1051 v4l2_info(sd, "\tEnabled: %s\n",
1052 cntrl & CNTRL_TXE ? "yes" : "no");
1053 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1054 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1055 v4l2_info(sd, "\tFIFO: %s\n",
1056 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1057 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1058 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1059 v4l2_info(sd, "\tOutput pin level inversion %s\n",
1060 cntrl & CNTRL_IVO ? "yes" : "no");
1061 v4l2_info(sd, "\tCarrier polarity: %s\n",
1062 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1063 : "space:noburst mark:burst");
1064 if (cntrl & CNTRL_MOD) {
1065 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1066 clock_divider_to_carrier_freq(txclk));
1067 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1068 cduty + 1);
1069 }
1070 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1071 pulse_width_count_to_us(FIFO_RXTX, txclk),
1072 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1073 v4l2_info(sd, "\tBusy: %s\n",
1074 stats & STATS_TBY ? "yes" : "no");
1075 v4l2_info(sd, "\tFIFO service requested: %s\n",
1076 stats & STATS_TSR ? "yes" : "no");
1077 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1078 irqen & IRQEN_TSE ? "enabled" : "disabled");
1079
1080 return 0;
1081 }
1082
1083 static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
1084 {
1085 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
1086 }
1087
1088 static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
1089 struct v4l2_dbg_chip_ident *chip)
1090 {
1091 struct cx23888_ir_state *state = to_state(sd);
1092
1093 if (cx23888_ir_dbg_match(&chip->match)) {
1094 chip->ident = state->id;
1095 chip->revision = state->rev;
1096 }
1097 return 0;
1098 }
1099
1100 #ifdef CONFIG_VIDEO_ADV_DEBUG
1101 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1102 struct v4l2_dbg_register *reg)
1103 {
1104 struct cx23888_ir_state *state = to_state(sd);
1105 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1106
1107 if (!cx23888_ir_dbg_match(&reg->match))
1108 return -EINVAL;
1109 if ((addr & 0x3) != 0)
1110 return -EINVAL;
1111 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1112 return -EINVAL;
1113 if (!capable(CAP_SYS_ADMIN))
1114 return -EPERM;
1115 reg->size = 4;
1116 reg->val = cx23888_ir_read4(state->dev, addr);
1117 return 0;
1118 }
1119
1120 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1121 struct v4l2_dbg_register *reg)
1122 {
1123 struct cx23888_ir_state *state = to_state(sd);
1124 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1125
1126 if (!cx23888_ir_dbg_match(&reg->match))
1127 return -EINVAL;
1128 if ((addr & 0x3) != 0)
1129 return -EINVAL;
1130 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1131 return -EINVAL;
1132 if (!capable(CAP_SYS_ADMIN))
1133 return -EPERM;
1134 cx23888_ir_write4(state->dev, addr, reg->val);
1135 return 0;
1136 }
1137 #endif
1138
1139 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1140 .g_chip_ident = cx23888_ir_g_chip_ident,
1141 .log_status = cx23888_ir_log_status,
1142 #ifdef CONFIG_VIDEO_ADV_DEBUG
1143 .g_register = cx23888_ir_g_register,
1144 .s_register = cx23888_ir_s_register,
1145 #endif
1146 .interrupt_service_routine = cx23888_ir_irq_handler,
1147 };
1148
1149 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1150 .rx_read = cx23888_ir_rx_read,
1151 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1152 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1153
1154 .tx_write = cx23888_ir_tx_write,
1155 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1156 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1157 };
1158
1159 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1160 .core = &cx23888_ir_core_ops,
1161 .ir = &cx23888_ir_ir_ops,
1162 };
1163
1164 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1165 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1166 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1167
1168 .enable = false,
1169 .interrupt_enable = false,
1170 .shutdown = true,
1171
1172 .modulation = true,
1173 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1174
1175 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1176 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1177 .noise_filter_min_width = 333333, /* ns */
1178 .carrier_range_lower = 35000,
1179 .carrier_range_upper = 37000,
1180 .invert_level = false,
1181 };
1182
1183 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1184 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1185 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1186
1187 .enable = false,
1188 .interrupt_enable = false,
1189 .shutdown = true,
1190
1191 .modulation = true,
1192 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1193 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1194 .invert_level = false,
1195 .invert_carrier_sense = false,
1196 };
1197
1198 int cx23888_ir_probe(struct cx23885_dev *dev)
1199 {
1200 struct cx23888_ir_state *state;
1201 struct v4l2_subdev *sd;
1202 struct v4l2_subdev_ir_parameters default_params;
1203 int ret;
1204
1205 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1206 if (state == NULL)
1207 return -ENOMEM;
1208
1209 spin_lock_init(&state->rx_kfifo_lock);
1210 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1211 return -ENOMEM;
1212
1213 state->dev = dev;
1214 state->id = V4L2_IDENT_CX23888_IR;
1215 state->rev = 0;
1216 sd = &state->sd;
1217
1218 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1219 v4l2_set_subdevdata(sd, state);
1220 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1221 sd->grp_id = CX23885_HW_888_IR;
1222
1223 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1224 if (ret == 0) {
1225 /*
1226 * Ensure no interrupts arrive from '888 specific conditions,
1227 * since we ignore them in this driver to have commonality with
1228 * similar IR controller cores.
1229 */
1230 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1231
1232 mutex_init(&state->rx_params_lock);
1233 memcpy(&default_params, &default_rx_params,
1234 sizeof(struct v4l2_subdev_ir_parameters));
1235 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1236
1237 mutex_init(&state->tx_params_lock);
1238 memcpy(&default_params, &default_tx_params,
1239 sizeof(struct v4l2_subdev_ir_parameters));
1240 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1241 } else {
1242 kfifo_free(&state->rx_kfifo);
1243 }
1244 return ret;
1245 }
1246
1247 int cx23888_ir_remove(struct cx23885_dev *dev)
1248 {
1249 struct v4l2_subdev *sd;
1250 struct cx23888_ir_state *state;
1251
1252 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1253 if (sd == NULL)
1254 return -ENODEV;
1255
1256 cx23888_ir_rx_shutdown(sd);
1257 cx23888_ir_tx_shutdown(sd);
1258
1259 state = to_state(sd);
1260 v4l2_device_unregister_subdev(sd);
1261 kfifo_free(&state->rx_kfifo);
1262 kfree(state);
1263 /* Nothing more to free() as state held the actual v4l2_subdev object */
1264 return 0;
1265 }
Tomato firmware and modifications.