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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / infiniband / hw / mthca / mthca_cmd.c
blobb038283e3f564a52a14a68b91363505786f0081a
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/completion.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <asm/io.h>
41 #include <rdma/ib_mad.h>
42
43 #include "mthca_dev.h"
44 #include "mthca_config_reg.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 #define CMD_POLL_TOKEN 0xffff
49
50 enum {
51 HCR_IN_PARAM_OFFSET = 0x00,
52 HCR_IN_MODIFIER_OFFSET = 0x08,
53 HCR_OUT_PARAM_OFFSET = 0x0c,
54 HCR_TOKEN_OFFSET = 0x14,
55 HCR_STATUS_OFFSET = 0x18,
56
57 HCR_OPMOD_SHIFT = 12,
58 HCA_E_BIT = 22,
59 HCR_GO_BIT = 23
60 };
61
62 enum {
63 /* initialization and general commands */
64 CMD_SYS_EN = 0x1,
65 CMD_SYS_DIS = 0x2,
66 CMD_MAP_FA = 0xfff,
67 CMD_UNMAP_FA = 0xffe,
68 CMD_RUN_FW = 0xff6,
69 CMD_MOD_STAT_CFG = 0x34,
70 CMD_QUERY_DEV_LIM = 0x3,
71 CMD_QUERY_FW = 0x4,
72 CMD_ENABLE_LAM = 0xff8,
73 CMD_DISABLE_LAM = 0xff7,
74 CMD_QUERY_DDR = 0x5,
75 CMD_QUERY_ADAPTER = 0x6,
76 CMD_INIT_HCA = 0x7,
77 CMD_CLOSE_HCA = 0x8,
78 CMD_INIT_IB = 0x9,
79 CMD_CLOSE_IB = 0xa,
80 CMD_QUERY_HCA = 0xb,
81 CMD_SET_IB = 0xc,
82 CMD_ACCESS_DDR = 0x2e,
83 CMD_MAP_ICM = 0xffa,
84 CMD_UNMAP_ICM = 0xff9,
85 CMD_MAP_ICM_AUX = 0xffc,
86 CMD_UNMAP_ICM_AUX = 0xffb,
87 CMD_SET_ICM_SIZE = 0xffd,
88
89 /* TPT commands */
90 CMD_SW2HW_MPT = 0xd,
91 CMD_QUERY_MPT = 0xe,
92 CMD_HW2SW_MPT = 0xf,
93 CMD_READ_MTT = 0x10,
94 CMD_WRITE_MTT = 0x11,
95 CMD_SYNC_TPT = 0x2f,
96
97 /* EQ commands */
98 CMD_MAP_EQ = 0x12,
99 CMD_SW2HW_EQ = 0x13,
100 CMD_HW2SW_EQ = 0x14,
101 CMD_QUERY_EQ = 0x15,
102
103 /* CQ commands */
104 CMD_SW2HW_CQ = 0x16,
105 CMD_HW2SW_CQ = 0x17,
106 CMD_QUERY_CQ = 0x18,
107 CMD_RESIZE_CQ = 0x2c,
108
109 /* SRQ commands */
110 CMD_SW2HW_SRQ = 0x35,
111 CMD_HW2SW_SRQ = 0x36,
112 CMD_QUERY_SRQ = 0x37,
113 CMD_ARM_SRQ = 0x40,
114
115 /* QP/EE commands */
116 CMD_RST2INIT_QPEE = 0x19,
117 CMD_INIT2RTR_QPEE = 0x1a,
118 CMD_RTR2RTS_QPEE = 0x1b,
119 CMD_RTS2RTS_QPEE = 0x1c,
120 CMD_SQERR2RTS_QPEE = 0x1d,
121 CMD_2ERR_QPEE = 0x1e,
122 CMD_RTS2SQD_QPEE = 0x1f,
123 CMD_SQD2SQD_QPEE = 0x38,
124 CMD_SQD2RTS_QPEE = 0x20,
125 CMD_ERR2RST_QPEE = 0x21,
126 CMD_QUERY_QPEE = 0x22,
127 CMD_INIT2INIT_QPEE = 0x2d,
128 CMD_SUSPEND_QPEE = 0x32,
129 CMD_UNSUSPEND_QPEE = 0x33,
130 /* special QPs and management commands */
131 CMD_CONF_SPECIAL_QP = 0x23,
132 CMD_MAD_IFC = 0x24,
133
134 /* multicast commands */
135 CMD_READ_MGM = 0x25,
136 CMD_WRITE_MGM = 0x26,
137 CMD_MGID_HASH = 0x27,
138
139 /* miscellaneous commands */
140 CMD_DIAG_RPRT = 0x30,
141 CMD_NOP = 0x31,
142
143 /* debug commands */
144 CMD_QUERY_DEBUG_MSG = 0x2a,
145 CMD_SET_DEBUG_MSG = 0x2b,
146 };
147
148 /*
149 * According to Mellanox code, FW may be starved and never complete
150 * commands. So we can't use strict timeouts described in PRM -- we
151 * just arbitrarily select 60 seconds for now.
152 */
153 enum {
154 CMD_TIME_CLASS_A = 60 * HZ,
155 CMD_TIME_CLASS_B = 60 * HZ,
156 CMD_TIME_CLASS_C = 60 * HZ,
157 CMD_TIME_CLASS_D = 60 * HZ
158 };
159
160 enum {
161 GO_BIT_TIMEOUT = HZ * 10
162 };
163
164 struct mthca_cmd_context {
165 struct completion done;
166 int result;
167 int next;
168 u64 out_param;
169 u16 token;
170 u8 status;
171 };
172
173 static int fw_cmd_doorbell = 0;
174 module_param(fw_cmd_doorbell, int, 0644);
175 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
176 "(and supported by FW)");
177
178 static inline int go_bit(struct mthca_dev *dev)
179 {
180 return readl(dev->hcr + HCR_STATUS_OFFSET) &
181 swab32(1 << HCR_GO_BIT);
182 }
183
184 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
185 u64 in_param,
186 u64 out_param,
187 u32 in_modifier,
188 u8 op_modifier,
189 u16 op,
190 u16 token)
191 {
192 void __iomem *ptr = dev->cmd.dbell_map;
193 u16 *offs = dev->cmd.dbell_offsets;
194
195 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
196 wmb();
197 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
198 wmb();
199 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
200 wmb();
201 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
202 wmb();
203 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
204 wmb();
205 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
206 wmb();
207 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
208 (1 << HCA_E_BIT) |
209 (op_modifier << HCR_OPMOD_SHIFT) |
210 op), ptr + offs[6]);
211 wmb();
212 __raw_writel((__force u32) 0, ptr + offs[7]);
213 wmb();
214 }
215
216 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
217 u64 in_param,
218 u64 out_param,
219 u32 in_modifier,
220 u8 op_modifier,
221 u16 op,
222 u16 token,
223 int event)
224 {
225 if (event) {
226 unsigned long end = jiffies + GO_BIT_TIMEOUT;
227
228 while (go_bit(dev) && time_before(jiffies, end)) {
229 set_current_state(TASK_RUNNING);
230 schedule();
231 }
232 }
233
234 if (go_bit(dev))
235 return -EAGAIN;
236
237 /*
238 * We use writel (instead of something like memcpy_toio)
239 * because writes of less than 32 bits to the HCR don't work
240 * (and some architectures such as ia64 implement memcpy_toio
241 * in terms of writeb).
242 */
243 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
244 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
245 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
246 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
247 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
248 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
249
250 /* __raw_writel may not order writes. */
251 wmb();
252
253 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
254 (event ? (1 << HCA_E_BIT) : 0) |
255 (op_modifier << HCR_OPMOD_SHIFT) |
256 op), dev->hcr + 6 * 4);
257
258 return 0;
259 }
260
261 static int mthca_cmd_post(struct mthca_dev *dev,
262 u64 in_param,
263 u64 out_param,
264 u32 in_modifier,
265 u8 op_modifier,
266 u16 op,
267 u16 token,
268 int event)
269 {
270 int err = 0;
271
272 mutex_lock(&dev->cmd.hcr_mutex);
273
274 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
275 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
276 op_modifier, op, token);
277 else
278 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
279 op_modifier, op, token, event);
280
281 /*
282 * Make sure that our HCR writes don't get mixed in with
283 * writes from another CPU starting a FW command.
284 */
285 mmiowb();
286
287 mutex_unlock(&dev->cmd.hcr_mutex);
288 return err;
289 }
290
291 static int mthca_cmd_poll(struct mthca_dev *dev,
292 u64 in_param,
293 u64 *out_param,
294 int out_is_imm,
295 u32 in_modifier,
296 u8 op_modifier,
297 u16 op,
298 unsigned long timeout,
299 u8 *status)
300 {
301 int err = 0;
302 unsigned long end;
303
304 down(&dev->cmd.poll_sem);
305
306 err = mthca_cmd_post(dev, in_param,
307 out_param ? *out_param : 0,
308 in_modifier, op_modifier,
309 op, CMD_POLL_TOKEN, 0);
310 if (err)
311 goto out;
312
313 end = timeout + jiffies;
314 while (go_bit(dev) && time_before(jiffies, end)) {
315 set_current_state(TASK_RUNNING);
316 schedule();
317 }
318
319 if (go_bit(dev)) {
320 err = -EBUSY;
321 goto out;
322 }
323
324 if (out_is_imm)
325 *out_param =
326 (u64) be32_to_cpu((__force __be32)
327 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
328 (u64) be32_to_cpu((__force __be32)
329 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
330
331 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
332
333 out:
334 up(&dev->cmd.poll_sem);
335 return err;
336 }
337
338 void mthca_cmd_event(struct mthca_dev *dev,
339 u16 token,
340 u8 status,
341 u64 out_param)
342 {
343 struct mthca_cmd_context *context =
344 &dev->cmd.context[token & dev->cmd.token_mask];
345
346 /* previously timed out command completing at long last */
347 if (token != context->token)
348 return;
349
350 context->result = 0;
351 context->status = status;
352 context->out_param = out_param;
353
354 complete(&context->done);
355 }
356
357 static int mthca_cmd_wait(struct mthca_dev *dev,
358 u64 in_param,
359 u64 *out_param,
360 int out_is_imm,
361 u32 in_modifier,
362 u8 op_modifier,
363 u16 op,
364 unsigned long timeout,
365 u8 *status)
366 {
367 int err = 0;
368 struct mthca_cmd_context *context;
369
370 down(&dev->cmd.event_sem);
371
372 spin_lock(&dev->cmd.context_lock);
373 BUG_ON(dev->cmd.free_head < 0);
374 context = &dev->cmd.context[dev->cmd.free_head];
375 context->token += dev->cmd.token_mask + 1;
376 dev->cmd.free_head = context->next;
377 spin_unlock(&dev->cmd.context_lock);
378
379 init_completion(&context->done);
380
381 err = mthca_cmd_post(dev, in_param,
382 out_param ? *out_param : 0,
383 in_modifier, op_modifier,
384 op, context->token, 1);
385 if (err)
386 goto out;
387
388 if (!wait_for_completion_timeout(&context->done, timeout)) {
389 err = -EBUSY;
390 goto out;
391 }
392
393 err = context->result;
394 if (err)
395 goto out;
396
397 *status = context->status;
398 if (*status)
399 mthca_dbg(dev, "Command %02x completed with status %02x\n",
400 op, *status);
401
402 if (out_is_imm)
403 *out_param = context->out_param;
404
405 out:
406 spin_lock(&dev->cmd.context_lock);
407 context->next = dev->cmd.free_head;
408 dev->cmd.free_head = context - dev->cmd.context;
409 spin_unlock(&dev->cmd.context_lock);
410
411 up(&dev->cmd.event_sem);
412 return err;
413 }
414
415 /* Invoke a command with an output mailbox */
416 static int mthca_cmd_box(struct mthca_dev *dev,
417 u64 in_param,
418 u64 out_param,
419 u32 in_modifier,
420 u8 op_modifier,
421 u16 op,
422 unsigned long timeout,
423 u8 *status)
424 {
425 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
426 return mthca_cmd_wait(dev, in_param, &out_param, 0,
427 in_modifier, op_modifier, op,
428 timeout, status);
429 else
430 return mthca_cmd_poll(dev, in_param, &out_param, 0,
431 in_modifier, op_modifier, op,
432 timeout, status);
433 }
434
435 /* Invoke a command with no output parameter */
436 static int mthca_cmd(struct mthca_dev *dev,
437 u64 in_param,
438 u32 in_modifier,
439 u8 op_modifier,
440 u16 op,
441 unsigned long timeout,
442 u8 *status)
443 {
444 return mthca_cmd_box(dev, in_param, 0, in_modifier,
445 op_modifier, op, timeout, status);
446 }
447
448 /*
449 * Invoke a command with an immediate output parameter (and copy the
450 * output into the caller's out_param pointer after the command
451 * executes).
452 */
453 static int mthca_cmd_imm(struct mthca_dev *dev,
454 u64 in_param,
455 u64 *out_param,
456 u32 in_modifier,
457 u8 op_modifier,
458 u16 op,
459 unsigned long timeout,
460 u8 *status)
461 {
462 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
463 return mthca_cmd_wait(dev, in_param, out_param, 1,
464 in_modifier, op_modifier, op,
465 timeout, status);
466 else
467 return mthca_cmd_poll(dev, in_param, out_param, 1,
468 in_modifier, op_modifier, op,
469 timeout, status);
470 }
471
472 int mthca_cmd_init(struct mthca_dev *dev)
473 {
474 mutex_init(&dev->cmd.hcr_mutex);
475 sema_init(&dev->cmd.poll_sem, 1);
476 dev->cmd.flags = 0;
477
478 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
479 MTHCA_HCR_SIZE);
480 if (!dev->hcr) {
481 mthca_err(dev, "Couldn't map command register.");
482 return -ENOMEM;
483 }
484
485 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
486 MTHCA_MAILBOX_SIZE,
487 MTHCA_MAILBOX_SIZE, 0);
488 if (!dev->cmd.pool) {
489 iounmap(dev->hcr);
490 return -ENOMEM;
491 }
492
493 return 0;
494 }
495
496 void mthca_cmd_cleanup(struct mthca_dev *dev)
497 {
498 pci_pool_destroy(dev->cmd.pool);
499 iounmap(dev->hcr);
500 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
501 iounmap(dev->cmd.dbell_map);
502 }
503
504 /*
505 * Switch to using events to issue FW commands (should be called after
506 * event queue to command events has been initialized).
507 */
508 int mthca_cmd_use_events(struct mthca_dev *dev)
509 {
510 int i;
511
512 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
513 sizeof (struct mthca_cmd_context),
514 GFP_KERNEL);
515 if (!dev->cmd.context)
516 return -ENOMEM;
517
518 for (i = 0; i < dev->cmd.max_cmds; ++i) {
519 dev->cmd.context[i].token = i;
520 dev->cmd.context[i].next = i + 1;
521 }
522
523 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
524 dev->cmd.free_head = 0;
525
526 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
527 spin_lock_init(&dev->cmd.context_lock);
528
529 for (dev->cmd.token_mask = 1;
530 dev->cmd.token_mask < dev->cmd.max_cmds;
531 dev->cmd.token_mask <<= 1)
532 ; /* nothing */
533 --dev->cmd.token_mask;
534
535 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
536
537 down(&dev->cmd.poll_sem);
538
539 return 0;
540 }
541
542 /*
543 * Switch back to polling (used when shutting down the device)
544 */
545 void mthca_cmd_use_polling(struct mthca_dev *dev)
546 {
547 int i;
548
549 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
550
551 for (i = 0; i < dev->cmd.max_cmds; ++i)
552 down(&dev->cmd.event_sem);
553
554 kfree(dev->cmd.context);
555
556 up(&dev->cmd.poll_sem);
557 }
558
559 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
560 gfp_t gfp_mask)
561 {
562 struct mthca_mailbox *mailbox;
563
564 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
565 if (!mailbox)
566 return ERR_PTR(-ENOMEM);
567
568 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
569 if (!mailbox->buf) {
570 kfree(mailbox);
571 return ERR_PTR(-ENOMEM);
572 }
573
574 return mailbox;
575 }
576
577 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
578 {
579 if (!mailbox)
580 return;
581
582 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
583 kfree(mailbox);
584 }
585
586 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
587 {
588 u64 out;
589 int ret;
590
591 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status);
592
593 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
594 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
595 "sladdr=%d, SPD source=%s\n",
596 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
597 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
598
599 return ret;
600 }
601
602 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
603 {
604 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
605 }
606
607 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
608 u64 virt, u8 *status)
609 {
610 struct mthca_mailbox *mailbox;
611 struct mthca_icm_iter iter;
612 __be64 *pages;
613 int lg;
614 int nent = 0;
615 int i;
616 int err = 0;
617 int ts = 0, tc = 0;
618
619 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
620 if (IS_ERR(mailbox))
621 return PTR_ERR(mailbox);
622 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
623 pages = mailbox->buf;
624
625 for (mthca_icm_first(icm, &iter);
626 !mthca_icm_last(&iter);
627 mthca_icm_next(&iter)) {
628 /*
629 * We have to pass pages that are aligned to their
630 * size, so find the least significant 1 in the
631 * address or size and use that as our log2 size.
632 */
633 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
634 if (lg < MTHCA_ICM_PAGE_SHIFT) {
635 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
636 MTHCA_ICM_PAGE_SIZE,
637 (unsigned long long) mthca_icm_addr(&iter),
638 mthca_icm_size(&iter));
639 err = -EINVAL;
640 goto out;
641 }
642 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
643 if (virt != -1) {
644 pages[nent * 2] = cpu_to_be64(virt);
645 virt += 1 << lg;
646 }
647
648 pages[nent * 2 + 1] =
649 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
650 (lg - MTHCA_ICM_PAGE_SHIFT));
651 ts += 1 << (lg - 10);
652 ++tc;
653
654 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
655 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
656 CMD_TIME_CLASS_B, status);
657 if (err || *status)
658 goto out;
659 nent = 0;
660 }
661 }
662 }
663
664 if (nent)
665 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
666 CMD_TIME_CLASS_B, status);
667
668 switch (op) {
669 case CMD_MAP_FA:
670 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
671 break;
672 case CMD_MAP_ICM_AUX:
673 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
674 break;
675 case CMD_MAP_ICM:
676 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
677 tc, ts, (unsigned long long) virt - (ts << 10));
678 break;
679 }
680
681 out:
682 mthca_free_mailbox(dev, mailbox);
683 return err;
684 }
685
686 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
687 {
688 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
689 }
690
691 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
692 {
693 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
694 }
695
696 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
697 {
698 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
699 }
700
701 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
702 {
703 unsigned long addr;
704 u16 max_off = 0;
705 int i;
706
707 for (i = 0; i < 8; ++i)
708 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
709
710 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
711 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
712 "length 0x%x crosses a page boundary\n",
713 (unsigned long long) base, max_off);
714 return;
715 }
716
717 addr = pci_resource_start(dev->pdev, 2) +
718 ((pci_resource_len(dev->pdev, 2) - 1) & base);
719 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
720 if (!dev->cmd.dbell_map)
721 return;
722
723 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
724 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
725 }
726
727 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
728 {
729 struct mthca_mailbox *mailbox;
730 u32 *outbox;
731 u64 base;
732 u32 tmp;
733 int err = 0;
734 u8 lg;
735 int i;
736
737 #define QUERY_FW_OUT_SIZE 0x100
738 #define QUERY_FW_VER_OFFSET 0x00
739 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
740 #define QUERY_FW_ERR_START_OFFSET 0x30
741 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
742
743 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
744 #define QUERY_FW_CMD_DB_OFFSET 0x50
745 #define QUERY_FW_CMD_DB_BASE 0x60
746
747 #define QUERY_FW_START_OFFSET 0x20
748 #define QUERY_FW_END_OFFSET 0x28
749
750 #define QUERY_FW_SIZE_OFFSET 0x00
751 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
752 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
753 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
754
755 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
756 if (IS_ERR(mailbox))
757 return PTR_ERR(mailbox);
758 outbox = mailbox->buf;
759
760 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
761 CMD_TIME_CLASS_A, status);
762
763 if (err)
764 goto out;
765
766 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
767 /*
768 * FW subminor version is at more significant bits than minor
769 * version, so swap here.
770 */
771 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
772 ((dev->fw_ver & 0xffff0000ull) >> 16) |
773 ((dev->fw_ver & 0x0000ffffull) << 16);
774
775 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
776 dev->cmd.max_cmds = 1 << lg;
777
778 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
779 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
780
781 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
782 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
783
784 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
785 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
786
787 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
788 if (tmp & 0x1) {
789 mthca_dbg(dev, "FW supports commands through doorbells\n");
790
791 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
792 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
793 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
794 QUERY_FW_CMD_DB_OFFSET + (i << 1));
795
796 mthca_setup_cmd_doorbells(dev, base);
797 }
798
799 if (mthca_is_memfree(dev)) {
800 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
801 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
802 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
803 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
804 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
805
806 /*
807 * Round up number of system pages needed in case
808 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
809 */
810 dev->fw.arbel.fw_pages =
811 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
812 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
813
814 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
815 (unsigned long long) dev->fw.arbel.clr_int_base,
816 (unsigned long long) dev->fw.arbel.eq_arm_base,
817 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
818 } else {
819 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
820 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
821
822 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
823 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
824 (unsigned long long) dev->fw.tavor.fw_start,
825 (unsigned long long) dev->fw.tavor.fw_end);
826 }
827
828 out:
829 mthca_free_mailbox(dev, mailbox);
830 return err;
831 }
832
833 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
834 {
835 struct mthca_mailbox *mailbox;
836 u8 info;
837 u32 *outbox;
838 int err = 0;
839
840 #define ENABLE_LAM_OUT_SIZE 0x100
841 #define ENABLE_LAM_START_OFFSET 0x00
842 #define ENABLE_LAM_END_OFFSET 0x08
843 #define ENABLE_LAM_INFO_OFFSET 0x13
844
845 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
846 #define ENABLE_LAM_INFO_ECC_MASK 0x3
847
848 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
849 if (IS_ERR(mailbox))
850 return PTR_ERR(mailbox);
851 outbox = mailbox->buf;
852
853 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
854 CMD_TIME_CLASS_C, status);
855
856 if (err)
857 goto out;
858
859 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
860 goto out;
861
862 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
863 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
864 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
865
866 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
867 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
868 mthca_info(dev, "FW reports that HCA-attached memory "
869 "is %s hidden; does not match PCI config\n",
870 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
871 "" : "not");
872 }
873 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
874 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
875
876 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
877 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
878 (unsigned long long) dev->ddr_start,
879 (unsigned long long) dev->ddr_end);
880
881 out:
882 mthca_free_mailbox(dev, mailbox);
883 return err;
884 }
885
886 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
887 {
888 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
889 }
890
891 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
892 {
893 struct mthca_mailbox *mailbox;
894 u8 info;
895 u32 *outbox;
896 int err = 0;
897
898 #define QUERY_DDR_OUT_SIZE 0x100
899 #define QUERY_DDR_START_OFFSET 0x00
900 #define QUERY_DDR_END_OFFSET 0x08
901 #define QUERY_DDR_INFO_OFFSET 0x13
902
903 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
904 #define QUERY_DDR_INFO_ECC_MASK 0x3
905
906 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
907 if (IS_ERR(mailbox))
908 return PTR_ERR(mailbox);
909 outbox = mailbox->buf;
910
911 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
912 CMD_TIME_CLASS_A, status);
913
914 if (err)
915 goto out;
916
917 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
918 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
919 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
920
921 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
922 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
923 mthca_info(dev, "FW reports that HCA-attached memory "
924 "is %s hidden; does not match PCI config\n",
925 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
926 "" : "not");
927 }
928 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
929 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
930
931 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
932 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
933 (unsigned long long) dev->ddr_start,
934 (unsigned long long) dev->ddr_end);
935
936 out:
937 mthca_free_mailbox(dev, mailbox);
938 return err;
939 }
940
941 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
942 struct mthca_dev_lim *dev_lim, u8 *status)
943 {
944 struct mthca_mailbox *mailbox;
945 u32 *outbox;
946 u8 field;
947 u16 size;
948 u16 stat_rate;
949 int err;
950
951 #define QUERY_DEV_LIM_OUT_SIZE 0x100
952 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
953 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
954 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
955 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
956 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
957 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
958 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
959 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
960 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
961 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
962 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
963 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
964 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
965 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
966 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
967 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
968 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
969 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
970 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
971 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
972 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
973 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
974 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
975 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
976 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
977 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
978 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
979 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
980 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
981 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
982 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
983 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
984 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
985 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
986 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
987 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
988 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
989 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
990 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
991 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
992 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
993 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
994 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
995 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
996 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
997 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
998 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
999 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1000 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1001 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1002 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1003 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1004 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1005 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1006 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1007 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1008 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1009 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1010 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1011
1012 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1013 if (IS_ERR(mailbox))
1014 return PTR_ERR(mailbox);
1015 outbox = mailbox->buf;
1016
1017 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1018 CMD_TIME_CLASS_A, status);
1019
1020 if (err)
1021 goto out;
1022
1023 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1024 dev_lim->reserved_qps = 1 << (field & 0xf);
1025 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1026 dev_lim->max_qps = 1 << (field & 0x1f);
1027 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1028 dev_lim->reserved_srqs = 1 << (field >> 4);
1029 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1030 dev_lim->max_srqs = 1 << (field & 0x1f);
1031 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1032 dev_lim->reserved_eecs = 1 << (field & 0xf);
1033 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1034 dev_lim->max_eecs = 1 << (field & 0x1f);
1035 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1036 dev_lim->max_cq_sz = 1 << field;
1037 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1038 dev_lim->reserved_cqs = 1 << (field & 0xf);
1039 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1040 dev_lim->max_cqs = 1 << (field & 0x1f);
1041 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1042 dev_lim->max_mpts = 1 << (field & 0x3f);
1043 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1044 dev_lim->reserved_eqs = 1 << (field & 0xf);
1045 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1046 dev_lim->max_eqs = 1 << (field & 0x7);
1047 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1048 if (mthca_is_memfree(dev))
1049 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1050 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1051 else
1052 dev_lim->reserved_mtts = 1 << (field >> 4);
1053 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1054 dev_lim->max_mrw_sz = 1 << field;
1055 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1056 dev_lim->reserved_mrws = 1 << (field & 0xf);
1057 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1058 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1059 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1060 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1061 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1062 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1063 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1064 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1065 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1066 dev_lim->local_ca_ack_delay = field & 0x1f;
1067 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1068 dev_lim->max_mtu = field >> 4;
1069 dev_lim->max_port_width = field & 0xf;
1070 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1071 dev_lim->max_vl = field >> 4;
1072 dev_lim->num_ports = field & 0xf;
1073 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1074 dev_lim->max_gids = 1 << (field & 0xf);
1075 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1076 dev_lim->stat_rate_support = stat_rate;
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1078 dev_lim->max_pkeys = 1 << (field & 0xf);
1079 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1080 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1081 dev_lim->reserved_uars = field >> 4;
1082 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1083 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1084 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1085 dev_lim->min_page_sz = 1 << field;
1086 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1087 dev_lim->max_sg = field;
1088
1089 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1090 dev_lim->max_desc_sz = size;
1091
1092 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1093 dev_lim->max_qp_per_mcg = 1 << field;
1094 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1095 dev_lim->reserved_mgms = field & 0xf;
1096 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1097 dev_lim->max_mcgs = 1 << field;
1098 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1099 dev_lim->reserved_pds = field >> 4;
1100 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1101 dev_lim->max_pds = 1 << (field & 0x3f);
1102 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1103 dev_lim->reserved_rdds = field >> 4;
1104 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1105 dev_lim->max_rdds = 1 << (field & 0x3f);
1106
1107 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1108 dev_lim->eec_entry_sz = size;
1109 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1110 dev_lim->qpc_entry_sz = size;
1111 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1112 dev_lim->eeec_entry_sz = size;
1113 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1114 dev_lim->eqpc_entry_sz = size;
1115 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1116 dev_lim->eqc_entry_sz = size;
1117 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1118 dev_lim->cqc_entry_sz = size;
1119 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1120 dev_lim->srq_entry_sz = size;
1121 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1122 dev_lim->uar_scratch_entry_sz = size;
1123
1124 if (mthca_is_memfree(dev)) {
1125 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1126 dev_lim->max_srq_sz = 1 << field;
1127 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1128 dev_lim->max_qp_sz = 1 << field;
1129 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1130 dev_lim->hca.arbel.resize_srq = field & 1;
1131 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1132 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1133 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1134 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1135 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1136 dev_lim->mpt_entry_sz = size;
1137 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1138 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1139 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1140 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1141 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1142 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1143 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1144 dev_lim->hca.arbel.lam_required = field & 1;
1145 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1146 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1147
1148 if (dev_lim->hca.arbel.bmme_flags & 1)
1149 mthca_dbg(dev, "Base MM extensions: yes "
1150 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1151 dev_lim->hca.arbel.bmme_flags,
1152 dev_lim->hca.arbel.max_pbl_sz,
1153 dev_lim->hca.arbel.reserved_lkey);
1154 else
1155 mthca_dbg(dev, "Base MM extensions: no\n");
1156
1157 mthca_dbg(dev, "Max ICM size %lld MB\n",
1158 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1159 } else {
1160 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1161 dev_lim->max_srq_sz = (1 << field) - 1;
1162 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1163 dev_lim->max_qp_sz = (1 << field) - 1;
1164 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1165 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1166 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1167 }
1168
1169 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1170 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1171 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1172 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1173 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1174 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1175 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1176 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1177 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1178 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1179 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1180 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1181 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1182 dev_lim->max_pds, dev_lim->reserved_mgms);
1183 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1184 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1185
1186 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1187
1188 out:
1189 mthca_free_mailbox(dev, mailbox);
1190 return err;
1191 }
1192
1193 static void get_board_id(void *vsd, char *board_id)
1194 {
1195 int i;
1196
1197 #define VSD_OFFSET_SIG1 0x00
1198 #define VSD_OFFSET_SIG2 0xde
1199 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1200 #define VSD_OFFSET_TS_BOARD_ID 0x20
1201
1202 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1203
1204 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1205
1206 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1207 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1208 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1209 } else {
1210 /*
1211 * The board ID is a string but the firmware byte
1212 * swaps each 4-byte word before passing it back to
1213 * us. Therefore we need to swab it before printing.
1214 */
1215 for (i = 0; i < 4; ++i)
1216 ((u32 *) board_id)[i] =
1217 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1218 }
1219 }
1220
1221 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1222 struct mthca_adapter *adapter, u8 *status)
1223 {
1224 struct mthca_mailbox *mailbox;
1225 u32 *outbox;
1226 int err;
1227
1228 #define QUERY_ADAPTER_OUT_SIZE 0x100
1229 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1230 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1231 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1232 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1233 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1234
1235 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1236 if (IS_ERR(mailbox))
1237 return PTR_ERR(mailbox);
1238 outbox = mailbox->buf;
1239
1240 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1241 CMD_TIME_CLASS_A, status);
1242
1243 if (err)
1244 goto out;
1245
1246 if (!mthca_is_memfree(dev)) {
1247 MTHCA_GET(adapter->vendor_id, outbox,
1248 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1249 MTHCA_GET(adapter->device_id, outbox,
1250 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1251 MTHCA_GET(adapter->revision_id, outbox,
1252 QUERY_ADAPTER_REVISION_ID_OFFSET);
1253 }
1254 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1255
1256 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1257 adapter->board_id);
1258
1259 out:
1260 mthca_free_mailbox(dev, mailbox);
1261 return err;
1262 }
1263
1264 int mthca_INIT_HCA(struct mthca_dev *dev,
1265 struct mthca_init_hca_param *param,
1266 u8 *status)
1267 {
1268 struct mthca_mailbox *mailbox;
1269 __be32 *inbox;
1270 int err;
1271
1272 #define INIT_HCA_IN_SIZE 0x200
1273 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1274 #define INIT_HCA_FLAGS2_OFFSET 0x014
1275 #define INIT_HCA_QPC_OFFSET 0x020
1276 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1277 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1278 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1279 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1280 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1281 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1282 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1283 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1284 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1285 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1286 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1287 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1288 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1289 #define INIT_HCA_UDAV_OFFSET 0x0b0
1290 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1291 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1292 #define INIT_HCA_MCAST_OFFSET 0x0c0
1293 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1294 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1295 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1296 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1297 #define INIT_HCA_TPT_OFFSET 0x0f0
1298 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1299 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1300 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1301 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1302 #define INIT_HCA_UAR_OFFSET 0x120
1303 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1304 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1305 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1306 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1307 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1308 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1309
1310 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1311 if (IS_ERR(mailbox))
1312 return PTR_ERR(mailbox);
1313 inbox = mailbox->buf;
1314
1315 memset(inbox, 0, INIT_HCA_IN_SIZE);
1316
1317 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1318 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1319
1320 #if defined(__LITTLE_ENDIAN)
1321 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1322 #elif defined(__BIG_ENDIAN)
1323 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1324 #else
1325 #error Host endianness not defined
1326 #endif
1327 /* Check port for UD address vector: */
1328 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1329
1330 /* Enable IPoIB checksumming if we can: */
1331 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1332 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1333
1334 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1335
1336 /* QPC/EEC/CQC/EQC/RDB attributes */
1337
1338 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1339 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1340 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1341 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1342 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1343 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1344 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1345 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1346 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1347 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1348 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1349 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1350 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1351
1352 /* UD AV attributes */
1353
1354 /* multicast attributes */
1355
1356 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1357 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1358 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1359 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1360
1361 /* TPT attributes */
1362
1363 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1364 if (!mthca_is_memfree(dev))
1365 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1366 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1367 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1368
1369 /* UAR attributes */
1370 {
1371 u8 uar_page_sz = PAGE_SHIFT - 12;
1372 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1373 }
1374
1375 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1376
1377 if (mthca_is_memfree(dev)) {
1378 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1379 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1380 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1381 }
1382
1383 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status);
1384
1385 mthca_free_mailbox(dev, mailbox);
1386 return err;
1387 }
1388
1389 int mthca_INIT_IB(struct mthca_dev *dev,
1390 struct mthca_init_ib_param *param,
1391 int port, u8 *status)
1392 {
1393 struct mthca_mailbox *mailbox;
1394 u32 *inbox;
1395 int err;
1396 u32 flags;
1397
1398 #define INIT_IB_IN_SIZE 56
1399 #define INIT_IB_FLAGS_OFFSET 0x00
1400 #define INIT_IB_FLAG_SIG (1 << 18)
1401 #define INIT_IB_FLAG_NG (1 << 17)
1402 #define INIT_IB_FLAG_G0 (1 << 16)
1403 #define INIT_IB_VL_SHIFT 4
1404 #define INIT_IB_PORT_WIDTH_SHIFT 8
1405 #define INIT_IB_MTU_SHIFT 12
1406 #define INIT_IB_MAX_GID_OFFSET 0x06
1407 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1408 #define INIT_IB_GUID0_OFFSET 0x10
1409 #define INIT_IB_NODE_GUID_OFFSET 0x18
1410 #define INIT_IB_SI_GUID_OFFSET 0x20
1411
1412 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1413 if (IS_ERR(mailbox))
1414 return PTR_ERR(mailbox);
1415 inbox = mailbox->buf;
1416
1417 memset(inbox, 0, INIT_IB_IN_SIZE);
1418
1419 flags = 0;
1420 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1421 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1422 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1423 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1424 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1425 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1426 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1427
1428 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1429 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1430 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1431 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1432 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1433
1434 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1435 CMD_TIME_CLASS_A, status);
1436
1437 mthca_free_mailbox(dev, mailbox);
1438 return err;
1439 }
1440
1441 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1442 {
1443 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status);
1444 }
1445
1446 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1447 {
1448 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status);
1449 }
1450
1451 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1452 int port, u8 *status)
1453 {
1454 struct mthca_mailbox *mailbox;
1455 u32 *inbox;
1456 int err;
1457 u32 flags = 0;
1458
1459 #define SET_IB_IN_SIZE 0x40
1460 #define SET_IB_FLAGS_OFFSET 0x00
1461 #define SET_IB_FLAG_SIG (1 << 18)
1462 #define SET_IB_FLAG_RQK (1 << 0)
1463 #define SET_IB_CAP_MASK_OFFSET 0x04
1464 #define SET_IB_SI_GUID_OFFSET 0x08
1465
1466 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1467 if (IS_ERR(mailbox))
1468 return PTR_ERR(mailbox);
1469 inbox = mailbox->buf;
1470
1471 memset(inbox, 0, SET_IB_IN_SIZE);
1472
1473 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1474 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1475 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1476
1477 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1478 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1479
1480 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1481 CMD_TIME_CLASS_B, status);
1482
1483 mthca_free_mailbox(dev, mailbox);
1484 return err;
1485 }
1486
1487 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1488 {
1489 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1490 }
1491
1492 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1493 {
1494 struct mthca_mailbox *mailbox;
1495 __be64 *inbox;
1496 int err;
1497
1498 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1499 if (IS_ERR(mailbox))
1500 return PTR_ERR(mailbox);
1501 inbox = mailbox->buf;
1502
1503 inbox[0] = cpu_to_be64(virt);
1504 inbox[1] = cpu_to_be64(dma_addr);
1505
1506 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1507 CMD_TIME_CLASS_B, status);
1508
1509 mthca_free_mailbox(dev, mailbox);
1510
1511 if (!err)
1512 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1513 (unsigned long long) dma_addr, (unsigned long long) virt);
1514
1515 return err;
1516 }
1517
1518 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1519 {
1520 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1521 page_count, (unsigned long long) virt);
1522
1523 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1524 }
1525
1526 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1527 {
1528 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1529 }
1530
1531 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1532 {
1533 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1534 }
1535
1536 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1537 u8 *status)
1538 {
1539 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1540 CMD_TIME_CLASS_A, status);
1541
1542 if (ret || status)
1543 return ret;
1544
1545 /*
1546 * Round up number of system pages needed in case
1547 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1548 */
1549 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1550 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1551
1552 return 0;
1553 }
1554
1555 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1556 int mpt_index, u8 *status)
1557 {
1558 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1559 CMD_TIME_CLASS_B, status);
1560 }
1561
1562 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1563 int mpt_index, u8 *status)
1564 {
1565 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1566 !mailbox, CMD_HW2SW_MPT,
1567 CMD_TIME_CLASS_B, status);
1568 }
1569
1570 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1571 int num_mtt, u8 *status)
1572 {
1573 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1574 CMD_TIME_CLASS_B, status);
1575 }
1576
1577 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1578 {
1579 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1580 }
1581
1582 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1583 int eq_num, u8 *status)
1584 {
1585 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1586 unmap ? "Clearing" : "Setting",
1587 (unsigned long long) event_mask, eq_num);
1588 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1589 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1590 }
1591
1592 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1593 int eq_num, u8 *status)
1594 {
1595 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1596 CMD_TIME_CLASS_A, status);
1597 }
1598
1599 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1600 int eq_num, u8 *status)
1601 {
1602 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1603 CMD_HW2SW_EQ,
1604 CMD_TIME_CLASS_A, status);
1605 }
1606
1607 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1608 int cq_num, u8 *status)
1609 {
1610 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1611 CMD_TIME_CLASS_A, status);
1612 }
1613
1614 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1615 int cq_num, u8 *status)
1616 {
1617 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1618 CMD_HW2SW_CQ,
1619 CMD_TIME_CLASS_A, status);
1620 }
1621
1622 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
1623 u8 *status)
1624 {
1625 struct mthca_mailbox *mailbox;
1626 __be32 *inbox;
1627 int err;
1628
1629 #define RESIZE_CQ_IN_SIZE 0x40
1630 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1631 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1632
1633 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1634 if (IS_ERR(mailbox))
1635 return PTR_ERR(mailbox);
1636 inbox = mailbox->buf;
1637
1638 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1639 /*
1640 * Leave start address fields zeroed out -- mthca assumes that
1641 * MRs for CQs always start at virtual address 0.
1642 */
1643 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1644 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1645
1646 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1647 CMD_TIME_CLASS_B, status);
1648
1649 mthca_free_mailbox(dev, mailbox);
1650 return err;
1651 }
1652
1653 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1654 int srq_num, u8 *status)
1655 {
1656 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1657 CMD_TIME_CLASS_A, status);
1658 }
1659
1660 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1661 int srq_num, u8 *status)
1662 {
1663 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1664 CMD_HW2SW_SRQ,
1665 CMD_TIME_CLASS_A, status);
1666 }
1667
1668 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1669 struct mthca_mailbox *mailbox, u8 *status)
1670 {
1671 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1672 CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
1673 }
1674
1675 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1676 {
1677 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1678 CMD_TIME_CLASS_B, status);
1679 }
1680
1681 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1682 enum ib_qp_state next, u32 num, int is_ee,
1683 struct mthca_mailbox *mailbox, u32 optmask,
1684 u8 *status)
1685 {
1686 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1687 [IB_QPS_RESET] = {
1688 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1689 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1690 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1691 },
1692 [IB_QPS_INIT] = {
1693 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1694 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1695 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1696 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1697 },
1698 [IB_QPS_RTR] = {
1699 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1700 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1701 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1702 },
1703 [IB_QPS_RTS] = {
1704 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1705 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1706 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1707 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1708 },
1709 [IB_QPS_SQD] = {
1710 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1711 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1712 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1713 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1714 },
1715 [IB_QPS_SQE] = {
1716 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1717 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1718 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1719 },
1720 [IB_QPS_ERR] = {
1721 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1722 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1723 }
1724 };
1725
1726 u8 op_mod = 0;
1727 int my_mailbox = 0;
1728 int err;
1729
1730 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1731 op_mod = 3; /* don't write outbox, any->reset */
1732
1733 /* For debugging */
1734 if (!mailbox) {
1735 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1736 if (!IS_ERR(mailbox)) {
1737 my_mailbox = 1;
1738 op_mod = 2; /* write outbox, any->reset */
1739 } else
1740 mailbox = NULL;
1741 }
1742
1743 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1744 (!!is_ee << 24) | num, op_mod,
1745 op[cur][next], CMD_TIME_CLASS_C, status);
1746
1747 if (0 && mailbox) {
1748 int i;
1749 mthca_dbg(dev, "Dumping QP context:\n");
1750 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1751 for (i = 0; i < 0x100 / 4; ++i) {
1752 if (i % 8 == 0)
1753 printk("[%02x] ", i * 4);
1754 printk(" %08x",
1755 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1756 if ((i + 1) % 8 == 0)
1757 printk("\n");
1758 }
1759 }
1760
1761 if (my_mailbox)
1762 mthca_free_mailbox(dev, mailbox);
1763 } else {
1764 if (0) {
1765 int i;
1766 mthca_dbg(dev, "Dumping QP context:\n");
1767 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1768 for (i = 0; i < 0x100 / 4; ++i) {
1769 if (i % 8 == 0)
1770 printk(" [%02x] ", i * 4);
1771 printk(" %08x",
1772 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1773 if ((i + 1) % 8 == 0)
1774 printk("\n");
1775 }
1776 }
1777
1778 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1779 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1780 }
1781
1782 return err;
1783 }
1784
1785 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1786 struct mthca_mailbox *mailbox, u8 *status)
1787 {
1788 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1789 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1790 }
1791
1792 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1793 u8 *status)
1794 {
1795 u8 op_mod;
1796
1797 switch (type) {
1798 case IB_QPT_SMI:
1799 op_mod = 0;
1800 break;
1801 case IB_QPT_GSI:
1802 op_mod = 1;
1803 break;
1804 case IB_QPT_RAW_IPV6:
1805 op_mod = 2;
1806 break;
1807 case IB_QPT_RAW_ETHERTYPE:
1808 op_mod = 3;
1809 break;
1810 default:
1811 return -EINVAL;
1812 }
1813
1814 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1815 CMD_TIME_CLASS_B, status);
1816 }
1817
1818 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1819 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1820 void *in_mad, void *response_mad, u8 *status)
1821 {
1822 struct mthca_mailbox *inmailbox, *outmailbox;
1823 void *inbox;
1824 int err;
1825 u32 in_modifier = port;
1826 u8 op_modifier = 0;
1827
1828 #define MAD_IFC_BOX_SIZE 0x400
1829 #define MAD_IFC_MY_QPN_OFFSET 0x100
1830 #define MAD_IFC_RQPN_OFFSET 0x108
1831 #define MAD_IFC_SL_OFFSET 0x10c
1832 #define MAD_IFC_G_PATH_OFFSET 0x10d
1833 #define MAD_IFC_RLID_OFFSET 0x10e
1834 #define MAD_IFC_PKEY_OFFSET 0x112
1835 #define MAD_IFC_GRH_OFFSET 0x140
1836
1837 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1838 if (IS_ERR(inmailbox))
1839 return PTR_ERR(inmailbox);
1840 inbox = inmailbox->buf;
1841
1842 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1843 if (IS_ERR(outmailbox)) {
1844 mthca_free_mailbox(dev, inmailbox);
1845 return PTR_ERR(outmailbox);
1846 }
1847
1848 memcpy(inbox, in_mad, 256);
1849
1850 /*
1851 * Key check traps can't be generated unless we have in_wc to
1852 * tell us where to send the trap.
1853 */
1854 if (ignore_mkey || !in_wc)
1855 op_modifier |= 0x1;
1856 if (ignore_bkey || !in_wc)
1857 op_modifier |= 0x2;
1858
1859 if (in_wc) {
1860 u8 val;
1861
1862 memset(inbox + 256, 0, 256);
1863
1864 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1865 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1866
1867 val = in_wc->sl << 4;
1868 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1869
1870 val = in_wc->dlid_path_bits |
1871 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1872 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1873
1874 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1875 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1876
1877 if (in_grh)
1878 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1879
1880 op_modifier |= 0x4;
1881
1882 in_modifier |= in_wc->slid << 16;
1883 }
1884
1885 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1886 in_modifier, op_modifier,
1887 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1888
1889 if (!err && !*status)
1890 memcpy(response_mad, outmailbox->buf, 256);
1891
1892 mthca_free_mailbox(dev, inmailbox);
1893 mthca_free_mailbox(dev, outmailbox);
1894 return err;
1895 }
1896
1897 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1898 struct mthca_mailbox *mailbox, u8 *status)
1899 {
1900 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1901 CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1902 }
1903
1904 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1905 struct mthca_mailbox *mailbox, u8 *status)
1906 {
1907 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1908 CMD_TIME_CLASS_A, status);
1909 }
1910
1911 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1912 u16 *hash, u8 *status)
1913 {
1914 u64 imm;
1915 int err;
1916
1917 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1918 CMD_TIME_CLASS_A, status);
1919
1920 *hash = imm;
1921 return err;
1922 }
1923
1924 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1925 {
1926 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1927 }
Tomato firmware and modifications.