release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48 #include <linux/kfifo.h>
  49
  50 #include <asm/byteorder.h>
  51
  52 #include <net/net_namespace.h>
  53
  54 #include <rdma/ib_verbs.h>
  55 #include <rdma/iw_cm.h>
  56
  57 #include "cxgb4.h"
  58 #include "cxgb4_uld.h"
  59 #include "l2t.h"
  60 #include "user.h"
  61
  62 #define DRV_NAME "iw_cxgb4"
  63 #define MOD DRV_NAME ":"
  64
  65 extern int c4iw_debug;
  66 #define PDBG(fmt, args...) \
  67 do { \
  68         if (c4iw_debug) \
  69                 printk(MOD fmt, ## args); \
  70 } while (0)
  71
  72 #include "t4.h"
  73
  74 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  75 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  76
  77 static inline void *cplhdr(struct sk_buff *skb)
  78 {
  79         return skb->data;
  80 }
  81
  82 #define C4IW_WR_TO (10*HZ)
  83
  84 struct c4iw_wr_wait {
  85         wait_queue_head_t wait;
  86         int done;
  87         int ret;
  88 };
  89
  90 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
  91 {
  92         wr_waitp->ret = 0;
  93         wr_waitp->done = 0;
  94         init_waitqueue_head(&wr_waitp->wait);
  95 }
  96
  97 struct c4iw_resource {
  98         struct kfifo tpt_fifo;
  99         spinlock_t tpt_fifo_lock;
 100         struct kfifo qid_fifo;
 101         spinlock_t qid_fifo_lock;
 102         struct kfifo pdid_fifo;
 103         spinlock_t pdid_fifo_lock;
 104 };
 105
 106 struct c4iw_qid_list {
 107         struct list_head entry;
 108         u32 qid;
 109 };
 110
 111 struct c4iw_dev_ucontext {
 112         struct list_head qpids;
 113         struct list_head cqids;
 114         struct mutex lock;
 115 };
 116
 117 enum c4iw_rdev_flags {
 118         T4_FATAL_ERROR = (1<<0),
 119 };
 120
 121 struct c4iw_rdev {
 122         struct c4iw_resource resource;
 123         unsigned long qpshift;
 124         u32 qpmask;
 125         unsigned long cqshift;
 126         u32 cqmask;
 127         struct c4iw_dev_ucontext uctx;
 128         struct gen_pool *pbl_pool;
 129         struct gen_pool *rqt_pool;
 130         u32 flags;
 131         struct cxgb4_lld_info lldi;
 132 };
 133
 134 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 135 {
 136         return rdev->flags & T4_FATAL_ERROR;
 137 }
 138
 139 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 140 {
 141         return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
 142 }
 143
 144 struct c4iw_dev {
 145         struct ib_device ibdev;
 146         struct c4iw_rdev rdev;
 147         u32 device_cap_flags;
 148         struct idr cqidr;
 149         struct idr qpidr;
 150         struct idr mmidr;
 151         spinlock_t lock;
 152         struct list_head entry;
 153         struct delayed_work db_drop_task;
 154         struct dentry *debugfs_root;
 155         u8 registered;
 156 };
 157
 158 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 159 {
 160         return container_of(ibdev, struct c4iw_dev, ibdev);
 161 }
 162
 163 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 164 {
 165         return container_of(rdev, struct c4iw_dev, rdev);
 166 }
 167
 168 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 169 {
 170         return idr_find(&rhp->cqidr, cqid);
 171 }
 172
 173 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 174 {
 175         return idr_find(&rhp->qpidr, qpid);
 176 }
 177
 178 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 179 {
 180         return idr_find(&rhp->mmidr, mmid);
 181 }
 182
 183 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 184                                 void *handle, u32 id)
 185 {
 186         int ret;
 187         int newid;
 188
 189         do {
 190                 if (!idr_pre_get(idr, GFP_KERNEL))
 191                         return -ENOMEM;
 192                 spin_lock_irq(&rhp->lock);
 193                 ret = idr_get_new_above(idr, handle, id, &newid);
 194                 BUG_ON(newid != id);
 195                 spin_unlock_irq(&rhp->lock);
 196         } while (ret == -EAGAIN);
 197
 198         return ret;
 199 }
 200
 201 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 202 {
 203         spin_lock_irq(&rhp->lock);
 204         idr_remove(idr, id);
 205         spin_unlock_irq(&rhp->lock);
 206 }
 207
 208 struct c4iw_pd {
 209         struct ib_pd ibpd;
 210         u32 pdid;
 211         struct c4iw_dev *rhp;
 212 };
 213
 214 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 215 {
 216         return container_of(ibpd, struct c4iw_pd, ibpd);
 217 }
 218
 219 struct tpt_attributes {
 220         u64 len;
 221         u64 va_fbo;
 222         enum fw_ri_mem_perms perms;
 223         u32 stag;
 224         u32 pdid;
 225         u32 qpid;
 226         u32 pbl_addr;
 227         u32 pbl_size;
 228         u32 state:1;
 229         u32 type:2;
 230         u32 rsvd:1;
 231         u32 remote_invaliate_disable:1;
 232         u32 zbva:1;
 233         u32 mw_bind_enable:1;
 234         u32 page_size:5;
 235 };
 236
 237 struct c4iw_mr {
 238         struct ib_mr ibmr;
 239         struct ib_umem *umem;
 240         struct c4iw_dev *rhp;
 241         u64 kva;
 242         struct tpt_attributes attr;
 243 };
 244
 245 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 246 {
 247         return container_of(ibmr, struct c4iw_mr, ibmr);
 248 }
 249
 250 struct c4iw_mw {
 251         struct ib_mw ibmw;
 252         struct c4iw_dev *rhp;
 253         u64 kva;
 254         struct tpt_attributes attr;
 255 };
 256
 257 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 258 {
 259         return container_of(ibmw, struct c4iw_mw, ibmw);
 260 }
 261
 262 struct c4iw_fr_page_list {
 263         struct ib_fast_reg_page_list ibpl;
 264         DEFINE_DMA_UNMAP_ADDR(mapping);
 265         dma_addr_t dma_addr;
 266         struct c4iw_dev *dev;
 267         int size;
 268 };
 269
 270 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 271                                         struct ib_fast_reg_page_list *ibpl)
 272 {
 273         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 274 }
 275
 276 struct c4iw_cq {
 277         struct ib_cq ibcq;
 278         struct c4iw_dev *rhp;
 279         struct t4_cq cq;
 280         spinlock_t lock;
 281         atomic_t refcnt;
 282         wait_queue_head_t wait;
 283 };
 284
 285 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 286 {
 287         return container_of(ibcq, struct c4iw_cq, ibcq);
 288 }
 289
 290 struct c4iw_mpa_attributes {
 291         u8 initiator;
 292         u8 recv_marker_enabled;
 293         u8 xmit_marker_enabled;
 294         u8 crc_enabled;
 295         u8 version;
 296         u8 p2p_type;
 297 };
 298
 299 struct c4iw_qp_attributes {
 300         u32 scq;
 301         u32 rcq;
 302         u32 sq_num_entries;
 303         u32 rq_num_entries;
 304         u32 sq_max_sges;
 305         u32 sq_max_sges_rdma_write;
 306         u32 rq_max_sges;
 307         u32 state;
 308         u8 enable_rdma_read;
 309         u8 enable_rdma_write;
 310         u8 enable_bind;
 311         u8 enable_mmid0_fastreg;
 312         u32 max_ord;
 313         u32 max_ird;
 314         u32 pd;
 315         u32 next_state;
 316         char terminate_buffer[52];
 317         u32 terminate_msg_len;
 318         u8 is_terminate_local;
 319         struct c4iw_mpa_attributes mpa_attr;
 320         struct c4iw_ep *llp_stream_handle;
 321 };
 322
 323 struct c4iw_qp {
 324         struct ib_qp ibqp;
 325         struct c4iw_dev *rhp;
 326         struct c4iw_ep *ep;
 327         struct c4iw_qp_attributes attr;
 328         struct t4_wq wq;
 329         spinlock_t lock;
 330         atomic_t refcnt;
 331         wait_queue_head_t wait;
 332         struct timer_list timer;
 333 };
 334
 335 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 336 {
 337         return container_of(ibqp, struct c4iw_qp, ibqp);
 338 }
 339
 340 struct c4iw_ucontext {
 341         struct ib_ucontext ibucontext;
 342         struct c4iw_dev_ucontext uctx;
 343         u32 key;
 344         spinlock_t mmap_lock;
 345         struct list_head mmaps;
 346 };
 347
 348 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 349 {
 350         return container_of(c, struct c4iw_ucontext, ibucontext);
 351 }
 352
 353 struct c4iw_mm_entry {
 354         struct list_head entry;
 355         u64 addr;
 356         u32 key;
 357         unsigned len;
 358 };
 359
 360 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 361                                                 u32 key, unsigned len)
 362 {
 363         struct list_head *pos, *nxt;
 364         struct c4iw_mm_entry *mm;
 365
 366         spin_lock(&ucontext->mmap_lock);
 367         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 368
 369                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 370                 if (mm->key == key && mm->len == len) {
 371                         list_del_init(&mm->entry);
 372                         spin_unlock(&ucontext->mmap_lock);
 373                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 374                              key, (unsigned long long) mm->addr, mm->len);
 375                         return mm;
 376                 }
 377         }
 378         spin_unlock(&ucontext->mmap_lock);
 379         return NULL;
 380 }
 381
 382 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 383                                struct c4iw_mm_entry *mm)
 384 {
 385         spin_lock(&ucontext->mmap_lock);
 386         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 387              mm->key, (unsigned long long) mm->addr, mm->len);
 388         list_add_tail(&mm->entry, &ucontext->mmaps);
 389         spin_unlock(&ucontext->mmap_lock);
 390 }
 391
 392 enum c4iw_qp_attr_mask {
 393         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 394         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 395         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 396         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 397         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 398         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 399         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 400         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 401         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 402         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 403         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 404                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 405                                      C4IW_QP_ATTR_MAX_ORD |
 406                                      C4IW_QP_ATTR_MAX_IRD |
 407                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 408                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 409                                      C4IW_QP_ATTR_MPA_ATTR |
 410                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 411 };
 412
 413 int c4iw_modify_qp(struct c4iw_dev *rhp,
 414                                 struct c4iw_qp *qhp,
 415                                 enum c4iw_qp_attr_mask mask,
 416                                 struct c4iw_qp_attributes *attrs,
 417                                 int internal);
 418
 419 enum c4iw_qp_state {
 420         C4IW_QP_STATE_IDLE,
 421         C4IW_QP_STATE_RTS,
 422         C4IW_QP_STATE_ERROR,
 423         C4IW_QP_STATE_TERMINATE,
 424         C4IW_QP_STATE_CLOSING,
 425         C4IW_QP_STATE_TOT
 426 };
 427
 428 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 429 {
 430         switch (ib_state) {
 431         case IB_QPS_RESET:
 432         case IB_QPS_INIT:
 433                 return C4IW_QP_STATE_IDLE;
 434         case IB_QPS_RTS:
 435                 return C4IW_QP_STATE_RTS;
 436         case IB_QPS_SQD:
 437                 return C4IW_QP_STATE_CLOSING;
 438         case IB_QPS_SQE:
 439                 return C4IW_QP_STATE_TERMINATE;
 440         case IB_QPS_ERR:
 441                 return C4IW_QP_STATE_ERROR;
 442         default:
 443                 return -1;
 444         }
 445 }
 446
 447 static inline u32 c4iw_ib_to_tpt_access(int a)
 448 {
 449         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 450                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 451                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 452                FW_RI_MEM_ACCESS_LOCAL_READ;
 453 }
 454
 455 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 456 {
 457         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 458                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 459 }
 460
 461 enum c4iw_mmid_state {
 462         C4IW_STAG_STATE_VALID,
 463         C4IW_STAG_STATE_INVALID
 464 };
 465
 466 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 467
 468 #define MPA_KEY_REQ "MPA ID Req Frame"
 469 #define MPA_KEY_REP "MPA ID Rep Frame"
 470
 471 #define MPA_MAX_PRIVATE_DATA    256
 472 #define MPA_REJECT              0x20
 473 #define MPA_CRC                 0x40
 474 #define MPA_MARKERS             0x80
 475 #define MPA_FLAGS_MASK          0xE0
 476
 477 #define c4iw_put_ep(ep) { \
 478         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 479              ep, atomic_read(&((ep)->kref.refcount))); \
 480         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 481         kref_put(&((ep)->kref), _c4iw_free_ep); \
 482 }
 483
 484 #define c4iw_get_ep(ep) { \
 485         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 486              ep, atomic_read(&((ep)->kref.refcount))); \
 487         kref_get(&((ep)->kref));  \
 488 }
 489 void _c4iw_free_ep(struct kref *kref);
 490
 491 struct mpa_message {
 492         u8 key[16];
 493         u8 flags;
 494         u8 revision;
 495         __be16 private_data_size;
 496         u8 private_data[0];
 497 };
 498
 499 struct terminate_message {
 500         u8 layer_etype;
 501         u8 ecode;
 502         __be16 hdrct_rsvd;
 503         u8 len_hdrs[0];
 504 };
 505
 506 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 507
 508 enum c4iw_layers_types {
 509         LAYER_RDMAP             = 0x00,
 510         LAYER_DDP               = 0x10,
 511         LAYER_MPA               = 0x20,
 512         RDMAP_LOCAL_CATA        = 0x00,
 513         RDMAP_REMOTE_PROT       = 0x01,
 514         RDMAP_REMOTE_OP         = 0x02,
 515         DDP_LOCAL_CATA          = 0x00,
 516         DDP_TAGGED_ERR          = 0x01,
 517         DDP_UNTAGGED_ERR        = 0x02,
 518         DDP_LLP                 = 0x03
 519 };
 520
 521 enum c4iw_rdma_ecodes {
 522         RDMAP_INV_STAG          = 0x00,
 523         RDMAP_BASE_BOUNDS       = 0x01,
 524         RDMAP_ACC_VIOL          = 0x02,
 525         RDMAP_STAG_NOT_ASSOC    = 0x03,
 526         RDMAP_TO_WRAP           = 0x04,
 527         RDMAP_INV_VERS          = 0x05,
 528         RDMAP_INV_OPCODE        = 0x06,
 529         RDMAP_STREAM_CATA       = 0x07,
 530         RDMAP_GLOBAL_CATA       = 0x08,
 531         RDMAP_CANT_INV_STAG     = 0x09,
 532         RDMAP_UNSPECIFIED       = 0xff
 533 };
 534
 535 enum c4iw_ddp_ecodes {
 536         DDPT_INV_STAG           = 0x00,
 537         DDPT_BASE_BOUNDS        = 0x01,
 538         DDPT_STAG_NOT_ASSOC     = 0x02,
 539         DDPT_TO_WRAP            = 0x03,
 540         DDPT_INV_VERS           = 0x04,
 541         DDPU_INV_QN             = 0x01,
 542         DDPU_INV_MSN_NOBUF      = 0x02,
 543         DDPU_INV_MSN_RANGE      = 0x03,
 544         DDPU_INV_MO             = 0x04,
 545         DDPU_MSG_TOOBIG         = 0x05,
 546         DDPU_INV_VERS           = 0x06
 547 };
 548
 549 enum c4iw_mpa_ecodes {
 550         MPA_CRC_ERR             = 0x02,
 551         MPA_MARKER_ERR          = 0x03
 552 };
 553
 554 enum c4iw_ep_state {
 555         IDLE = 0,
 556         LISTEN,
 557         CONNECTING,
 558         MPA_REQ_WAIT,
 559         MPA_REQ_SENT,
 560         MPA_REQ_RCVD,
 561         MPA_REP_SENT,
 562         FPDU_MODE,
 563         ABORTING,
 564         CLOSING,
 565         MORIBUND,
 566         DEAD,
 567 };
 568
 569 enum c4iw_ep_flags {
 570         PEER_ABORT_IN_PROGRESS  = 0,
 571         ABORT_REQ_IN_PROGRESS   = 1,
 572         RELEASE_RESOURCES       = 2,
 573         CLOSE_SENT              = 3,
 574 };
 575
 576 struct c4iw_ep_common {
 577         struct iw_cm_id *cm_id;
 578         struct c4iw_qp *qp;
 579         struct c4iw_dev *dev;
 580         enum c4iw_ep_state state;
 581         struct kref kref;
 582         spinlock_t lock;
 583         struct sockaddr_in local_addr;
 584         struct sockaddr_in remote_addr;
 585         wait_queue_head_t waitq;
 586         int rpl_done;
 587         int rpl_err;
 588         unsigned long flags;
 589 };
 590
 591 struct c4iw_listen_ep {
 592         struct c4iw_ep_common com;
 593         unsigned int stid;
 594         int backlog;
 595 };
 596
 597 struct c4iw_ep {
 598         struct c4iw_ep_common com;
 599         struct c4iw_ep *parent_ep;
 600         struct timer_list timer;
 601         struct list_head entry;
 602         unsigned int atid;
 603         u32 hwtid;
 604         u32 snd_seq;
 605         u32 rcv_seq;
 606         struct l2t_entry *l2t;
 607         struct dst_entry *dst;
 608         struct sk_buff *mpa_skb;
 609         struct c4iw_mpa_attributes mpa_attr;
 610         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 611         unsigned int mpa_pkt_len;
 612         u32 ird;
 613         u32 ord;
 614         u32 smac_idx;
 615         u32 tx_chan;
 616         u32 mtu;
 617         u16 mss;
 618         u16 emss;
 619         u16 plen;
 620         u16 rss_qid;
 621         u16 txq_idx;
 622         u16 ctrlq_idx;
 623         u8 tos;
 624 };
 625
 626 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 627 {
 628         return cm_id->provider_data;
 629 }
 630
 631 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 632 {
 633         return cm_id->provider_data;
 634 }
 635
 636 static inline int compute_wscale(int win)
 637 {
 638         int wscale = 0;
 639
 640         while (wscale < 14 && (65535<<wscale) < win)
 641                 wscale++;
 642         return wscale;
 643 }
 644
 645 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 646
 647 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 648                      struct l2t_entry *l2t);
 649 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 650                    struct c4iw_dev_ucontext *uctx);
 651 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
 652 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
 653 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 654 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 655 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 656 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 657 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 658 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 659 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 660 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 661 int c4iw_register_device(struct c4iw_dev *dev);
 662 void c4iw_unregister_device(struct c4iw_dev *dev);
 663 int __init c4iw_cm_init(void);
 664 void __exit c4iw_cm_term(void);
 665 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 666                                struct c4iw_dev_ucontext *uctx);
 667 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 668                             struct c4iw_dev_ucontext *uctx);
 669 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 670 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 671                       struct ib_send_wr **bad_wr);
 672 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 673                       struct ib_recv_wr **bad_wr);
 674 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 675                  struct ib_mw_bind *mw_bind);
 676 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 677 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 678 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 679 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 680 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 681 void c4iw_qp_add_ref(struct ib_qp *qp);
 682 void c4iw_qp_rem_ref(struct ib_qp *qp);
 683 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 684 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 685                                         struct ib_device *device,
 686                                         int page_list_len);
 687 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
 688 int c4iw_dealloc_mw(struct ib_mw *mw);
 689 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
 690 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 691                                            u64 length, u64 virt, int acc,
 692                                            struct ib_udata *udata);
 693 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 694 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 695                                         struct ib_phys_buf *buffer_list,
 696                                         int num_phys_buf,
 697                                         int acc,
 698                                         u64 *iova_start);
 699 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 700                                      int mr_rereg_mask,
 701                                      struct ib_pd *pd,
 702                                      struct ib_phys_buf *buffer_list,
 703                                      int num_phys_buf,
 704                                      int acc, u64 *iova_start);
 705 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 706 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 707 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 708                                         int vector,
 709                                         struct ib_ucontext *ib_context,
 710                                         struct ib_udata *udata);
 711 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 712 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 713 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 714 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 715                              struct ib_qp_init_attr *attrs,
 716                              struct ib_udata *udata);
 717 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 718                                  int attr_mask, struct ib_udata *udata);
 719 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
 720 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
 721 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 722 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
 723 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 724 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
 725 void c4iw_flush_hw_cq(struct t4_cq *cq);
 726 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 727 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 728 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
 729 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
 730 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
 731 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
 732 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
 733 int c4iw_post_zb_read(struct c4iw_qp *qhp);
 734 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
 735 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 736 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
 737                 struct c4iw_dev_ucontext *uctx);
 738 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 739 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
 740                 struct c4iw_dev_ucontext *uctx);
 741 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
 742
 743 extern struct cxgb4_client t4c_client;
 744 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
 745 extern int c4iw_max_read_depth;
 746
 747 #endif