release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/i2c/busses/i2c-piix4.c

   1 /*
   2     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   3     Philip Edelbrock <phil@netroedge.com>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21    Supports:
  22         Intel PIIX4, 440MX
  23         Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  24         ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
  25         AMD Hudson-2
  26         SMSC Victory66
  27
  28    Note: we assume there can only be one device, with one SMBus interface.
  29 */
  30
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/stddef.h>
  37 #include <linux/ioport.h>
  38 #include <linux/i2c.h>
  39 #include <linux/init.h>
  40 #include <linux/dmi.h>
  41 #include <linux/acpi.h>
  42 #include <linux/io.h>
  43
  44
  45 /* PIIX4 SMBus address offsets */
  46 #define SMBHSTSTS       (0 + piix4_smba)
  47 #define SMBHSLVSTS      (1 + piix4_smba)
  48 #define SMBHSTCNT       (2 + piix4_smba)
  49 #define SMBHSTCMD       (3 + piix4_smba)
  50 #define SMBHSTADD       (4 + piix4_smba)
  51 #define SMBHSTDAT0      (5 + piix4_smba)
  52 #define SMBHSTDAT1      (6 + piix4_smba)
  53 #define SMBBLKDAT       (7 + piix4_smba)
  54 #define SMBSLVCNT       (8 + piix4_smba)
  55 #define SMBSHDWCMD      (9 + piix4_smba)
  56 #define SMBSLVEVT       (0xA + piix4_smba)
  57 #define SMBSLVDAT       (0xC + piix4_smba)
  58
  59 /* count for request_region */
  60 #define SMBIOSIZE       8
  61
  62 /* PCI Address Constants */
  63 #define SMBBA           0x090
  64 #define SMBHSTCFG       0x0D2
  65 #define SMBSLVC         0x0D3
  66 #define SMBSHDW1        0x0D4
  67 #define SMBSHDW2        0x0D5
  68 #define SMBREV          0x0D6
  69
  70 /* Other settings */
  71 #define MAX_TIMEOUT     500
  72 #define  ENABLE_INT9    0
  73
  74 /* PIIX4 constants */
  75 #define PIIX4_QUICK             0x00
  76 #define PIIX4_BYTE              0x04
  77 #define PIIX4_BYTE_DATA         0x08
  78 #define PIIX4_WORD_DATA         0x0C
  79 #define PIIX4_BLOCK_DATA        0x14
  80
  81 /* insmod parameters */
  82
  83 /* If force is set to anything different from 0, we forcibly enable the
  84    PIIX4. DANGEROUS! */
  85 static int force;
  86 module_param (force, int, 0);
  87 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  88
  89 /* If force_addr is set to anything different from 0, we forcibly enable
  90    the PIIX4 at the given address. VERY DANGEROUS! */
  91 static int force_addr;
  92 module_param (force_addr, int, 0);
  93 MODULE_PARM_DESC(force_addr,
  94                  "Forcibly enable the PIIX4 at the given address. "
  95                  "EXTREMELY DANGEROUS!");
  96
  97 static unsigned short piix4_smba;
  98 static int srvrworks_csb5_delay;
  99 static struct pci_driver piix4_driver;
 100 static struct i2c_adapter piix4_adapter;
 101
 102 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
 103         {
 104                 .ident = "Sapphire AM2RD790",
 105                 .matches = {
 106                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 107                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 108                 },
 109         },
 110         {
 111                 .ident = "DFI Lanparty UT 790FX",
 112                 .matches = {
 113                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 114                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 115                 },
 116         },
 117         { }
 118 };
 119
 120 /* The IBM entry is in a separate table because we only check it
 121    on Intel-based systems */
 122 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
 123         {
 124                 .ident = "IBM",
 125                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 126         },
 127         { },
 128 };
 129
 130 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 131                                 const struct pci_device_id *id)
 132 {
 133         unsigned char temp;
 134
 135         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 136             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 137                 srvrworks_csb5_delay = 1;
 138
 139         /* On some motherboards, it was reported that accessing the SMBus
 140            caused severe hardware problems */
 141         if (dmi_check_system(piix4_dmi_blacklist)) {
 142                 dev_err(&PIIX4_dev->dev,
 143                         "Accessing the SMBus on this system is unsafe!\n");
 144                 return -EPERM;
 145         }
 146
 147         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 148         if (dmi_check_system(piix4_dmi_ibm) &&
 149                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 150                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 151                         "may corrupt your serial eeprom! Refusing to load "
 152                         "module!\n");
 153                 return -EPERM;
 154         }
 155
 156         /* Determine the address of the SMBus areas */
 157         if (force_addr) {
 158                 piix4_smba = force_addr & 0xfff0;
 159                 force = 0;
 160         } else {
 161                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 162                 piix4_smba &= 0xfff0;
 163                 if(piix4_smba == 0) {
 164                         dev_err(&PIIX4_dev->dev, "SMBus base address "
 165                                 "uninitialized - upgrade BIOS or use "
 166                                 "force_addr=0xaddr\n");
 167                         return -ENODEV;
 168                 }
 169         }
 170
 171         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 172                 return -ENODEV;
 173
 174         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 175                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 176                         piix4_smba);
 177                 return -EBUSY;
 178         }
 179
 180         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 181
 182         /* If force_addr is set, we program the new address here. Just to make
 183            sure, we disable the PIIX4 first. */
 184         if (force_addr) {
 185                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 186                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 187                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 188                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 189                         "new address %04x!\n", piix4_smba);
 190         } else if ((temp & 1) == 0) {
 191                 if (force) {
 192                         /* This should never need to be done, but has been
 193                          * noted that many Dell machines have the SMBus
 194                          * interface on the PIIX4 disabled!? NOTE: This assumes
 195                          * I/O space and other allocations WERE done by the
 196                          * Bios!  Don't complain if your hardware does weird
 197                          * things after enabling this. :') Check for Bios
 198                          * updates before resorting to this.
 199                          */
 200                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 201                                               temp | 1);
 202                         dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
 203                                 "WARNING: SMBus interface has been "
 204                                 "FORCEFULLY ENABLED!\n");
 205                 } else {
 206                         dev_err(&PIIX4_dev->dev,
 207                                 "Host SMBus controller not enabled!\n");
 208                         release_region(piix4_smba, SMBIOSIZE);
 209                         piix4_smba = 0;
 210                         return -ENODEV;
 211                 }
 212         }
 213
 214         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 215                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
 216         else if ((temp & 0x0E) == 0)
 217                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
 218         else
 219                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 220                         "(or code out of date)!\n");
 221
 222         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 223         dev_info(&PIIX4_dev->dev,
 224                  "SMBus Host Controller at 0x%x, revision %d\n",
 225                  piix4_smba, temp);
 226
 227         return 0;
 228 }
 229
 230 static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 231                                 const struct pci_device_id *id)
 232 {
 233         unsigned short smba_idx = 0xcd6;
 234         u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
 235
 236         /* SB800 and later SMBus does not support forcing address */
 237         if (force || force_addr) {
 238                 dev_err(&PIIX4_dev->dev, "SMBus does not support "
 239                         "forcing address!\n");
 240                 return -EINVAL;
 241         }
 242
 243         /* Determine the address of the SMBus areas */
 244         if (!request_region(smba_idx, 2, "smba_idx")) {
 245                 dev_err(&PIIX4_dev->dev, "SMBus base address index region "
 246                         "0x%x already in use!\n", smba_idx);
 247                 return -EBUSY;
 248         }
 249         outb_p(smb_en, smba_idx);
 250         smba_en_lo = inb_p(smba_idx + 1);
 251         outb_p(smb_en + 1, smba_idx);
 252         smba_en_hi = inb_p(smba_idx + 1);
 253         release_region(smba_idx, 2);
 254
 255         if ((smba_en_lo & 1) == 0) {
 256                 dev_err(&PIIX4_dev->dev,
 257                         "Host SMBus controller not enabled!\n");
 258                 return -ENODEV;
 259         }
 260
 261         piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
 262         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 263                 return -ENODEV;
 264
 265         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 266                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 267                         piix4_smba);
 268                 return -EBUSY;
 269         }
 270
 271         /* Request the SMBus I2C bus config region */
 272         if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
 273                 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
 274                         "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
 275                 release_region(piix4_smba, SMBIOSIZE);
 276                 piix4_smba = 0;
 277                 return -EBUSY;
 278         }
 279         i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
 280         release_region(piix4_smba + i2ccfg_offset, 1);
 281
 282         if (i2ccfg & 1)
 283                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
 284         else
 285                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");
 286
 287         dev_info(&PIIX4_dev->dev,
 288                  "SMBus Host Controller at 0x%x, revision %d\n",
 289                  piix4_smba, i2ccfg >> 4);
 290
 291         return 0;
 292 }
 293
 294 static int piix4_transaction(void)
 295 {
 296         int temp;
 297         int result = 0;
 298         int timeout = 0;
 299
 300         dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 301                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 302                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 303                 inb_p(SMBHSTDAT1));
 304
 305         /* Make sure the SMBus host is ready to start transmitting */
 306         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 307                 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
 308                         "Resetting...\n", temp);
 309                 outb_p(temp, SMBHSTSTS);
 310                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 311                         dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
 312                         return -EBUSY;
 313                 } else {
 314                         dev_dbg(&piix4_adapter.dev, "Successful!\n");
 315                 }
 316         }
 317
 318         /* start the transaction by setting bit 6 */
 319         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 320
 321         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 322         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 323                 msleep(2);
 324         else
 325                 msleep(1);
 326
 327         while ((++timeout < MAX_TIMEOUT) &&
 328                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 329                 msleep(1);
 330
 331         /* If the SMBus is still busy, we give up */
 332         if (timeout == MAX_TIMEOUT) {
 333                 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
 334                 result = -ETIMEDOUT;
 335         }
 336
 337         if (temp & 0x10) {
 338                 result = -EIO;
 339                 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
 340         }
 341
 342         if (temp & 0x08) {
 343                 result = -EIO;
 344                 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
 345                         "locked until next hard reset. (sorry!)\n");
 346                 /* Clock stops and slave is stuck in mid-transmission */
 347         }
 348
 349         if (temp & 0x04) {
 350                 result = -ENXIO;
 351                 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
 352         }
 353
 354         if (inb_p(SMBHSTSTS) != 0x00)
 355                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 356
 357         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 358                 dev_err(&piix4_adapter.dev, "Failed reset at end of "
 359                         "transaction (%02x)\n", temp);
 360         }
 361         dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 362                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 363                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 364                 inb_p(SMBHSTDAT1));
 365         return result;
 366 }
 367
 368 /* Return negative errno on error. */
 369 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 370                  unsigned short flags, char read_write,
 371                  u8 command, int size, union i2c_smbus_data * data)
 372 {
 373         int i, len;
 374         int status;
 375
 376         switch (size) {
 377         case I2C_SMBUS_QUICK:
 378                 outb_p((addr << 1) | read_write,
 379                        SMBHSTADD);
 380                 size = PIIX4_QUICK;
 381                 break;
 382         case I2C_SMBUS_BYTE:
 383                 outb_p((addr << 1) | read_write,
 384                        SMBHSTADD);
 385                 if (read_write == I2C_SMBUS_WRITE)
 386                         outb_p(command, SMBHSTCMD);
 387                 size = PIIX4_BYTE;
 388                 break;
 389         case I2C_SMBUS_BYTE_DATA:
 390                 outb_p((addr << 1) | read_write,
 391                        SMBHSTADD);
 392                 outb_p(command, SMBHSTCMD);
 393                 if (read_write == I2C_SMBUS_WRITE)
 394                         outb_p(data->byte, SMBHSTDAT0);
 395                 size = PIIX4_BYTE_DATA;
 396                 break;
 397         case I2C_SMBUS_WORD_DATA:
 398                 outb_p((addr << 1) | read_write,
 399                        SMBHSTADD);
 400                 outb_p(command, SMBHSTCMD);
 401                 if (read_write == I2C_SMBUS_WRITE) {
 402                         outb_p(data->word & 0xff, SMBHSTDAT0);
 403                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 404                 }
 405                 size = PIIX4_WORD_DATA;
 406                 break;
 407         case I2C_SMBUS_BLOCK_DATA:
 408                 outb_p((addr << 1) | read_write,
 409                        SMBHSTADD);
 410                 outb_p(command, SMBHSTCMD);
 411                 if (read_write == I2C_SMBUS_WRITE) {
 412                         len = data->block[0];
 413                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 414                                 return -EINVAL;
 415                         outb_p(len, SMBHSTDAT0);
 416                         i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 417                         for (i = 1; i <= len; i++)
 418                                 outb_p(data->block[i], SMBBLKDAT);
 419                 }
 420                 size = PIIX4_BLOCK_DATA;
 421                 break;
 422         default:
 423                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 424                 return -EOPNOTSUPP;
 425         }
 426
 427         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 428
 429         status = piix4_transaction();
 430         if (status)
 431                 return status;
 432
 433         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 434                 return 0;
 435
 436
 437         switch (size) {
 438         case PIIX4_BYTE:
 439         case PIIX4_BYTE_DATA:
 440                 data->byte = inb_p(SMBHSTDAT0);
 441                 break;
 442         case PIIX4_WORD_DATA:
 443                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 444                 break;
 445         case PIIX4_BLOCK_DATA:
 446                 data->block[0] = inb_p(SMBHSTDAT0);
 447                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 448                         return -EPROTO;
 449                 i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 450                 for (i = 1; i <= data->block[0]; i++)
 451                         data->block[i] = inb_p(SMBBLKDAT);
 452                 break;
 453         }
 454         return 0;
 455 }
 456
 457 static u32 piix4_func(struct i2c_adapter *adapter)
 458 {
 459         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 460             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 461             I2C_FUNC_SMBUS_BLOCK_DATA;
 462 }
 463
 464 static const struct i2c_algorithm smbus_algorithm = {
 465         .smbus_xfer     = piix4_access,
 466         .functionality  = piix4_func,
 467 };
 468
 469 static struct i2c_adapter piix4_adapter = {
 470         .owner          = THIS_MODULE,
 471         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 472         .algo           = &smbus_algorithm,
 473 };
 474
 475 static const struct pci_device_id piix4_ids[] = {
 476         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 477         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 478         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 479         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 480         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 481         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 482         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 483         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
 484         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 485                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 486         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 487                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 488         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 489                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 490         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 491                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 492         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 493                      PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
 494         { 0, }
 495 };
 496
 497 MODULE_DEVICE_TABLE (pci, piix4_ids);
 498
 499 static int __devinit piix4_probe(struct pci_dev *dev,
 500                                 const struct pci_device_id *id)
 501 {
 502         int retval;
 503
 504         if ((dev->vendor == PCI_VENDOR_ID_ATI &&
 505              dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
 506              dev->revision >= 0x40) ||
 507             dev->vendor == PCI_VENDOR_ID_AMD)
 508                 /* base address location etc changed in SB800 */
 509                 retval = piix4_setup_sb800(dev, id);
 510         else
 511                 retval = piix4_setup(dev, id);
 512
 513         if (retval)
 514                 return retval;
 515
 516         /* set up the sysfs linkage to our parent device */
 517         piix4_adapter.dev.parent = &dev->dev;
 518
 519         snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
 520                 "SMBus PIIX4 adapter at %04x", piix4_smba);
 521
 522         if ((retval = i2c_add_adapter(&piix4_adapter))) {
 523                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 524                 release_region(piix4_smba, SMBIOSIZE);
 525                 piix4_smba = 0;
 526         }
 527
 528         return retval;
 529 }
 530
 531 static void __devexit piix4_remove(struct pci_dev *dev)
 532 {
 533         if (piix4_smba) {
 534                 i2c_del_adapter(&piix4_adapter);
 535                 release_region(piix4_smba, SMBIOSIZE);
 536                 piix4_smba = 0;
 537         }
 538 }
 539
 540 static struct pci_driver piix4_driver = {
 541         .name           = "piix4_smbus",
 542         .id_table       = piix4_ids,
 543         .probe          = piix4_probe,
 544         .remove         = __devexit_p(piix4_remove),
 545 };
 546
 547 static int __init i2c_piix4_init(void)
 548 {
 549         return pci_register_driver(&piix4_driver);
 550 }
 551
 552 static void __exit i2c_piix4_exit(void)
 553 {
 554         pci_unregister_driver(&piix4_driver);
 555 }
 556
 557 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
 558                 "Philip Edelbrock <phil@netroedge.com>");
 559 MODULE_DESCRIPTION("PIIX4 SMBus driver");
 560 MODULE_LICENSE("GPL");
 561
 562 module_init(i2c_piix4_init);
 563 module_exit(i2c_piix4_exit);