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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / radeon_encoders.c
blob354ce1025528b9db03e19ddde6bb0c0371523566
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179 void
180 radeon_link_encoder_connector(struct drm_device *dev)
181 {
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
186
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
194 }
195 }
196 }
197
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
199 {
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
203
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
211 }
212 }
213 }
214
215 struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217 {
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
222
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
226 return connector;
227 }
228 return NULL;
229 }
230
231 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode)
233 {
234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
235 struct drm_device *dev = encoder->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
238 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
239 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
240 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
241 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
242 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
243 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
244
245 adjusted_mode->clock = native_mode->clock;
246 adjusted_mode->flags = native_mode->flags;
247
248 if (ASIC_IS_AVIVO(rdev)) {
249 adjusted_mode->hdisplay = native_mode->hdisplay;
250 adjusted_mode->vdisplay = native_mode->vdisplay;
251 }
252
253 adjusted_mode->htotal = native_mode->hdisplay + hblank;
254 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
255 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
256
257 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
258 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
259 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
260
261 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
262
263 if (ASIC_IS_AVIVO(rdev)) {
264 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
265 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
266 }
267
268 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
269 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
270 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
271
272 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
273 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
274 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
275
276 }
277
278 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
281 {
282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
285
286 /* set the active encoder to connector routing */
287 radeon_encoder_set_active_device(encoder);
288 drm_mode_set_crtcinfo(adjusted_mode, 0);
289
290 /* hw bug */
291 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
292 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
293 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
294
295 /* get the native mode for LVDS */
296 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
297 radeon_panel_mode_fixup(encoder, adjusted_mode);
298
299 /* get the native mode for TV */
300 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
301 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
302 if (tv_dac) {
303 if (tv_dac->tv_std == TV_STD_NTSC ||
304 tv_dac->tv_std == TV_STD_NTSC_J ||
305 tv_dac->tv_std == TV_STD_PAL_M)
306 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
307 else
308 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
309 }
310 }
311
312 if (ASIC_IS_DCE3(rdev) &&
313 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
315 radeon_dp_set_link_config(connector, mode);
316 }
317
318 return true;
319 }
320
321 static void
322 atombios_dac_setup(struct drm_encoder *encoder, int action)
323 {
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
328 int index = 0;
329 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
330
331 memset(&args, 0, sizeof(args));
332
333 switch (radeon_encoder->encoder_id) {
334 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
336 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
337 break;
338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
340 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
341 break;
342 }
343
344 args.ucAction = action;
345
346 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_PS2;
348 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
349 args.ucDacStandard = ATOM_DAC1_CV;
350 else {
351 switch (dac_info->tv_std) {
352 case TV_STD_PAL:
353 case TV_STD_PAL_M:
354 case TV_STD_SCART_PAL:
355 case TV_STD_SECAM:
356 case TV_STD_PAL_CN:
357 args.ucDacStandard = ATOM_DAC1_PAL;
358 break;
359 case TV_STD_NTSC:
360 case TV_STD_NTSC_J:
361 case TV_STD_PAL_60:
362 default:
363 args.ucDacStandard = ATOM_DAC1_NTSC;
364 break;
365 }
366 }
367 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
368
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
370
371 }
372
373 static void
374 atombios_tv_setup(struct drm_encoder *encoder, int action)
375 {
376 struct drm_device *dev = encoder->dev;
377 struct radeon_device *rdev = dev->dev_private;
378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
379 TV_ENCODER_CONTROL_PS_ALLOCATION args;
380 int index = 0;
381 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
382
383 memset(&args, 0, sizeof(args));
384
385 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
386
387 args.sTVEncoder.ucAction = action;
388
389 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
390 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
391 else {
392 switch (dac_info->tv_std) {
393 case TV_STD_NTSC:
394 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
395 break;
396 case TV_STD_PAL:
397 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
398 break;
399 case TV_STD_PAL_M:
400 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
401 break;
402 case TV_STD_PAL_60:
403 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
404 break;
405 case TV_STD_NTSC_J:
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
407 break;
408 case TV_STD_SCART_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
410 break;
411 case TV_STD_SECAM:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
413 break;
414 case TV_STD_PAL_CN:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
416 break;
417 default:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
419 break;
420 }
421 }
422
423 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
424
425 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
426
427 }
428
429 void
430 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
431 {
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
436 int index = 0;
437
438 memset(&args, 0, sizeof(args));
439
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
441
442 args.sXTmdsEncoder.ucEnable = action;
443
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
446
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
449
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
451
452 }
453
454 static void
455 atombios_ddia_setup(struct drm_encoder *encoder, int action)
456 {
457 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
461 int index = 0;
462
463 memset(&args, 0, sizeof(args));
464
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
466
467 args.sDVOEncoder.ucAction = action;
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
469
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
472
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
474
475 }
476
477 union lvds_encoder_control {
478 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
479 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
480 };
481
482 void
483 atombios_digital_setup(struct drm_encoder *encoder, int action)
484 {
485 struct drm_device *dev = encoder->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
489 union lvds_encoder_control args;
490 int index = 0;
491 int hdmi_detected = 0;
492 uint8_t frev, crev;
493
494 if (!dig)
495 return;
496
497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
498 hdmi_detected = 1;
499
500 memset(&args, 0, sizeof(args));
501
502 switch (radeon_encoder->encoder_id) {
503 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
504 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
505 break;
506 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
508 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
509 break;
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
512 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
513 else
514 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
515 break;
516 }
517
518 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
519 return;
520
521 switch (frev) {
522 case 1:
523 case 2:
524 switch (crev) {
525 case 1:
526 args.v1.ucMisc = 0;
527 args.v1.ucAction = action;
528 if (hdmi_detected)
529 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
530 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
532 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
535 args.v1.ucMisc |= (1 << 1);
536 } else {
537 if (dig->linkb)
538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1);
543 }
544 break;
545 case 2:
546 case 3:
547 args.v2.ucMisc = 0;
548 args.v2.ucAction = action;
549 if (crev == 3) {
550 if (dig->coherent_mode)
551 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
552 }
553 if (hdmi_detected)
554 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
555 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
556 args.v2.ucTruncate = 0;
557 args.v2.ucSpatial = 0;
558 args.v2.ucTemporal = 0;
559 args.v2.ucFRC = 0;
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
561 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
562 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
563 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
564 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
565 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
566 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
567 }
568 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
569 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
570 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
571 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
572 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
574 }
575 } else {
576 if (dig->linkb)
577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
578 if (radeon_encoder->pixel_clock > 165000)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
580 }
581 break;
582 default:
583 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
584 break;
585 }
586 break;
587 default:
588 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
589 break;
590 }
591
592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
593 }
594
595 int
596 atombios_get_encoder_mode(struct drm_encoder *encoder)
597 {
598 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
599 struct drm_device *dev = encoder->dev;
600 struct radeon_device *rdev = dev->dev_private;
601 struct drm_connector *connector;
602 struct radeon_connector *radeon_connector;
603 struct radeon_connector_atom_dig *dig_connector;
604
605 connector = radeon_get_connector_for_encoder(encoder);
606 if (!connector) {
607 switch (radeon_encoder->encoder_id) {
608 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
610 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
612 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
613 return ATOM_ENCODER_MODE_DVI;
614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
615 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
616 default:
617 return ATOM_ENCODER_MODE_CRT;
618 }
619 }
620 radeon_connector = to_radeon_connector(connector);
621
622 switch (connector->connector_type) {
623 case DRM_MODE_CONNECTOR_DVII:
624 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
625 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
626 /* fix me */
627 if (ASIC_IS_DCE4(rdev))
628 return ATOM_ENCODER_MODE_DVI;
629 else
630 return ATOM_ENCODER_MODE_HDMI;
631 } else if (radeon_connector->use_digital)
632 return ATOM_ENCODER_MODE_DVI;
633 else
634 return ATOM_ENCODER_MODE_CRT;
635 break;
636 case DRM_MODE_CONNECTOR_DVID:
637 case DRM_MODE_CONNECTOR_HDMIA:
638 default:
639 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
640 /* fix me */
641 if (ASIC_IS_DCE4(rdev))
642 return ATOM_ENCODER_MODE_DVI;
643 else
644 return ATOM_ENCODER_MODE_HDMI;
645 } else
646 return ATOM_ENCODER_MODE_DVI;
647 break;
648 case DRM_MODE_CONNECTOR_LVDS:
649 return ATOM_ENCODER_MODE_LVDS;
650 break;
651 case DRM_MODE_CONNECTOR_DisplayPort:
652 case DRM_MODE_CONNECTOR_eDP:
653 dig_connector = radeon_connector->con_priv;
654 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
655 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
656 return ATOM_ENCODER_MODE_DP;
657 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
658 /* fix me */
659 if (ASIC_IS_DCE4(rdev))
660 return ATOM_ENCODER_MODE_DVI;
661 else
662 return ATOM_ENCODER_MODE_HDMI;
663 } else
664 return ATOM_ENCODER_MODE_DVI;
665 break;
666 case DRM_MODE_CONNECTOR_DVIA:
667 case DRM_MODE_CONNECTOR_VGA:
668 return ATOM_ENCODER_MODE_CRT;
669 break;
670 case DRM_MODE_CONNECTOR_Composite:
671 case DRM_MODE_CONNECTOR_SVIDEO:
672 case DRM_MODE_CONNECTOR_9PinDIN:
673 /* fix me */
674 return ATOM_ENCODER_MODE_TV;
675 /*return ATOM_ENCODER_MODE_CV;*/
676 break;
677 }
678 }
679
680 /*
681 * DIG Encoder/Transmitter Setup
682 *
683 * DCE 3.0/3.1
684 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
685 * Supports up to 3 digital outputs
686 * - 2 DIG encoder blocks.
687 * DIG1 can drive UNIPHY link A or link B
688 * DIG2 can drive UNIPHY link B or LVTMA
689 *
690 * DCE 3.2
691 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
692 * Supports up to 5 digital outputs
693 * - 2 DIG encoder blocks.
694 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
695 *
696 * DCE 4.0
697 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
698 * Supports up to 6 digital outputs
699 * - 6 DIG encoder blocks.
700 * - DIG to PHY mapping is hardcoded
701 * DIG1 drives UNIPHY0 link A, A+B
702 * DIG2 drives UNIPHY0 link B
703 * DIG3 drives UNIPHY1 link A, A+B
704 * DIG4 drives UNIPHY1 link B
705 * DIG5 drives UNIPHY2 link A, A+B
706 * DIG6 drives UNIPHY2 link B
707 *
708 * Routing
709 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
710 * Examples:
711 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
712 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
713 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
714 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
715 */
716
717 union dig_encoder_control {
718 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
719 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
720 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
721 };
722
723 void
724 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
725 {
726 struct drm_device *dev = encoder->dev;
727 struct radeon_device *rdev = dev->dev_private;
728 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
729 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
730 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
731 union dig_encoder_control args;
732 int index = 0;
733 uint8_t frev, crev;
734 int dp_clock = 0;
735 int dp_lane_count = 0;
736
737 if (connector) {
738 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
739 struct radeon_connector_atom_dig *dig_connector =
740 radeon_connector->con_priv;
741
742 dp_clock = dig_connector->dp_clock;
743 dp_lane_count = dig_connector->dp_lane_count;
744 }
745
746 /* no dig encoder assigned */
747 if (dig->dig_encoder == -1)
748 return;
749
750 memset(&args, 0, sizeof(args));
751
752 if (ASIC_IS_DCE4(rdev))
753 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
754 else {
755 if (dig->dig_encoder)
756 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
757 else
758 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
759 }
760
761 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
762 return;
763
764 args.v1.ucAction = action;
765 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
766 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
767
768 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
769 if (dp_clock == 270000)
770 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
771 args.v1.ucLaneNum = dp_lane_count;
772 } else if (radeon_encoder->pixel_clock > 165000)
773 args.v1.ucLaneNum = 8;
774 else
775 args.v1.ucLaneNum = 4;
776
777 if (ASIC_IS_DCE4(rdev)) {
778 args.v3.acConfig.ucDigSel = dig->dig_encoder;
779 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
780 } else {
781 switch (radeon_encoder->encoder_id) {
782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
783 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
784 break;
785 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
786 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
787 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
788 break;
789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
790 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
791 break;
792 }
793 if (dig->linkb)
794 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
795 else
796 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
797 }
798
799 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
800
801 }
802
803 union dig_transmitter_control {
804 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
805 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
806 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
807 };
808
809 void
810 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
811 {
812 struct drm_device *dev = encoder->dev;
813 struct radeon_device *rdev = dev->dev_private;
814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
815 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
816 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
817 union dig_transmitter_control args;
818 int index = 0;
819 uint8_t frev, crev;
820 bool is_dp = false;
821 int pll_id = 0;
822 int dp_clock = 0;
823 int dp_lane_count = 0;
824 int connector_object_id = 0;
825 int igp_lane_info = 0;
826
827 if (connector) {
828 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
829 struct radeon_connector_atom_dig *dig_connector =
830 radeon_connector->con_priv;
831
832 dp_clock = dig_connector->dp_clock;
833 dp_lane_count = dig_connector->dp_lane_count;
834 connector_object_id =
835 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
836 igp_lane_info = dig_connector->igp_lane_info;
837 }
838
839 /* no dig encoder assigned */
840 if (dig->dig_encoder == -1)
841 return;
842
843 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
844 is_dp = true;
845
846 memset(&args, 0, sizeof(args));
847
848 switch (radeon_encoder->encoder_id) {
849 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
850 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
852 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
853 break;
854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
855 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
856 break;
857 }
858
859 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
860 return;
861
862 args.v1.ucAction = action;
863 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
864 args.v1.usInitInfo = connector_object_id;
865 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
866 args.v1.asMode.ucLaneSel = lane_num;
867 args.v1.asMode.ucLaneSet = lane_set;
868 } else {
869 if (is_dp)
870 args.v1.usPixelClock =
871 cpu_to_le16(dp_clock / 10);
872 else if (radeon_encoder->pixel_clock > 165000)
873 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
874 else
875 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
876 }
877 if (ASIC_IS_DCE4(rdev)) {
878 if (is_dp)
879 args.v3.ucLaneNum = dp_lane_count;
880 else if (radeon_encoder->pixel_clock > 165000)
881 args.v3.ucLaneNum = 8;
882 else
883 args.v3.ucLaneNum = 4;
884
885 if (dig->linkb) {
886 args.v3.acConfig.ucLinkSel = 1;
887 args.v3.acConfig.ucEncoderSel = 1;
888 }
889
890 /* Select the PLL for the PHY
891 * DP PHY should be clocked from external src if there is
892 * one.
893 */
894 if (encoder->crtc) {
895 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
896 pll_id = radeon_crtc->pll_id;
897 }
898 if (is_dp && rdev->clock.dp_extclk)
899 args.v3.acConfig.ucRefClkSource = 2; /* external src */
900 else
901 args.v3.acConfig.ucRefClkSource = pll_id;
902
903 switch (radeon_encoder->encoder_id) {
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
905 args.v3.acConfig.ucTransmitterSel = 0;
906 break;
907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
908 args.v3.acConfig.ucTransmitterSel = 1;
909 break;
910 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
911 args.v3.acConfig.ucTransmitterSel = 2;
912 break;
913 }
914
915 if (is_dp)
916 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
917 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
918 if (dig->coherent_mode)
919 args.v3.acConfig.fCoherentMode = 1;
920 if (radeon_encoder->pixel_clock > 165000)
921 args.v3.acConfig.fDualLinkConnector = 1;
922 }
923 } else if (ASIC_IS_DCE32(rdev)) {
924 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
925 if (dig->linkb)
926 args.v2.acConfig.ucLinkSel = 1;
927
928 switch (radeon_encoder->encoder_id) {
929 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
930 args.v2.acConfig.ucTransmitterSel = 0;
931 break;
932 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
933 args.v2.acConfig.ucTransmitterSel = 1;
934 break;
935 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
936 args.v2.acConfig.ucTransmitterSel = 2;
937 break;
938 }
939
940 if (is_dp)
941 args.v2.acConfig.fCoherentMode = 1;
942 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
943 if (dig->coherent_mode)
944 args.v2.acConfig.fCoherentMode = 1;
945 if (radeon_encoder->pixel_clock > 165000)
946 args.v2.acConfig.fDualLinkConnector = 1;
947 }
948 } else {
949 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
950
951 if (dig->dig_encoder)
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
953 else
954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
955
956 if ((rdev->flags & RADEON_IS_IGP) &&
957 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
958 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
959 if (igp_lane_info & 0x1)
960 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
961 else if (igp_lane_info & 0x2)
962 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
963 else if (igp_lane_info & 0x4)
964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
965 else if (igp_lane_info & 0x8)
966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
967 } else {
968 if (igp_lane_info & 0x3)
969 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
970 else if (igp_lane_info & 0xc)
971 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
972 }
973 }
974
975 if (dig->linkb)
976 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
977 else
978 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
979
980 if (is_dp)
981 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
982 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
983 if (dig->coherent_mode)
984 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
985 if (radeon_encoder->pixel_clock > 165000)
986 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
987 }
988 }
989
990 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
991 }
992
993 static void
994 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
995 {
996 struct drm_device *dev = encoder->dev;
997 struct radeon_device *rdev = dev->dev_private;
998 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
999 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1000 ENABLE_YUV_PS_ALLOCATION args;
1001 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1002 uint32_t temp, reg;
1003
1004 memset(&args, 0, sizeof(args));
1005
1006 if (rdev->family >= CHIP_R600)
1007 reg = R600_BIOS_3_SCRATCH;
1008 else
1009 reg = RADEON_BIOS_3_SCRATCH;
1010
1011 temp = RREG32(reg);
1012 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1013 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1014 (radeon_crtc->crtc_id << 18)));
1015 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1016 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1017 else
1018 WREG32(reg, 0);
1019
1020 if (enable)
1021 args.ucEnable = ATOM_ENABLE;
1022 args.ucCRTC = radeon_crtc->crtc_id;
1023
1024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1025
1026 WREG32(reg, temp);
1027 }
1028
1029 static void
1030 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1031 {
1032 struct drm_device *dev = encoder->dev;
1033 struct radeon_device *rdev = dev->dev_private;
1034 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1035 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1036 int index = 0;
1037 bool is_dig = false;
1038
1039 memset(&args, 0, sizeof(args));
1040
1041 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1042 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1043 radeon_encoder->active_device);
1044 switch (radeon_encoder->encoder_id) {
1045 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1047 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1048 break;
1049 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1051 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1052 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1053 is_dig = true;
1054 break;
1055 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1056 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1057 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1058 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1059 break;
1060 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1061 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1062 break;
1063 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1064 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1065 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1066 else
1067 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1068 break;
1069 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1070 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1071 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1072 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1073 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1074 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1075 else
1076 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1077 break;
1078 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1079 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1080 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1081 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1082 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1083 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1084 else
1085 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1086 break;
1087 }
1088
1089 if (is_dig) {
1090 switch (mode) {
1091 case DRM_MODE_DPMS_ON:
1092 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1093 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1094 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1095
1096 dp_link_train(encoder, connector);
1097 if (ASIC_IS_DCE4(rdev))
1098 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1099 }
1100 break;
1101 case DRM_MODE_DPMS_STANDBY:
1102 case DRM_MODE_DPMS_SUSPEND:
1103 case DRM_MODE_DPMS_OFF:
1104 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1105 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1106 if (ASIC_IS_DCE4(rdev))
1107 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1108 }
1109 break;
1110 }
1111 } else {
1112 switch (mode) {
1113 case DRM_MODE_DPMS_ON:
1114 args.ucAction = ATOM_ENABLE;
1115 break;
1116 case DRM_MODE_DPMS_STANDBY:
1117 case DRM_MODE_DPMS_SUSPEND:
1118 case DRM_MODE_DPMS_OFF:
1119 args.ucAction = ATOM_DISABLE;
1120 break;
1121 }
1122 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1123 }
1124 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1125
1126 }
1127
1128 union crtc_source_param {
1129 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1130 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1131 };
1132
1133 static void
1134 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1135 {
1136 struct drm_device *dev = encoder->dev;
1137 struct radeon_device *rdev = dev->dev_private;
1138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1139 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1140 union crtc_source_param args;
1141 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1142 uint8_t frev, crev;
1143 struct radeon_encoder_atom_dig *dig;
1144
1145 memset(&args, 0, sizeof(args));
1146
1147 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1148 return;
1149
1150 switch (frev) {
1151 case 1:
1152 switch (crev) {
1153 case 1:
1154 default:
1155 if (ASIC_IS_AVIVO(rdev))
1156 args.v1.ucCRTC = radeon_crtc->crtc_id;
1157 else {
1158 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1159 args.v1.ucCRTC = radeon_crtc->crtc_id;
1160 } else {
1161 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1162 }
1163 }
1164 switch (radeon_encoder->encoder_id) {
1165 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1167 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1168 break;
1169 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1170 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1171 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1172 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1173 else
1174 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1175 break;
1176 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1177 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1178 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1179 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1180 break;
1181 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1183 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1184 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1185 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1186 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1187 else
1188 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1189 break;
1190 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1191 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1192 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1193 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1194 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1195 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1196 else
1197 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1198 break;
1199 }
1200 break;
1201 case 2:
1202 args.v2.ucCRTC = radeon_crtc->crtc_id;
1203 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1204 switch (radeon_encoder->encoder_id) {
1205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1208 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1209 dig = radeon_encoder->enc_priv;
1210 switch (dig->dig_encoder) {
1211 case 0:
1212 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1213 break;
1214 case 1:
1215 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1216 break;
1217 case 2:
1218 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1219 break;
1220 case 3:
1221 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1222 break;
1223 case 4:
1224 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1225 break;
1226 case 5:
1227 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1228 break;
1229 }
1230 break;
1231 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1232 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1233 break;
1234 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1235 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1236 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1237 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1238 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1239 else
1240 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1241 break;
1242 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1243 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1244 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1245 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1246 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1247 else
1248 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1249 break;
1250 }
1251 break;
1252 }
1253 break;
1254 default:
1255 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1256 break;
1257 }
1258
1259 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1260
1261 /* update scratch regs with new routing */
1262 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1263 }
1264
1265 static void
1266 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1267 struct drm_display_mode *mode)
1268 {
1269 struct drm_device *dev = encoder->dev;
1270 struct radeon_device *rdev = dev->dev_private;
1271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1273
1274 /* Funky macbooks */
1275 if ((dev->pdev->device == 0x71C5) &&
1276 (dev->pdev->subsystem_vendor == 0x106b) &&
1277 (dev->pdev->subsystem_device == 0x0080)) {
1278 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1279 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1280
1281 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1282 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1283
1284 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1285 }
1286 }
1287
1288 /* set scaler clears this on some chips */
1289 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1290 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1291 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1292 AVIVO_D1MODE_INTERLEAVE_EN);
1293 }
1294 }
1295
1296 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1297 {
1298 struct drm_device *dev = encoder->dev;
1299 struct radeon_device *rdev = dev->dev_private;
1300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1302 struct drm_encoder *test_encoder;
1303 struct radeon_encoder_atom_dig *dig;
1304 uint32_t dig_enc_in_use = 0;
1305
1306 if (ASIC_IS_DCE4(rdev)) {
1307 dig = radeon_encoder->enc_priv;
1308 switch (radeon_encoder->encoder_id) {
1309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1310 if (dig->linkb)
1311 return 1;
1312 else
1313 return 0;
1314 break;
1315 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1316 if (dig->linkb)
1317 return 3;
1318 else
1319 return 2;
1320 break;
1321 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1322 if (dig->linkb)
1323 return 5;
1324 else
1325 return 4;
1326 break;
1327 }
1328 }
1329
1330 /* on DCE32 and encoder can driver any block so just crtc id */
1331 if (ASIC_IS_DCE32(rdev)) {
1332 return radeon_crtc->crtc_id;
1333 }
1334
1335 /* on DCE3 - LVTMA can only be driven by DIGB */
1336 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1337 struct radeon_encoder *radeon_test_encoder;
1338
1339 if (encoder == test_encoder)
1340 continue;
1341
1342 if (!radeon_encoder_is_digital(test_encoder))
1343 continue;
1344
1345 radeon_test_encoder = to_radeon_encoder(test_encoder);
1346 dig = radeon_test_encoder->enc_priv;
1347
1348 if (dig->dig_encoder >= 0)
1349 dig_enc_in_use |= (1 << dig->dig_encoder);
1350 }
1351
1352 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1353 if (dig_enc_in_use & 0x2)
1354 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1355 return 1;
1356 }
1357 if (!(dig_enc_in_use & 1))
1358 return 0;
1359 return 1;
1360 }
1361
1362 static void
1363 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1364 struct drm_display_mode *mode,
1365 struct drm_display_mode *adjusted_mode)
1366 {
1367 struct drm_device *dev = encoder->dev;
1368 struct radeon_device *rdev = dev->dev_private;
1369 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1370
1371 radeon_encoder->pixel_clock = adjusted_mode->clock;
1372
1373 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1374 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1375 atombios_yuv_setup(encoder, true);
1376 else
1377 atombios_yuv_setup(encoder, false);
1378 }
1379
1380 switch (radeon_encoder->encoder_id) {
1381 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1382 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1383 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1384 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1385 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1388 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1389 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1391 if (ASIC_IS_DCE4(rdev)) {
1392 /* disable the transmitter */
1393 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1394 /* setup and enable the encoder */
1395 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1396
1397 /* init and enable the transmitter */
1398 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1399 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1400 } else {
1401 /* disable the encoder and transmitter */
1402 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1403 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1404
1405 /* setup and enable the encoder and transmitter */
1406 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1407 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1408 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1409 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1410 }
1411 break;
1412 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1413 atombios_ddia_setup(encoder, ATOM_ENABLE);
1414 break;
1415 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1416 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1417 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1418 break;
1419 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1421 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1423 atombios_dac_setup(encoder, ATOM_ENABLE);
1424 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1425 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1426 atombios_tv_setup(encoder, ATOM_ENABLE);
1427 else
1428 atombios_tv_setup(encoder, ATOM_DISABLE);
1429 }
1430 break;
1431 }
1432 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1433
1434 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1435 r600_hdmi_enable(encoder);
1436 r600_hdmi_setmode(encoder, adjusted_mode);
1437 }
1438 }
1439
1440 static bool
1441 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1442 {
1443 struct drm_device *dev = encoder->dev;
1444 struct radeon_device *rdev = dev->dev_private;
1445 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1446 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1447
1448 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1449 ATOM_DEVICE_CV_SUPPORT |
1450 ATOM_DEVICE_CRT_SUPPORT)) {
1451 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1452 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1453 uint8_t frev, crev;
1454
1455 memset(&args, 0, sizeof(args));
1456
1457 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1458 return false;
1459
1460 args.sDacload.ucMisc = 0;
1461
1462 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1463 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1464 args.sDacload.ucDacType = ATOM_DAC_A;
1465 else
1466 args.sDacload.ucDacType = ATOM_DAC_B;
1467
1468 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1469 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1470 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1471 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1472 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1473 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1474 if (crev >= 3)
1475 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1476 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1477 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1478 if (crev >= 3)
1479 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1480 }
1481
1482 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1483
1484 return true;
1485 } else
1486 return false;
1487 }
1488
1489 static enum drm_connector_status
1490 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1491 {
1492 struct drm_device *dev = encoder->dev;
1493 struct radeon_device *rdev = dev->dev_private;
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1496 uint32_t bios_0_scratch;
1497
1498 if (!atombios_dac_load_detect(encoder, connector)) {
1499 DRM_DEBUG_KMS("detect returned false \n");
1500 return connector_status_unknown;
1501 }
1502
1503 if (rdev->family >= CHIP_R600)
1504 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1505 else
1506 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1507
1508 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1509 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1510 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1511 return connector_status_connected;
1512 }
1513 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1514 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1515 return connector_status_connected;
1516 }
1517 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1518 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1519 return connector_status_connected;
1520 }
1521 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1522 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1523 return connector_status_connected; /* CTV */
1524 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1525 return connector_status_connected; /* STV */
1526 }
1527 return connector_status_disconnected;
1528 }
1529
1530 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1531 {
1532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1533
1534 if (radeon_encoder->active_device &
1535 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1536 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1537 if (dig)
1538 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1539 }
1540
1541 radeon_atom_output_lock(encoder, true);
1542 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1543
1544 /* this is needed for the pll/ss setup to work correctly in some cases */
1545 atombios_set_encoder_crtc_source(encoder);
1546 }
1547
1548 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1549 {
1550 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1551 radeon_atom_output_lock(encoder, false);
1552 }
1553
1554 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1555 {
1556 struct drm_device *dev = encoder->dev;
1557 struct radeon_device *rdev = dev->dev_private;
1558 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1559 struct radeon_encoder_atom_dig *dig;
1560
1561 /* check for pre-DCE3 cards with shared encoders;
1562 * can't really use the links individually, so don't disable
1563 * the encoder if it's in use by another connector
1564 */
1565 if (!ASIC_IS_DCE3(rdev)) {
1566 struct drm_encoder *other_encoder;
1567 struct radeon_encoder *other_radeon_encoder;
1568
1569 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1570 other_radeon_encoder = to_radeon_encoder(other_encoder);
1571 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1572 drm_helper_encoder_in_use(other_encoder))
1573 goto disable_done;
1574 }
1575 }
1576
1577 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1578
1579 switch (radeon_encoder->encoder_id) {
1580 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1582 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1583 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1584 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1585 break;
1586 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1587 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1588 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1590 if (ASIC_IS_DCE4(rdev))
1591 /* disable the transmitter */
1592 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1593 else {
1594 /* disable the encoder and transmitter */
1595 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1596 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1597 }
1598 break;
1599 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1600 atombios_ddia_setup(encoder, ATOM_DISABLE);
1601 break;
1602 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1604 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1605 break;
1606 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1607 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1608 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1610 atombios_dac_setup(encoder, ATOM_DISABLE);
1611 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1612 atombios_tv_setup(encoder, ATOM_DISABLE);
1613 break;
1614 }
1615
1616 disable_done:
1617 if (radeon_encoder_is_digital(encoder)) {
1618 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1619 r600_hdmi_disable(encoder);
1620 dig = radeon_encoder->enc_priv;
1621 dig->dig_encoder = -1;
1622 }
1623 radeon_encoder->active_device = 0;
1624 }
1625
1626 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1627 .dpms = radeon_atom_encoder_dpms,
1628 .mode_fixup = radeon_atom_mode_fixup,
1629 .prepare = radeon_atom_encoder_prepare,
1630 .mode_set = radeon_atom_encoder_mode_set,
1631 .commit = radeon_atom_encoder_commit,
1632 .disable = radeon_atom_encoder_disable,
1633 /* no detect for TMDS/LVDS yet */
1634 };
1635
1636 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1637 .dpms = radeon_atom_encoder_dpms,
1638 .mode_fixup = radeon_atom_mode_fixup,
1639 .prepare = radeon_atom_encoder_prepare,
1640 .mode_set = radeon_atom_encoder_mode_set,
1641 .commit = radeon_atom_encoder_commit,
1642 .detect = radeon_atom_dac_detect,
1643 };
1644
1645 void radeon_enc_destroy(struct drm_encoder *encoder)
1646 {
1647 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1648 kfree(radeon_encoder->enc_priv);
1649 drm_encoder_cleanup(encoder);
1650 kfree(radeon_encoder);
1651 }
1652
1653 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1654 .destroy = radeon_enc_destroy,
1655 };
1656
1657 struct radeon_encoder_atom_dac *
1658 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1659 {
1660 struct drm_device *dev = radeon_encoder->base.dev;
1661 struct radeon_device *rdev = dev->dev_private;
1662 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1663
1664 if (!dac)
1665 return NULL;
1666
1667 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1668 return dac;
1669 }
1670
1671 struct radeon_encoder_atom_dig *
1672 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1673 {
1674 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1675 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1676
1677 if (!dig)
1678 return NULL;
1679
1680 /* coherent mode by default */
1681 dig->coherent_mode = true;
1682 dig->dig_encoder = -1;
1683
1684 if (encoder_enum == 2)
1685 dig->linkb = true;
1686 else
1687 dig->linkb = false;
1688
1689 return dig;
1690 }
1691
1692 void
1693 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1694 {
1695 struct radeon_device *rdev = dev->dev_private;
1696 struct drm_encoder *encoder;
1697 struct radeon_encoder *radeon_encoder;
1698
1699 /* see if we already added it */
1700 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1701 radeon_encoder = to_radeon_encoder(encoder);
1702 if (radeon_encoder->encoder_enum == encoder_enum) {
1703 radeon_encoder->devices |= supported_device;
1704 return;
1705 }
1706
1707 }
1708
1709 /* add a new one */
1710 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1711 if (!radeon_encoder)
1712 return;
1713
1714 encoder = &radeon_encoder->base;
1715 switch (rdev->num_crtc) {
1716 case 1:
1717 encoder->possible_crtcs = 0x1;
1718 break;
1719 case 2:
1720 default:
1721 encoder->possible_crtcs = 0x3;
1722 break;
1723 case 6:
1724 encoder->possible_crtcs = 0x3f;
1725 break;
1726 }
1727
1728 radeon_encoder->enc_priv = NULL;
1729
1730 radeon_encoder->encoder_enum = encoder_enum;
1731 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1732 radeon_encoder->devices = supported_device;
1733 radeon_encoder->rmx_type = RMX_OFF;
1734 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1735
1736 switch (radeon_encoder->encoder_id) {
1737 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1738 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1739 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1740 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1741 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1742 radeon_encoder->rmx_type = RMX_FULL;
1743 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1744 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1745 } else {
1746 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1747 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1748 if (ASIC_IS_AVIVO(rdev))
1749 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1750 }
1751 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1752 break;
1753 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1754 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1755 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1756 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1757 break;
1758 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1761 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1762 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1763 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1764 break;
1765 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1767 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1769 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1770 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1771 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1772 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1773 radeon_encoder->rmx_type = RMX_FULL;
1774 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1775 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1776 } else {
1777 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1778 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1779 if (ASIC_IS_AVIVO(rdev))
1780 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1781 }
1782 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1783 break;
1784 }
1785 }
Tomato firmware and modifications.