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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / radeon_display.c
blob4fdc8158487220696b552462cb712ff6c35c2985
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99 }
100
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102 {
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123 }
124
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
126 {
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139 }
140
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144 {
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150 }
151
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155 {
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161 }
162
163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t start, uint32_t size)
165 {
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 /* userspace palettes are always correct as is */
170 for (i = start; i < end; i++) {
171 radeon_crtc->lut_r[i] = red[i] >> 6;
172 radeon_crtc->lut_g[i] = green[i] >> 6;
173 radeon_crtc->lut_b[i] = blue[i] >> 6;
174 }
175 radeon_crtc_load_lut(crtc);
176 }
177
178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
179 {
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
181
182 drm_crtc_cleanup(crtc);
183 kfree(radeon_crtc);
184 }
185
186 static const struct drm_crtc_funcs radeon_crtc_funcs = {
187 .cursor_set = radeon_crtc_cursor_set,
188 .cursor_move = radeon_crtc_cursor_move,
189 .gamma_set = radeon_crtc_gamma_set,
190 .set_config = drm_crtc_helper_set_config,
191 .destroy = radeon_crtc_destroy,
192 };
193
194 static void radeon_crtc_init(struct drm_device *dev, int index)
195 {
196 struct radeon_device *rdev = dev->dev_private;
197 struct radeon_crtc *radeon_crtc;
198 int i;
199
200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
201 if (radeon_crtc == NULL)
202 return;
203
204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
205
206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
207 radeon_crtc->crtc_id = index;
208 rdev->mode_info.crtcs[index] = radeon_crtc;
209
210
211 for (i = 0; i < 256; i++) {
212 radeon_crtc->lut_r[i] = i << 2;
213 radeon_crtc->lut_g[i] = i << 2;
214 radeon_crtc->lut_b[i] = i << 2;
215 }
216
217 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
218 radeon_atombios_init_crtc(dev, radeon_crtc);
219 else
220 radeon_legacy_init_crtc(dev, radeon_crtc);
221 }
222
223 static const char *encoder_names[34] = {
224 "NONE",
225 "INTERNAL_LVDS",
226 "INTERNAL_TMDS1",
227 "INTERNAL_TMDS2",
228 "INTERNAL_DAC1",
229 "INTERNAL_DAC2",
230 "INTERNAL_SDVOA",
231 "INTERNAL_SDVOB",
232 "SI170B",
233 "CH7303",
234 "CH7301",
235 "INTERNAL_DVO1",
236 "EXTERNAL_SDVOA",
237 "EXTERNAL_SDVOB",
238 "TITFP513",
239 "INTERNAL_LVTM1",
240 "VT1623",
241 "HDMI_SI1930",
242 "HDMI_INTERNAL",
243 "INTERNAL_KLDSCP_TMDS1",
244 "INTERNAL_KLDSCP_DVO1",
245 "INTERNAL_KLDSCP_DAC1",
246 "INTERNAL_KLDSCP_DAC2",
247 "SI178",
248 "MVPU_FPGA",
249 "INTERNAL_DDI",
250 "VT1625",
251 "HDMI_SI1932",
252 "DP_AN9801",
253 "DP_DP501",
254 "INTERNAL_UNIPHY",
255 "INTERNAL_KLDSCP_LVTMA",
256 "INTERNAL_UNIPHY1",
257 "INTERNAL_UNIPHY2",
258 };
259
260 static const char *connector_names[15] = {
261 "Unknown",
262 "VGA",
263 "DVI-I",
264 "DVI-D",
265 "DVI-A",
266 "Composite",
267 "S-video",
268 "LVDS",
269 "Component",
270 "DIN",
271 "DisplayPort",
272 "HDMI-A",
273 "HDMI-B",
274 "TV",
275 "eDP",
276 };
277
278 static const char *hpd_names[6] = {
279 "HPD1",
280 "HPD2",
281 "HPD3",
282 "HPD4",
283 "HPD5",
284 "HPD6",
285 };
286
287 static void radeon_print_display_setup(struct drm_device *dev)
288 {
289 struct drm_connector *connector;
290 struct radeon_connector *radeon_connector;
291 struct drm_encoder *encoder;
292 struct radeon_encoder *radeon_encoder;
293 uint32_t devices;
294 int i = 0;
295
296 DRM_INFO("Radeon Display Connectors\n");
297 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
298 radeon_connector = to_radeon_connector(connector);
299 DRM_INFO("Connector %d:\n", i);
300 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
301 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
302 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
303 if (radeon_connector->ddc_bus) {
304 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
305 radeon_connector->ddc_bus->rec.mask_clk_reg,
306 radeon_connector->ddc_bus->rec.mask_data_reg,
307 radeon_connector->ddc_bus->rec.a_clk_reg,
308 radeon_connector->ddc_bus->rec.a_data_reg,
309 radeon_connector->ddc_bus->rec.en_clk_reg,
310 radeon_connector->ddc_bus->rec.en_data_reg,
311 radeon_connector->ddc_bus->rec.y_clk_reg,
312 radeon_connector->ddc_bus->rec.y_data_reg);
313 if (radeon_connector->router_bus)
314 DRM_INFO(" DDC Router 0x%x/0x%x\n",
315 radeon_connector->router.mux_control_pin,
316 radeon_connector->router.mux_state);
317 } else {
318 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
319 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
320 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
321 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
322 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
323 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
324 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
325 }
326 DRM_INFO(" Encoders:\n");
327 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
328 radeon_encoder = to_radeon_encoder(encoder);
329 devices = radeon_encoder->devices & radeon_connector->devices;
330 if (devices) {
331 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
332 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
333 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
334 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
335 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
336 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
337 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
338 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
339 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
340 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
341 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
342 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
343 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
344 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
345 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
346 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
347 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
348 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
349 if (devices & ATOM_DEVICE_TV1_SUPPORT)
350 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
351 if (devices & ATOM_DEVICE_CV_SUPPORT)
352 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
353 }
354 }
355 i++;
356 }
357 }
358
359 static bool radeon_setup_enc_conn(struct drm_device *dev)
360 {
361 struct radeon_device *rdev = dev->dev_private;
362 struct drm_connector *drm_connector;
363 bool ret = false;
364
365 if (rdev->bios) {
366 if (rdev->is_atom_bios) {
367 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
368 if (ret == false)
369 ret = radeon_get_atom_connector_info_from_object_table(dev);
370 } else {
371 ret = radeon_get_legacy_connector_info_from_bios(dev);
372 if (ret == false)
373 ret = radeon_get_legacy_connector_info_from_table(dev);
374 }
375 } else {
376 if (!ASIC_IS_AVIVO(rdev))
377 ret = radeon_get_legacy_connector_info_from_table(dev);
378 }
379 if (ret) {
380 radeon_setup_encoder_clones(dev);
381 radeon_print_display_setup(dev);
382 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
383 radeon_ddc_dump(drm_connector);
384 }
385
386 return ret;
387 }
388
389 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
390 {
391 struct drm_device *dev = radeon_connector->base.dev;
392 struct radeon_device *rdev = dev->dev_private;
393 int ret = 0;
394
395 /* on hw with routers, select right port */
396 if (radeon_connector->router.valid)
397 radeon_router_select_port(radeon_connector);
398
399 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
400 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
401 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
402 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
403 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
404 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
405 }
406 if (!radeon_connector->ddc_bus)
407 return -1;
408 if (!radeon_connector->edid) {
409 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
410 }
411 /* some servers provide a hardcoded edid in rom for KVMs */
412 if (!radeon_connector->edid)
413 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
414 if (radeon_connector->edid) {
415 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
416 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
417 return ret;
418 }
419 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
420 return 0;
421 }
422
423 static int radeon_ddc_dump(struct drm_connector *connector)
424 {
425 struct edid *edid;
426 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427 int ret = 0;
428
429 /* on hw with routers, select right port */
430 if (radeon_connector->router.valid)
431 radeon_router_select_port(radeon_connector);
432
433 if (!radeon_connector->ddc_bus)
434 return -1;
435 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
436 if (edid) {
437 kfree(edid);
438 }
439 return ret;
440 }
441
442 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
443 {
444 uint64_t mod;
445
446 n += d / 2;
447
448 mod = do_div(n, d);
449 return n;
450 }
451
452 static void radeon_compute_pll_legacy(struct radeon_pll *pll,
453 uint64_t freq,
454 uint32_t *dot_clock_p,
455 uint32_t *fb_div_p,
456 uint32_t *frac_fb_div_p,
457 uint32_t *ref_div_p,
458 uint32_t *post_div_p)
459 {
460 uint32_t min_ref_div = pll->min_ref_div;
461 uint32_t max_ref_div = pll->max_ref_div;
462 uint32_t min_post_div = pll->min_post_div;
463 uint32_t max_post_div = pll->max_post_div;
464 uint32_t min_fractional_feed_div = 0;
465 uint32_t max_fractional_feed_div = 0;
466 uint32_t best_vco = pll->best_vco;
467 uint32_t best_post_div = 1;
468 uint32_t best_ref_div = 1;
469 uint32_t best_feedback_div = 1;
470 uint32_t best_frac_feedback_div = 0;
471 uint32_t best_freq = -1;
472 uint32_t best_error = 0xffffffff;
473 uint32_t best_vco_diff = 1;
474 uint32_t post_div;
475 u32 pll_out_min, pll_out_max;
476
477 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
478 freq = freq * 1000;
479
480 if (pll->flags & RADEON_PLL_IS_LCD) {
481 pll_out_min = pll->lcd_pll_out_min;
482 pll_out_max = pll->lcd_pll_out_max;
483 } else {
484 pll_out_min = pll->pll_out_min;
485 pll_out_max = pll->pll_out_max;
486 }
487
488 if (pll->flags & RADEON_PLL_USE_REF_DIV)
489 min_ref_div = max_ref_div = pll->reference_div;
490 else {
491 while (min_ref_div < max_ref_div-1) {
492 uint32_t mid = (min_ref_div + max_ref_div) / 2;
493 uint32_t pll_in = pll->reference_freq / mid;
494 if (pll_in < pll->pll_in_min)
495 max_ref_div = mid;
496 else if (pll_in > pll->pll_in_max)
497 min_ref_div = mid;
498 else
499 break;
500 }
501 }
502
503 if (pll->flags & RADEON_PLL_USE_POST_DIV)
504 min_post_div = max_post_div = pll->post_div;
505
506 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
507 min_fractional_feed_div = pll->min_frac_feedback_div;
508 max_fractional_feed_div = pll->max_frac_feedback_div;
509 }
510
511 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
512 uint32_t ref_div;
513
514 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
515 continue;
516
517 /* legacy radeons only have a few post_divs */
518 if (pll->flags & RADEON_PLL_LEGACY) {
519 if ((post_div == 5) ||
520 (post_div == 7) ||
521 (post_div == 9) ||
522 (post_div == 10) ||
523 (post_div == 11) ||
524 (post_div == 13) ||
525 (post_div == 14) ||
526 (post_div == 15))
527 continue;
528 }
529
530 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
531 uint32_t feedback_div, current_freq = 0, error, vco_diff;
532 uint32_t pll_in = pll->reference_freq / ref_div;
533 uint32_t min_feed_div = pll->min_feedback_div;
534 uint32_t max_feed_div = pll->max_feedback_div + 1;
535
536 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
537 continue;
538
539 while (min_feed_div < max_feed_div) {
540 uint32_t vco;
541 uint32_t min_frac_feed_div = min_fractional_feed_div;
542 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
543 uint32_t frac_feedback_div;
544 uint64_t tmp;
545
546 feedback_div = (min_feed_div + max_feed_div) / 2;
547
548 tmp = (uint64_t)pll->reference_freq * feedback_div;
549 vco = radeon_div(tmp, ref_div);
550
551 if (vco < pll_out_min) {
552 min_feed_div = feedback_div + 1;
553 continue;
554 } else if (vco > pll_out_max) {
555 max_feed_div = feedback_div;
556 continue;
557 }
558
559 while (min_frac_feed_div < max_frac_feed_div) {
560 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
561 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
562 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
563 current_freq = radeon_div(tmp, ref_div * post_div);
564
565 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
566 if (freq < current_freq)
567 error = 0xffffffff;
568 else
569 error = freq - current_freq;
570 } else
571 error = abs(current_freq - freq);
572 vco_diff = abs(vco - best_vco);
573
574 if ((best_vco == 0 && error < best_error) ||
575 (best_vco != 0 &&
576 ((best_error > 100 && error < best_error - 100) ||
577 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
578 best_post_div = post_div;
579 best_ref_div = ref_div;
580 best_feedback_div = feedback_div;
581 best_frac_feedback_div = frac_feedback_div;
582 best_freq = current_freq;
583 best_error = error;
584 best_vco_diff = vco_diff;
585 } else if (current_freq == freq) {
586 if (best_freq == -1) {
587 best_post_div = post_div;
588 best_ref_div = ref_div;
589 best_feedback_div = feedback_div;
590 best_frac_feedback_div = frac_feedback_div;
591 best_freq = current_freq;
592 best_error = error;
593 best_vco_diff = vco_diff;
594 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
595 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
596 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
597 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
598 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
599 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
600 best_post_div = post_div;
601 best_ref_div = ref_div;
602 best_feedback_div = feedback_div;
603 best_frac_feedback_div = frac_feedback_div;
604 best_freq = current_freq;
605 best_error = error;
606 best_vco_diff = vco_diff;
607 }
608 }
609 if (current_freq < freq)
610 min_frac_feed_div = frac_feedback_div + 1;
611 else
612 max_frac_feed_div = frac_feedback_div;
613 }
614 if (current_freq < freq)
615 min_feed_div = feedback_div + 1;
616 else
617 max_feed_div = feedback_div;
618 }
619 }
620 }
621
622 *dot_clock_p = best_freq / 10000;
623 *fb_div_p = best_feedback_div;
624 *frac_fb_div_p = best_frac_feedback_div;
625 *ref_div_p = best_ref_div;
626 *post_div_p = best_post_div;
627 DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
628 freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
629 best_ref_div, best_post_div);
630
631 }
632
633 static bool
634 calc_fb_div(struct radeon_pll *pll,
635 uint32_t freq,
636 uint32_t post_div,
637 uint32_t ref_div,
638 uint32_t *fb_div,
639 uint32_t *fb_div_frac)
640 {
641 fixed20_12 feedback_divider, a, b;
642 u32 vco_freq;
643
644 vco_freq = freq * post_div;
645 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
646 a.full = dfixed_const(pll->reference_freq);
647 feedback_divider.full = dfixed_const(vco_freq);
648 feedback_divider.full = dfixed_div(feedback_divider, a);
649 a.full = dfixed_const(ref_div);
650 feedback_divider.full = dfixed_mul(feedback_divider, a);
651
652 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
653 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
654 a.full = dfixed_const(10);
655 feedback_divider.full = dfixed_mul(feedback_divider, a);
656 feedback_divider.full += dfixed_const_half(0);
657 feedback_divider.full = dfixed_floor(feedback_divider);
658 feedback_divider.full = dfixed_div(feedback_divider, a);
659
660 /* *fb_div = floor(feedback_divider); */
661 a.full = dfixed_floor(feedback_divider);
662 *fb_div = dfixed_trunc(a);
663 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
664 a.full = dfixed_const(10);
665 b.full = dfixed_mul(feedback_divider, a);
666
667 feedback_divider.full = dfixed_floor(feedback_divider);
668 feedback_divider.full = dfixed_mul(feedback_divider, a);
669 feedback_divider.full = b.full - feedback_divider.full;
670 *fb_div_frac = dfixed_trunc(feedback_divider);
671 } else {
672 /* *fb_div = floor(feedback_divider + 0.5); */
673 feedback_divider.full += dfixed_const_half(0);
674 feedback_divider.full = dfixed_floor(feedback_divider);
675
676 *fb_div = dfixed_trunc(feedback_divider);
677 *fb_div_frac = 0;
678 }
679
680 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
681 return false;
682 else
683 return true;
684 }
685
686 static bool
687 calc_fb_ref_div(struct radeon_pll *pll,
688 uint32_t freq,
689 uint32_t post_div,
690 uint32_t *fb_div,
691 uint32_t *fb_div_frac,
692 uint32_t *ref_div)
693 {
694 fixed20_12 ffreq, max_error, error, pll_out, a;
695 u32 vco;
696 u32 pll_out_min, pll_out_max;
697
698 if (pll->flags & RADEON_PLL_IS_LCD) {
699 pll_out_min = pll->lcd_pll_out_min;
700 pll_out_max = pll->lcd_pll_out_max;
701 } else {
702 pll_out_min = pll->pll_out_min;
703 pll_out_max = pll->pll_out_max;
704 }
705
706 ffreq.full = dfixed_const(freq);
707 /* max_error = ffreq * 0.0025; */
708 a.full = dfixed_const(400);
709 max_error.full = dfixed_div(ffreq, a);
710
711 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
712 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
713 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
714 vco = vco / ((*ref_div) * 10);
715
716 if ((vco < pll_out_min) || (vco > pll_out_max))
717 continue;
718
719 /* pll_out = vco / post_div; */
720 a.full = dfixed_const(post_div);
721 pll_out.full = dfixed_const(vco);
722 pll_out.full = dfixed_div(pll_out, a);
723
724 if (pll_out.full >= ffreq.full) {
725 error.full = pll_out.full - ffreq.full;
726 if (error.full <= max_error.full)
727 return true;
728 }
729 }
730 }
731 return false;
732 }
733
734 static void radeon_compute_pll_new(struct radeon_pll *pll,
735 uint64_t freq,
736 uint32_t *dot_clock_p,
737 uint32_t *fb_div_p,
738 uint32_t *frac_fb_div_p,
739 uint32_t *ref_div_p,
740 uint32_t *post_div_p)
741 {
742 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
743 u32 best_freq = 0, vco_frequency;
744 u32 pll_out_min, pll_out_max;
745
746 if (pll->flags & RADEON_PLL_IS_LCD) {
747 pll_out_min = pll->lcd_pll_out_min;
748 pll_out_max = pll->lcd_pll_out_max;
749 } else {
750 pll_out_min = pll->pll_out_min;
751 pll_out_max = pll->pll_out_max;
752 }
753
754 /* freq = freq / 10; */
755 do_div(freq, 10);
756
757 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
758 post_div = pll->post_div;
759 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
760 goto done;
761
762 vco_frequency = freq * post_div;
763 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
764 goto done;
765
766 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
767 ref_div = pll->reference_div;
768 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
769 goto done;
770 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
771 goto done;
772 }
773 } else {
774 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
775 if (pll->flags & RADEON_PLL_LEGACY) {
776 if ((post_div == 5) ||
777 (post_div == 7) ||
778 (post_div == 9) ||
779 (post_div == 10) ||
780 (post_div == 11))
781 continue;
782 }
783
784 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
785 continue;
786
787 vco_frequency = freq * post_div;
788 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
789 continue;
790 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
791 ref_div = pll->reference_div;
792 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
793 goto done;
794 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
795 break;
796 } else {
797 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
798 break;
799 }
800 }
801 }
802
803 best_freq = pll->reference_freq * 10 * fb_div;
804 best_freq += pll->reference_freq * fb_div_frac;
805 best_freq = best_freq / (ref_div * post_div);
806
807 done:
808 if (best_freq == 0)
809 DRM_ERROR("Couldn't find valid PLL dividers\n");
810
811 *dot_clock_p = best_freq / 10;
812 *fb_div_p = fb_div;
813 *frac_fb_div_p = fb_div_frac;
814 *ref_div_p = ref_div;
815 *post_div_p = post_div;
816
817 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
818 }
819
820 void radeon_compute_pll(struct radeon_pll *pll,
821 uint64_t freq,
822 uint32_t *dot_clock_p,
823 uint32_t *fb_div_p,
824 uint32_t *frac_fb_div_p,
825 uint32_t *ref_div_p,
826 uint32_t *post_div_p)
827 {
828 switch (pll->algo) {
829 case PLL_ALGO_NEW:
830 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
831 frac_fb_div_p, ref_div_p, post_div_p);
832 break;
833 case PLL_ALGO_LEGACY:
834 default:
835 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
836 frac_fb_div_p, ref_div_p, post_div_p);
837 break;
838 }
839 }
840
841 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
842 {
843 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
844
845 if (radeon_fb->obj) {
846 drm_gem_object_unreference_unlocked(radeon_fb->obj);
847 }
848 drm_framebuffer_cleanup(fb);
849 kfree(radeon_fb);
850 }
851
852 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
853 struct drm_file *file_priv,
854 unsigned int *handle)
855 {
856 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
857
858 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
859 }
860
861 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
862 .destroy = radeon_user_framebuffer_destroy,
863 .create_handle = radeon_user_framebuffer_create_handle,
864 };
865
866 void
867 radeon_framebuffer_init(struct drm_device *dev,
868 struct radeon_framebuffer *rfb,
869 struct drm_mode_fb_cmd *mode_cmd,
870 struct drm_gem_object *obj)
871 {
872 rfb->obj = obj;
873 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
874 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
875 }
876
877 static struct drm_framebuffer *
878 radeon_user_framebuffer_create(struct drm_device *dev,
879 struct drm_file *file_priv,
880 struct drm_mode_fb_cmd *mode_cmd)
881 {
882 struct drm_gem_object *obj;
883 struct radeon_framebuffer *radeon_fb;
884
885 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
886 if (obj == NULL) {
887 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
888 "can't create framebuffer\n", mode_cmd->handle);
889 return ERR_PTR(-ENOENT);
890 }
891
892 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
893 if (radeon_fb == NULL)
894 return ERR_PTR(-ENOMEM);
895
896 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
897
898 return &radeon_fb->base;
899 }
900
901 static void radeon_output_poll_changed(struct drm_device *dev)
902 {
903 struct radeon_device *rdev = dev->dev_private;
904 radeon_fb_output_poll_changed(rdev);
905 }
906
907 static const struct drm_mode_config_funcs radeon_mode_funcs = {
908 .fb_create = radeon_user_framebuffer_create,
909 .output_poll_changed = radeon_output_poll_changed
910 };
911
912 struct drm_prop_enum_list {
913 int type;
914 char *name;
915 };
916
917 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
918 { { 0, "driver" },
919 { 1, "bios" },
920 };
921
922 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
923 { { TV_STD_NTSC, "ntsc" },
924 { TV_STD_PAL, "pal" },
925 { TV_STD_PAL_M, "pal-m" },
926 { TV_STD_PAL_60, "pal-60" },
927 { TV_STD_NTSC_J, "ntsc-j" },
928 { TV_STD_SCART_PAL, "scart-pal" },
929 { TV_STD_PAL_CN, "pal-cn" },
930 { TV_STD_SECAM, "secam" },
931 };
932
933 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
934 { { UNDERSCAN_OFF, "off" },
935 { UNDERSCAN_ON, "on" },
936 { UNDERSCAN_AUTO, "auto" },
937 };
938
939 static int radeon_modeset_create_props(struct radeon_device *rdev)
940 {
941 int i, sz;
942
943 if (rdev->is_atom_bios) {
944 rdev->mode_info.coherent_mode_property =
945 drm_property_create(rdev->ddev,
946 DRM_MODE_PROP_RANGE,
947 "coherent", 2);
948 if (!rdev->mode_info.coherent_mode_property)
949 return -ENOMEM;
950
951 rdev->mode_info.coherent_mode_property->values[0] = 0;
952 rdev->mode_info.coherent_mode_property->values[1] = 1;
953 }
954
955 if (!ASIC_IS_AVIVO(rdev)) {
956 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
957 rdev->mode_info.tmds_pll_property =
958 drm_property_create(rdev->ddev,
959 DRM_MODE_PROP_ENUM,
960 "tmds_pll", sz);
961 for (i = 0; i < sz; i++) {
962 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
963 i,
964 radeon_tmds_pll_enum_list[i].type,
965 radeon_tmds_pll_enum_list[i].name);
966 }
967 }
968
969 rdev->mode_info.load_detect_property =
970 drm_property_create(rdev->ddev,
971 DRM_MODE_PROP_RANGE,
972 "load detection", 2);
973 if (!rdev->mode_info.load_detect_property)
974 return -ENOMEM;
975 rdev->mode_info.load_detect_property->values[0] = 0;
976 rdev->mode_info.load_detect_property->values[1] = 1;
977
978 drm_mode_create_scaling_mode_property(rdev->ddev);
979
980 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
981 rdev->mode_info.tv_std_property =
982 drm_property_create(rdev->ddev,
983 DRM_MODE_PROP_ENUM,
984 "tv standard", sz);
985 for (i = 0; i < sz; i++) {
986 drm_property_add_enum(rdev->mode_info.tv_std_property,
987 i,
988 radeon_tv_std_enum_list[i].type,
989 radeon_tv_std_enum_list[i].name);
990 }
991
992 sz = ARRAY_SIZE(radeon_underscan_enum_list);
993 rdev->mode_info.underscan_property =
994 drm_property_create(rdev->ddev,
995 DRM_MODE_PROP_ENUM,
996 "underscan", sz);
997 for (i = 0; i < sz; i++) {
998 drm_property_add_enum(rdev->mode_info.underscan_property,
999 i,
1000 radeon_underscan_enum_list[i].type,
1001 radeon_underscan_enum_list[i].name);
1002 }
1003
1004 return 0;
1005 }
1006
1007 void radeon_update_display_priority(struct radeon_device *rdev)
1008 {
1009 /* adjustment options for the display watermarks */
1010 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1011 /* set display priority to high for r3xx, rv515 chips
1012 * this avoids flickering due to underflow to the
1013 * display controllers during heavy acceleration.
1014 * Don't force high on rs4xx igp chips as it seems to
1015 * affect the sound card. See kernel bug 15982.
1016 */
1017 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1018 !(rdev->flags & RADEON_IS_IGP))
1019 rdev->disp_priority = 2;
1020 else
1021 rdev->disp_priority = 0;
1022 } else
1023 rdev->disp_priority = radeon_disp_priority;
1024
1025 }
1026
1027 int radeon_modeset_init(struct radeon_device *rdev)
1028 {
1029 int i;
1030 int ret;
1031
1032 drm_mode_config_init(rdev->ddev);
1033 rdev->mode_info.mode_config_initialized = true;
1034
1035 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1036
1037 if (ASIC_IS_AVIVO(rdev)) {
1038 rdev->ddev->mode_config.max_width = 8192;
1039 rdev->ddev->mode_config.max_height = 8192;
1040 } else {
1041 rdev->ddev->mode_config.max_width = 4096;
1042 rdev->ddev->mode_config.max_height = 4096;
1043 }
1044
1045 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1046
1047 ret = radeon_modeset_create_props(rdev);
1048 if (ret) {
1049 return ret;
1050 }
1051
1052 /* init i2c buses */
1053 radeon_i2c_init(rdev);
1054
1055 /* check combios for a valid hardcoded EDID - Sun servers */
1056 if (!rdev->is_atom_bios) {
1057 /* check for hardcoded EDID in BIOS */
1058 radeon_combios_check_hardcoded_edid(rdev);
1059 }
1060
1061 /* allocate crtcs */
1062 for (i = 0; i < rdev->num_crtc; i++) {
1063 radeon_crtc_init(rdev->ddev, i);
1064 }
1065
1066 /* okay we should have all the bios connectors */
1067 ret = radeon_setup_enc_conn(rdev->ddev);
1068 if (!ret) {
1069 return ret;
1070 }
1071 /* initialize hpd */
1072 radeon_hpd_init(rdev);
1073
1074 /* Initialize power management */
1075 radeon_pm_init(rdev);
1076
1077 radeon_fbdev_init(rdev);
1078 drm_kms_helper_poll_init(rdev->ddev);
1079
1080 return 0;
1081 }
1082
1083 void radeon_modeset_fini(struct radeon_device *rdev)
1084 {
1085 radeon_fbdev_fini(rdev);
1086 kfree(rdev->mode_info.bios_hardcoded_edid);
1087 radeon_pm_fini(rdev);
1088
1089 if (rdev->mode_info.mode_config_initialized) {
1090 drm_kms_helper_poll_fini(rdev->ddev);
1091 radeon_hpd_fini(rdev);
1092 drm_mode_config_cleanup(rdev->ddev);
1093 rdev->mode_info.mode_config_initialized = false;
1094 }
1095 /* free i2c buses */
1096 radeon_i2c_fini(rdev);
1097 }
1098
1099 static bool is_hdtv_mode(struct drm_display_mode *mode)
1100 {
1101 /* try and guess if this is a tv or a monitor */
1102 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1103 (mode->vdisplay == 576) || /* 576p */
1104 (mode->vdisplay == 720) || /* 720p */
1105 (mode->vdisplay == 1080)) /* 1080p */
1106 return true;
1107 else
1108 return false;
1109 }
1110
1111 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1112 struct drm_display_mode *mode,
1113 struct drm_display_mode *adjusted_mode)
1114 {
1115 struct drm_device *dev = crtc->dev;
1116 struct radeon_device *rdev = dev->dev_private;
1117 struct drm_encoder *encoder;
1118 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1119 struct radeon_encoder *radeon_encoder;
1120 struct drm_connector *connector;
1121 struct radeon_connector *radeon_connector;
1122 bool first = true;
1123 u32 src_v = 1, dst_v = 1;
1124 u32 src_h = 1, dst_h = 1;
1125
1126 radeon_crtc->h_border = 0;
1127 radeon_crtc->v_border = 0;
1128
1129 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1130 if (encoder->crtc != crtc)
1131 continue;
1132 radeon_encoder = to_radeon_encoder(encoder);
1133 connector = radeon_get_connector_for_encoder(encoder);
1134 radeon_connector = to_radeon_connector(connector);
1135
1136 if (first) {
1137 /* set scaling */
1138 if (radeon_encoder->rmx_type == RMX_OFF)
1139 radeon_crtc->rmx_type = RMX_OFF;
1140 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1141 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1142 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1143 else
1144 radeon_crtc->rmx_type = RMX_OFF;
1145 /* copy native mode */
1146 memcpy(&radeon_crtc->native_mode,
1147 &radeon_encoder->native_mode,
1148 sizeof(struct drm_display_mode));
1149 src_v = crtc->mode.vdisplay;
1150 dst_v = radeon_crtc->native_mode.vdisplay;
1151 src_h = crtc->mode.hdisplay;
1152 dst_h = radeon_crtc->native_mode.hdisplay;
1153
1154 /* fix up for overscan on hdmi */
1155 if (ASIC_IS_AVIVO(rdev) &&
1156 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1157 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1158 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1159 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1160 is_hdtv_mode(mode)))) {
1161 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1162 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1163 radeon_crtc->rmx_type = RMX_FULL;
1164 src_v = crtc->mode.vdisplay;
1165 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1166 src_h = crtc->mode.hdisplay;
1167 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1168 }
1169 first = false;
1170 } else {
1171 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1172 /* WARNING: Right now this can't happen but
1173 * in the future we need to check that scaling
1174 * are consistent across different encoder
1175 * (ie all encoder can work with the same
1176 * scaling).
1177 */
1178 DRM_ERROR("Scaling not consistent across encoder.\n");
1179 return false;
1180 }
1181 }
1182 }
1183 if (radeon_crtc->rmx_type != RMX_OFF) {
1184 fixed20_12 a, b;
1185 a.full = dfixed_const(src_v);
1186 b.full = dfixed_const(dst_v);
1187 radeon_crtc->vsc.full = dfixed_div(a, b);
1188 a.full = dfixed_const(src_h);
1189 b.full = dfixed_const(dst_h);
1190 radeon_crtc->hsc.full = dfixed_div(a, b);
1191 } else {
1192 radeon_crtc->vsc.full = dfixed_const(1);
1193 radeon_crtc->hsc.full = dfixed_const(1);
1194 }
1195 return true;
1196 }
Tomato firmware and modifications.