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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / radeon_combios.c
blobb823c53091a8d94f2e14de4c127faf5c4dddb98e
1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447 }
448
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 {
451 int edid_info;
452 struct edid *edid;
453 unsigned char *raw;
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
460 if (edid == NULL)
461 return false;
462
463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472 }
473
474 struct edid *
475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476 {
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480 }
481
482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 enum radeon_combios_ddc ddc,
484 u32 clk_mask,
485 u32 data_mask)
486 {
487 struct radeon_i2c_bus_rec i2c;
488 int ddc_line = 0;
489
490 /* ddc id = mask reg
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
496 * r1xx/r2xx
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
499 * r3xx
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
502 * rs3xx/rs4xx
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
505 */
506 switch (ddc) {
507 case DDC_NONE_DETECTED:
508 default:
509 ddc_line = 0;
510 break;
511 case DDC_DVI:
512 ddc_line = RADEON_GPIO_DVI_DDC;
513 break;
514 case DDC_VGA:
515 ddc_line = RADEON_GPIO_VGA_DDC;
516 break;
517 case DDC_LCD:
518 ddc_line = RADEON_GPIOPAD_MASK;
519 break;
520 case DDC_GPIO:
521 ddc_line = RADEON_MDGPIO_MASK;
522 break;
523 case DDC_MONID:
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
528 else
529 ddc_line = RADEON_GPIO_MONID;
530 break;
531 case DDC_CRT2:
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
538 ddc = DDC_DVI;
539 } else
540 ddc_line = RADEON_GPIO_CRT2_DDC;
541 break;
542 }
543
544 if (ddc_line == RADEON_GPIOPAD_MASK) {
545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
546 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
547 i2c.a_clk_reg = RADEON_GPIOPAD_A;
548 i2c.a_data_reg = RADEON_GPIOPAD_A;
549 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
550 i2c.en_data_reg = RADEON_GPIOPAD_EN;
551 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
552 i2c.y_data_reg = RADEON_GPIOPAD_Y;
553 } else if (ddc_line == RADEON_MDGPIO_MASK) {
554 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
555 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
556 i2c.a_clk_reg = RADEON_MDGPIO_A;
557 i2c.a_data_reg = RADEON_MDGPIO_A;
558 i2c.en_clk_reg = RADEON_MDGPIO_EN;
559 i2c.en_data_reg = RADEON_MDGPIO_EN;
560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
561 i2c.y_data_reg = RADEON_MDGPIO_Y;
562 } else {
563 i2c.mask_clk_reg = ddc_line;
564 i2c.mask_data_reg = ddc_line;
565 i2c.a_clk_reg = ddc_line;
566 i2c.a_data_reg = ddc_line;
567 i2c.en_clk_reg = ddc_line;
568 i2c.en_data_reg = ddc_line;
569 i2c.y_clk_reg = ddc_line;
570 i2c.y_data_reg = ddc_line;
571 }
572
573 if (clk_mask && data_mask) {
574 /* system specific masks */
575 i2c.mask_clk_mask = clk_mask;
576 i2c.mask_data_mask = data_mask;
577 i2c.a_clk_mask = clk_mask;
578 i2c.a_data_mask = data_mask;
579 i2c.en_clk_mask = clk_mask;
580 i2c.en_data_mask = data_mask;
581 i2c.y_clk_mask = clk_mask;
582 i2c.y_data_mask = data_mask;
583 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
584 (ddc_line == RADEON_MDGPIO_MASK)) {
585 /* default gpiopad masks */
586 i2c.mask_clk_mask = (0x20 << 8);
587 i2c.mask_data_mask = 0x80;
588 i2c.a_clk_mask = (0x20 << 8);
589 i2c.a_data_mask = 0x80;
590 i2c.en_clk_mask = (0x20 << 8);
591 i2c.en_data_mask = 0x80;
592 i2c.y_clk_mask = (0x20 << 8);
593 i2c.y_data_mask = 0x80;
594 } else {
595 /* default masks for ddc pads */
596 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
597 i2c.mask_data_mask = RADEON_GPIO_EN_0;
598 i2c.a_clk_mask = RADEON_GPIO_A_1;
599 i2c.a_data_mask = RADEON_GPIO_A_0;
600 i2c.en_clk_mask = RADEON_GPIO_EN_1;
601 i2c.en_data_mask = RADEON_GPIO_EN_0;
602 i2c.y_clk_mask = RADEON_GPIO_Y_1;
603 i2c.y_data_mask = RADEON_GPIO_Y_0;
604 }
605
606 switch (rdev->family) {
607 case CHIP_R100:
608 case CHIP_RV100:
609 case CHIP_RS100:
610 case CHIP_RV200:
611 case CHIP_RS200:
612 case CHIP_RS300:
613 switch (ddc_line) {
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
616 break;
617 default:
618 i2c.hw_capable = false;
619 break;
620 }
621 break;
622 case CHIP_R200:
623 switch (ddc_line) {
624 case RADEON_GPIO_DVI_DDC:
625 case RADEON_GPIO_MONID:
626 i2c.hw_capable = true;
627 break;
628 default:
629 i2c.hw_capable = false;
630 break;
631 }
632 break;
633 case CHIP_RV250:
634 case CHIP_RV280:
635 switch (ddc_line) {
636 case RADEON_GPIO_VGA_DDC:
637 case RADEON_GPIO_DVI_DDC:
638 case RADEON_GPIO_CRT2_DDC:
639 i2c.hw_capable = true;
640 break;
641 default:
642 i2c.hw_capable = false;
643 break;
644 }
645 break;
646 case CHIP_R300:
647 case CHIP_R350:
648 switch (ddc_line) {
649 case RADEON_GPIO_VGA_DDC:
650 case RADEON_GPIO_DVI_DDC:
651 i2c.hw_capable = true;
652 break;
653 default:
654 i2c.hw_capable = false;
655 break;
656 }
657 break;
658 case CHIP_RV350:
659 case CHIP_RV380:
660 case CHIP_RS400:
661 case CHIP_RS480:
662 switch (ddc_line) {
663 case RADEON_GPIO_VGA_DDC:
664 case RADEON_GPIO_DVI_DDC:
665 i2c.hw_capable = true;
666 break;
667 case RADEON_GPIO_MONID:
668 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
669 * reliably on some pre-r4xx hardware; not sure why.
670 */
671 i2c.hw_capable = false;
672 break;
673 default:
674 i2c.hw_capable = false;
675 break;
676 }
677 break;
678 default:
679 i2c.hw_capable = false;
680 break;
681 }
682 i2c.mm_i2c = false;
683
684 i2c.i2c_id = ddc;
685 i2c.hpd = RADEON_HPD_NONE;
686
687 if (ddc_line)
688 i2c.valid = true;
689 else
690 i2c.valid = false;
691
692 return i2c;
693 }
694
695 void radeon_combios_i2c_init(struct radeon_device *rdev)
696 {
697 struct drm_device *dev = rdev->ddev;
698 struct radeon_i2c_bus_rec i2c;
699
700
701 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
702 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
703
704 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
705 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
706
707 i2c.valid = true;
708 i2c.hw_capable = true;
709 i2c.mm_i2c = true;
710 i2c.i2c_id = 0xa0;
711 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
712
713 if (rdev->family == CHIP_RS300 ||
714 rdev->family == CHIP_RS400 ||
715 rdev->family == CHIP_RS480) {
716 u16 offset;
717 u8 id, blocks, clk, data;
718 int i;
719
720 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
721 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
722
723 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
724 if (offset) {
725 blocks = RBIOS8(offset + 2);
726 for (i = 0; i < blocks; i++) {
727 id = RBIOS8(offset + 3 + (i * 5) + 0);
728 if (id == 136) {
729 clk = RBIOS8(offset + 3 + (i * 5) + 3);
730 data = RBIOS8(offset + 3 + (i * 5) + 4);
731 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
732 (1 << clk), (1 << data));
733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
734 break;
735 }
736 }
737 }
738
739 } else if (rdev->family >= CHIP_R300) {
740 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
741 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
742 } else {
743 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
744 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
745
746 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
747 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
748 }
749 }
750
751 bool radeon_combios_get_clock_info(struct drm_device *dev)
752 {
753 struct radeon_device *rdev = dev->dev_private;
754 uint16_t pll_info;
755 struct radeon_pll *p1pll = &rdev->clock.p1pll;
756 struct radeon_pll *p2pll = &rdev->clock.p2pll;
757 struct radeon_pll *spll = &rdev->clock.spll;
758 struct radeon_pll *mpll = &rdev->clock.mpll;
759 int8_t rev;
760 uint16_t sclk, mclk;
761
762 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
763 if (pll_info) {
764 rev = RBIOS8(pll_info);
765
766 /* pixel clocks */
767 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
768 p1pll->reference_div = RBIOS16(pll_info + 0x10);
769 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
770 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
771 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
772 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
773
774 if (rev > 9) {
775 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
776 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
777 } else {
778 p1pll->pll_in_min = 40;
779 p1pll->pll_in_max = 500;
780 }
781 *p2pll = *p1pll;
782
783 /* system clock */
784 spll->reference_freq = RBIOS16(pll_info + 0x1a);
785 spll->reference_div = RBIOS16(pll_info + 0x1c);
786 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
787 spll->pll_out_max = RBIOS32(pll_info + 0x22);
788
789 if (rev > 10) {
790 spll->pll_in_min = RBIOS32(pll_info + 0x48);
791 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
792 } else {
793 /* ??? */
794 spll->pll_in_min = 40;
795 spll->pll_in_max = 500;
796 }
797
798 /* memory clock */
799 mpll->reference_freq = RBIOS16(pll_info + 0x26);
800 mpll->reference_div = RBIOS16(pll_info + 0x28);
801 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
802 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
803
804 if (rev > 10) {
805 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
806 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
807 } else {
808 /* ??? */
809 mpll->pll_in_min = 40;
810 mpll->pll_in_max = 500;
811 }
812
813 /* default sclk/mclk */
814 sclk = RBIOS16(pll_info + 0xa);
815 mclk = RBIOS16(pll_info + 0x8);
816 if (sclk == 0)
817 sclk = 200 * 100;
818 if (mclk == 0)
819 mclk = 200 * 100;
820
821 rdev->clock.default_sclk = sclk;
822 rdev->clock.default_mclk = mclk;
823
824 return true;
825 }
826 return false;
827 }
828
829 bool radeon_combios_sideport_present(struct radeon_device *rdev)
830 {
831 struct drm_device *dev = rdev->ddev;
832 u16 igp_info;
833
834 /* sideport is AMD only */
835 if (rdev->family == CHIP_RS400)
836 return false;
837
838 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
839
840 if (igp_info) {
841 if (RBIOS16(igp_info + 0x4))
842 return true;
843 }
844 return false;
845 }
846
847 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
848 0x00000808, /* r100 */
849 0x00000808, /* rv100 */
850 0x00000808, /* rs100 */
851 0x00000808, /* rv200 */
852 0x00000808, /* rs200 */
853 0x00000808, /* r200 */
854 0x00000808, /* rv250 */
855 0x00000000, /* rs300 */
856 0x00000808, /* rv280 */
857 0x00000808, /* r300 */
858 0x00000808, /* r350 */
859 0x00000808, /* rv350 */
860 0x00000808, /* rv380 */
861 0x00000808, /* r420 */
862 0x00000808, /* r423 */
863 0x00000808, /* rv410 */
864 0x00000000, /* rs400 */
865 0x00000000, /* rs480 */
866 };
867
868 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
869 struct radeon_encoder_primary_dac *p_dac)
870 {
871 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
872 return;
873 }
874
875 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
876 radeon_encoder
877 *encoder)
878 {
879 struct drm_device *dev = encoder->base.dev;
880 struct radeon_device *rdev = dev->dev_private;
881 uint16_t dac_info;
882 uint8_t rev, bg, dac;
883 struct radeon_encoder_primary_dac *p_dac = NULL;
884 int found = 0;
885
886 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
887 GFP_KERNEL);
888
889 if (!p_dac)
890 return NULL;
891
892 /* check CRT table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
894 if (dac_info) {
895 rev = RBIOS8(dac_info) & 0x3;
896 if (rev < 2) {
897 bg = RBIOS8(dac_info + 0x2) & 0xf;
898 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
899 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
900 } else {
901 bg = RBIOS8(dac_info + 0x2) & 0xf;
902 dac = RBIOS8(dac_info + 0x3) & 0xf;
903 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
904 }
905 /* if the values are all zeros, use the table */
906 if (p_dac->ps2_pdac_adj)
907 found = 1;
908 }
909
910 if (!found) /* fallback to defaults */
911 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
912
913 return p_dac;
914 }
915
916 enum radeon_tv_std
917 radeon_combios_get_tv_info(struct radeon_device *rdev)
918 {
919 struct drm_device *dev = rdev->ddev;
920 uint16_t tv_info;
921 enum radeon_tv_std tv_std = TV_STD_NTSC;
922
923 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
924 if (tv_info) {
925 if (RBIOS8(tv_info + 6) == 'T') {
926 switch (RBIOS8(tv_info + 7) & 0xf) {
927 case 1:
928 tv_std = TV_STD_NTSC;
929 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
930 break;
931 case 2:
932 tv_std = TV_STD_PAL;
933 DRM_DEBUG_KMS("Default TV standard: PAL\n");
934 break;
935 case 3:
936 tv_std = TV_STD_PAL_M;
937 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
938 break;
939 case 4:
940 tv_std = TV_STD_PAL_60;
941 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
942 break;
943 case 5:
944 tv_std = TV_STD_NTSC_J;
945 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
946 break;
947 case 6:
948 tv_std = TV_STD_SCART_PAL;
949 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
950 break;
951 default:
952 tv_std = TV_STD_NTSC;
953 DRM_DEBUG_KMS
954 ("Unknown TV standard; defaulting to NTSC\n");
955 break;
956 }
957
958 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
959 case 0:
960 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
961 break;
962 case 1:
963 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
964 break;
965 case 2:
966 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
967 break;
968 case 3:
969 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
970 break;
971 default:
972 break;
973 }
974 }
975 }
976 return tv_std;
977 }
978
979 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
980 0x00000000, /* r100 */
981 0x00280000, /* rv100 */
982 0x00000000, /* rs100 */
983 0x00880000, /* rv200 */
984 0x00000000, /* rs200 */
985 0x00000000, /* r200 */
986 0x00770000, /* rv250 */
987 0x00290000, /* rs300 */
988 0x00560000, /* rv280 */
989 0x00780000, /* r300 */
990 0x00770000, /* r350 */
991 0x00780000, /* rv350 */
992 0x00780000, /* rv380 */
993 0x01080000, /* r420 */
994 0x01080000, /* r423 */
995 0x01080000, /* rv410 */
996 0x00780000, /* rs400 */
997 0x00780000, /* rs480 */
998 };
999
1000 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1001 struct radeon_encoder_tv_dac *tv_dac)
1002 {
1003 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1004 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1005 tv_dac->ps2_tvdac_adj = 0x00880000;
1006 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1007 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1008 return;
1009 }
1010
1011 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1012 radeon_encoder
1013 *encoder)
1014 {
1015 struct drm_device *dev = encoder->base.dev;
1016 struct radeon_device *rdev = dev->dev_private;
1017 uint16_t dac_info;
1018 uint8_t rev, bg, dac;
1019 struct radeon_encoder_tv_dac *tv_dac = NULL;
1020 int found = 0;
1021
1022 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1023 if (!tv_dac)
1024 return NULL;
1025
1026 /* first check TV table */
1027 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1028 if (dac_info) {
1029 rev = RBIOS8(dac_info + 0x3);
1030 if (rev > 4) {
1031 bg = RBIOS8(dac_info + 0xc) & 0xf;
1032 dac = RBIOS8(dac_info + 0xd) & 0xf;
1033 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1034
1035 bg = RBIOS8(dac_info + 0xe) & 0xf;
1036 dac = RBIOS8(dac_info + 0xf) & 0xf;
1037 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1038
1039 bg = RBIOS8(dac_info + 0x10) & 0xf;
1040 dac = RBIOS8(dac_info + 0x11) & 0xf;
1041 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1042 /* if the values are all zeros, use the table */
1043 if (tv_dac->ps2_tvdac_adj)
1044 found = 1;
1045 } else if (rev > 1) {
1046 bg = RBIOS8(dac_info + 0xc) & 0xf;
1047 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1048 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1049
1050 bg = RBIOS8(dac_info + 0xd) & 0xf;
1051 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1052 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1053
1054 bg = RBIOS8(dac_info + 0xe) & 0xf;
1055 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1056 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1057 /* if the values are all zeros, use the table */
1058 if (tv_dac->ps2_tvdac_adj)
1059 found = 1;
1060 }
1061 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1062 }
1063 if (!found) {
1064 /* then check CRT table */
1065 dac_info =
1066 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1067 if (dac_info) {
1068 rev = RBIOS8(dac_info) & 0x3;
1069 if (rev < 2) {
1070 bg = RBIOS8(dac_info + 0x3) & 0xf;
1071 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1072 tv_dac->ps2_tvdac_adj =
1073 (bg << 16) | (dac << 20);
1074 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1075 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1076 /* if the values are all zeros, use the table */
1077 if (tv_dac->ps2_tvdac_adj)
1078 found = 1;
1079 } else {
1080 bg = RBIOS8(dac_info + 0x4) & 0xf;
1081 dac = RBIOS8(dac_info + 0x5) & 0xf;
1082 tv_dac->ps2_tvdac_adj =
1083 (bg << 16) | (dac << 20);
1084 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1085 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086 /* if the values are all zeros, use the table */
1087 if (tv_dac->ps2_tvdac_adj)
1088 found = 1;
1089 }
1090 } else {
1091 DRM_INFO("No TV DAC info found in BIOS\n");
1092 }
1093 }
1094
1095 if (!found) /* fallback to defaults */
1096 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1097
1098 return tv_dac;
1099 }
1100
1101 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1102 radeon_device
1103 *rdev)
1104 {
1105 struct radeon_encoder_lvds *lvds = NULL;
1106 uint32_t fp_vert_stretch, fp_horz_stretch;
1107 uint32_t ppll_div_sel, ppll_val;
1108 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1109
1110 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1111
1112 if (!lvds)
1113 return NULL;
1114
1115 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1116 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1117
1118 /* These should be fail-safe defaults, fingers crossed */
1119 lvds->panel_pwr_delay = 200;
1120 lvds->panel_vcc_delay = 2000;
1121
1122 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1123 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1124 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1125
1126 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1127 lvds->native_mode.vdisplay =
1128 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1129 RADEON_VERT_PANEL_SHIFT) + 1;
1130 else
1131 lvds->native_mode.vdisplay =
1132 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1133
1134 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1135 lvds->native_mode.hdisplay =
1136 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1137 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1138 else
1139 lvds->native_mode.hdisplay =
1140 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1141
1142 if ((lvds->native_mode.hdisplay < 640) ||
1143 (lvds->native_mode.vdisplay < 480)) {
1144 lvds->native_mode.hdisplay = 640;
1145 lvds->native_mode.vdisplay = 480;
1146 }
1147
1148 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1149 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1150 if ((ppll_val & 0x000707ff) == 0x1bb)
1151 lvds->use_bios_dividers = false;
1152 else {
1153 lvds->panel_ref_divider =
1154 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1155 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1156 lvds->panel_fb_divider = ppll_val & 0x7ff;
1157
1158 if ((lvds->panel_ref_divider != 0) &&
1159 (lvds->panel_fb_divider > 3))
1160 lvds->use_bios_dividers = true;
1161 }
1162 lvds->panel_vcc_delay = 200;
1163
1164 DRM_INFO("Panel info derived from registers\n");
1165 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1166 lvds->native_mode.vdisplay);
1167
1168 return lvds;
1169 }
1170
1171 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1172 *encoder)
1173 {
1174 struct drm_device *dev = encoder->base.dev;
1175 struct radeon_device *rdev = dev->dev_private;
1176 uint16_t lcd_info;
1177 uint32_t panel_setup;
1178 char stmp[30];
1179 int tmp, i;
1180 struct radeon_encoder_lvds *lvds = NULL;
1181
1182 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1183
1184 if (lcd_info) {
1185 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1186
1187 if (!lvds)
1188 return NULL;
1189
1190 for (i = 0; i < 24; i++)
1191 stmp[i] = RBIOS8(lcd_info + i + 1);
1192 stmp[24] = 0;
1193
1194 DRM_INFO("Panel ID String: %s\n", stmp);
1195
1196 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1197 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1198
1199 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1200 lvds->native_mode.vdisplay);
1201
1202 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1203 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1204
1205 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1206 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1207 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1208
1209 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1210 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1211 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1212 if ((lvds->panel_ref_divider != 0) &&
1213 (lvds->panel_fb_divider > 3))
1214 lvds->use_bios_dividers = true;
1215
1216 panel_setup = RBIOS32(lcd_info + 0x39);
1217 lvds->lvds_gen_cntl = 0xff00;
1218 if (panel_setup & 0x1)
1219 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1220
1221 if ((panel_setup >> 4) & 0x1)
1222 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1223
1224 switch ((panel_setup >> 8) & 0x7) {
1225 case 0:
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1227 break;
1228 case 1:
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1230 break;
1231 case 2:
1232 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1233 break;
1234 default:
1235 break;
1236 }
1237
1238 if ((panel_setup >> 16) & 0x1)
1239 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1240
1241 if ((panel_setup >> 17) & 0x1)
1242 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1243
1244 if ((panel_setup >> 18) & 0x1)
1245 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1246
1247 if ((panel_setup >> 23) & 0x1)
1248 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1249
1250 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1251
1252 for (i = 0; i < 32; i++) {
1253 tmp = RBIOS16(lcd_info + 64 + i * 2);
1254 if (tmp == 0)
1255 break;
1256
1257 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1258 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1259 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1260 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1261 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1262 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1263 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1264 (RBIOS8(tmp + 23) * 8);
1265
1266 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1267 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1268 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1269 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1270 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1271 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1272
1273 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1274 lvds->native_mode.flags = 0;
1275 /* set crtc values */
1276 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1277
1278 }
1279 }
1280 } else {
1281 DRM_INFO("No panel info found in BIOS\n");
1282 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1283 }
1284
1285 if (lvds)
1286 encoder->native_mode = lvds->native_mode;
1287 return lvds;
1288 }
1289
1290 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1293 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1294 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1296 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1297 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1298 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1299 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1309 };
1310
1311 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1312 struct radeon_encoder_int_tmds *tmds)
1313 {
1314 struct drm_device *dev = encoder->base.dev;
1315 struct radeon_device *rdev = dev->dev_private;
1316 int i;
1317
1318 for (i = 0; i < 4; i++) {
1319 tmds->tmds_pll[i].value =
1320 default_tmds_pll[rdev->family][i].value;
1321 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1322 }
1323
1324 return true;
1325 }
1326
1327 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1328 struct radeon_encoder_int_tmds *tmds)
1329 {
1330 struct drm_device *dev = encoder->base.dev;
1331 struct radeon_device *rdev = dev->dev_private;
1332 uint16_t tmds_info;
1333 int i, n;
1334 uint8_t ver;
1335
1336 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1337
1338 if (tmds_info) {
1339 ver = RBIOS8(tmds_info);
1340 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1341 if (ver == 3) {
1342 n = RBIOS8(tmds_info + 5) + 1;
1343 if (n > 4)
1344 n = 4;
1345 for (i = 0; i < n; i++) {
1346 tmds->tmds_pll[i].value =
1347 RBIOS32(tmds_info + i * 10 + 0x08);
1348 tmds->tmds_pll[i].freq =
1349 RBIOS16(tmds_info + i * 10 + 0x10);
1350 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1351 tmds->tmds_pll[i].freq,
1352 tmds->tmds_pll[i].value);
1353 }
1354 } else if (ver == 4) {
1355 int stride = 0;
1356 n = RBIOS8(tmds_info + 5) + 1;
1357 if (n > 4)
1358 n = 4;
1359 for (i = 0; i < n; i++) {
1360 tmds->tmds_pll[i].value =
1361 RBIOS32(tmds_info + stride + 0x08);
1362 tmds->tmds_pll[i].freq =
1363 RBIOS16(tmds_info + stride + 0x10);
1364 if (i == 0)
1365 stride += 10;
1366 else
1367 stride += 6;
1368 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1369 tmds->tmds_pll[i].freq,
1370 tmds->tmds_pll[i].value);
1371 }
1372 }
1373 } else {
1374 DRM_INFO("No TMDS info found in BIOS\n");
1375 return false;
1376 }
1377 return true;
1378 }
1379
1380 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1381 struct radeon_encoder_ext_tmds *tmds)
1382 {
1383 struct drm_device *dev = encoder->base.dev;
1384 struct radeon_device *rdev = dev->dev_private;
1385 struct radeon_i2c_bus_rec i2c_bus;
1386
1387 /* default for macs */
1388 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1389 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1390
1391 switch (rdev->mode_info.connector_table) {
1392 case CT_POWERBOOK_EXTERNAL:
1393 case CT_MINI_EXTERNAL:
1394 default:
1395 tmds->dvo_chip = DVO_SIL164;
1396 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1397 break;
1398 }
1399
1400 return true;
1401 }
1402
1403 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1404 struct radeon_encoder_ext_tmds *tmds)
1405 {
1406 struct drm_device *dev = encoder->base.dev;
1407 struct radeon_device *rdev = dev->dev_private;
1408 uint16_t offset;
1409 uint8_t ver;
1410 enum radeon_combios_ddc gpio;
1411 struct radeon_i2c_bus_rec i2c_bus;
1412
1413 tmds->i2c_bus = NULL;
1414 if (rdev->flags & RADEON_IS_IGP) {
1415 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1416 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1417 tmds->dvo_chip = DVO_SIL164;
1418 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1419 } else {
1420 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1421 if (offset) {
1422 ver = RBIOS8(offset);
1423 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1424 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1425 tmds->slave_addr >>= 1; /* 7 bit addressing */
1426 gpio = RBIOS8(offset + 4 + 3);
1427 if (gpio == DDC_LCD) {
1428 /* MM i2c */
1429 i2c_bus.valid = true;
1430 i2c_bus.hw_capable = true;
1431 i2c_bus.mm_i2c = true;
1432 i2c_bus.i2c_id = 0xa0;
1433 } else
1434 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1435 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1436 }
1437 }
1438
1439 if (!tmds->i2c_bus) {
1440 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1441 return false;
1442 }
1443
1444 return true;
1445 }
1446
1447 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1448 {
1449 struct radeon_device *rdev = dev->dev_private;
1450 struct radeon_i2c_bus_rec ddc_i2c;
1451 struct radeon_hpd hpd;
1452
1453 rdev->mode_info.connector_table = radeon_connector_table;
1454 if (rdev->mode_info.connector_table == CT_NONE) {
1455 #ifdef CONFIG_PPC_PMAC
1456 if (of_machine_is_compatible("PowerBook3,3")) {
1457 /* powerbook with VGA */
1458 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1459 } else if (of_machine_is_compatible("PowerBook3,4") ||
1460 of_machine_is_compatible("PowerBook3,5")) {
1461 /* powerbook with internal tmds */
1462 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1463 } else if (of_machine_is_compatible("PowerBook5,1") ||
1464 of_machine_is_compatible("PowerBook5,2") ||
1465 of_machine_is_compatible("PowerBook5,3") ||
1466 of_machine_is_compatible("PowerBook5,4") ||
1467 of_machine_is_compatible("PowerBook5,5")) {
1468 /* powerbook with external single link tmds (sil164) */
1469 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1470 } else if (of_machine_is_compatible("PowerBook5,6")) {
1471 /* powerbook with external dual or single link tmds */
1472 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1473 } else if (of_machine_is_compatible("PowerBook5,7") ||
1474 of_machine_is_compatible("PowerBook5,8") ||
1475 of_machine_is_compatible("PowerBook5,9")) {
1476 /* PowerBook6,2 ? */
1477 /* powerbook with external dual link tmds (sil1178?) */
1478 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1479 } else if (of_machine_is_compatible("PowerBook4,1") ||
1480 of_machine_is_compatible("PowerBook4,2") ||
1481 of_machine_is_compatible("PowerBook4,3") ||
1482 of_machine_is_compatible("PowerBook6,3") ||
1483 of_machine_is_compatible("PowerBook6,5") ||
1484 of_machine_is_compatible("PowerBook6,7")) {
1485 /* ibook */
1486 rdev->mode_info.connector_table = CT_IBOOK;
1487 } else if (of_machine_is_compatible("PowerMac4,4")) {
1488 /* emac */
1489 rdev->mode_info.connector_table = CT_EMAC;
1490 } else if (of_machine_is_compatible("PowerMac10,1")) {
1491 /* mini with internal tmds */
1492 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1493 } else if (of_machine_is_compatible("PowerMac10,2")) {
1494 /* mini with external tmds */
1495 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1496 } else if (of_machine_is_compatible("PowerMac12,1")) {
1497 /* PowerMac8,1 ? */
1498 /* imac g5 isight */
1499 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1500 } else if ((rdev->pdev->device == 0x4a48) &&
1501 (rdev->pdev->subsystem_vendor == 0x1002) &&
1502 (rdev->pdev->subsystem_device == 0x4a48)) {
1503 /* Mac X800 */
1504 rdev->mode_info.connector_table = CT_MAC_X800;
1505 } else
1506 #endif /* CONFIG_PPC_PMAC */
1507 #ifdef CONFIG_PPC64
1508 if (ASIC_IS_RN50(rdev))
1509 rdev->mode_info.connector_table = CT_RN50_POWER;
1510 else
1511 #endif
1512 rdev->mode_info.connector_table = CT_GENERIC;
1513 }
1514
1515 switch (rdev->mode_info.connector_table) {
1516 case CT_GENERIC:
1517 DRM_INFO("Connector Table: %d (generic)\n",
1518 rdev->mode_info.connector_table);
1519 /* these are the most common settings */
1520 if (rdev->flags & RADEON_SINGLE_CRTC) {
1521 /* VGA - primary dac */
1522 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1523 hpd.hpd = RADEON_HPD_NONE;
1524 radeon_add_legacy_encoder(dev,
1525 radeon_get_encoder_enum(dev,
1526 ATOM_DEVICE_CRT1_SUPPORT,
1527 1),
1528 ATOM_DEVICE_CRT1_SUPPORT);
1529 radeon_add_legacy_connector(dev, 0,
1530 ATOM_DEVICE_CRT1_SUPPORT,
1531 DRM_MODE_CONNECTOR_VGA,
1532 &ddc_i2c,
1533 CONNECTOR_OBJECT_ID_VGA,
1534 &hpd);
1535 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1536 /* LVDS */
1537 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1538 hpd.hpd = RADEON_HPD_NONE;
1539 radeon_add_legacy_encoder(dev,
1540 radeon_get_encoder_enum(dev,
1541 ATOM_DEVICE_LCD1_SUPPORT,
1542 0),
1543 ATOM_DEVICE_LCD1_SUPPORT);
1544 radeon_add_legacy_connector(dev, 0,
1545 ATOM_DEVICE_LCD1_SUPPORT,
1546 DRM_MODE_CONNECTOR_LVDS,
1547 &ddc_i2c,
1548 CONNECTOR_OBJECT_ID_LVDS,
1549 &hpd);
1550
1551 /* VGA - primary dac */
1552 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1553 hpd.hpd = RADEON_HPD_NONE;
1554 radeon_add_legacy_encoder(dev,
1555 radeon_get_encoder_enum(dev,
1556 ATOM_DEVICE_CRT1_SUPPORT,
1557 1),
1558 ATOM_DEVICE_CRT1_SUPPORT);
1559 radeon_add_legacy_connector(dev, 1,
1560 ATOM_DEVICE_CRT1_SUPPORT,
1561 DRM_MODE_CONNECTOR_VGA,
1562 &ddc_i2c,
1563 CONNECTOR_OBJECT_ID_VGA,
1564 &hpd);
1565 } else {
1566 /* DVI-I - tv dac, int tmds */
1567 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1568 hpd.hpd = RADEON_HPD_1;
1569 radeon_add_legacy_encoder(dev,
1570 radeon_get_encoder_enum(dev,
1571 ATOM_DEVICE_DFP1_SUPPORT,
1572 0),
1573 ATOM_DEVICE_DFP1_SUPPORT);
1574 radeon_add_legacy_encoder(dev,
1575 radeon_get_encoder_enum(dev,
1576 ATOM_DEVICE_CRT2_SUPPORT,
1577 2),
1578 ATOM_DEVICE_CRT2_SUPPORT);
1579 radeon_add_legacy_connector(dev, 0,
1580 ATOM_DEVICE_DFP1_SUPPORT |
1581 ATOM_DEVICE_CRT2_SUPPORT,
1582 DRM_MODE_CONNECTOR_DVII,
1583 &ddc_i2c,
1584 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1585 &hpd);
1586
1587 /* VGA - primary dac */
1588 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1589 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_CRT1_SUPPORT,
1593 1),
1594 ATOM_DEVICE_CRT1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 1,
1596 ATOM_DEVICE_CRT1_SUPPORT,
1597 DRM_MODE_CONNECTOR_VGA,
1598 &ddc_i2c,
1599 CONNECTOR_OBJECT_ID_VGA,
1600 &hpd);
1601 }
1602
1603 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1604 /* TV - tv dac */
1605 ddc_i2c.valid = false;
1606 hpd.hpd = RADEON_HPD_NONE;
1607 radeon_add_legacy_encoder(dev,
1608 radeon_get_encoder_enum(dev,
1609 ATOM_DEVICE_TV1_SUPPORT,
1610 2),
1611 ATOM_DEVICE_TV1_SUPPORT);
1612 radeon_add_legacy_connector(dev, 2,
1613 ATOM_DEVICE_TV1_SUPPORT,
1614 DRM_MODE_CONNECTOR_SVIDEO,
1615 &ddc_i2c,
1616 CONNECTOR_OBJECT_ID_SVIDEO,
1617 &hpd);
1618 }
1619 break;
1620 case CT_IBOOK:
1621 DRM_INFO("Connector Table: %d (ibook)\n",
1622 rdev->mode_info.connector_table);
1623 /* LVDS */
1624 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1625 hpd.hpd = RADEON_HPD_NONE;
1626 radeon_add_legacy_encoder(dev,
1627 radeon_get_encoder_enum(dev,
1628 ATOM_DEVICE_LCD1_SUPPORT,
1629 0),
1630 ATOM_DEVICE_LCD1_SUPPORT);
1631 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1632 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1633 CONNECTOR_OBJECT_ID_LVDS,
1634 &hpd);
1635 /* VGA - TV DAC */
1636 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1637 hpd.hpd = RADEON_HPD_NONE;
1638 radeon_add_legacy_encoder(dev,
1639 radeon_get_encoder_enum(dev,
1640 ATOM_DEVICE_CRT2_SUPPORT,
1641 2),
1642 ATOM_DEVICE_CRT2_SUPPORT);
1643 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1644 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1645 CONNECTOR_OBJECT_ID_VGA,
1646 &hpd);
1647 /* TV - TV DAC */
1648 ddc_i2c.valid = false;
1649 hpd.hpd = RADEON_HPD_NONE;
1650 radeon_add_legacy_encoder(dev,
1651 radeon_get_encoder_enum(dev,
1652 ATOM_DEVICE_TV1_SUPPORT,
1653 2),
1654 ATOM_DEVICE_TV1_SUPPORT);
1655 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1656 DRM_MODE_CONNECTOR_SVIDEO,
1657 &ddc_i2c,
1658 CONNECTOR_OBJECT_ID_SVIDEO,
1659 &hpd);
1660 break;
1661 case CT_POWERBOOK_EXTERNAL:
1662 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1663 rdev->mode_info.connector_table);
1664 /* LVDS */
1665 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1666 hpd.hpd = RADEON_HPD_NONE;
1667 radeon_add_legacy_encoder(dev,
1668 radeon_get_encoder_enum(dev,
1669 ATOM_DEVICE_LCD1_SUPPORT,
1670 0),
1671 ATOM_DEVICE_LCD1_SUPPORT);
1672 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1673 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1674 CONNECTOR_OBJECT_ID_LVDS,
1675 &hpd);
1676 /* DVI-I - primary dac, ext tmds */
1677 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1678 hpd.hpd = RADEON_HPD_2; /* ??? */
1679 radeon_add_legacy_encoder(dev,
1680 radeon_get_encoder_enum(dev,
1681 ATOM_DEVICE_DFP2_SUPPORT,
1682 0),
1683 ATOM_DEVICE_DFP2_SUPPORT);
1684 radeon_add_legacy_encoder(dev,
1685 radeon_get_encoder_enum(dev,
1686 ATOM_DEVICE_CRT1_SUPPORT,
1687 1),
1688 ATOM_DEVICE_CRT1_SUPPORT);
1689 radeon_add_legacy_connector(dev, 1,
1690 ATOM_DEVICE_DFP2_SUPPORT |
1691 ATOM_DEVICE_CRT1_SUPPORT,
1692 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1693 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1694 &hpd);
1695 /* TV - TV DAC */
1696 ddc_i2c.valid = false;
1697 hpd.hpd = RADEON_HPD_NONE;
1698 radeon_add_legacy_encoder(dev,
1699 radeon_get_encoder_enum(dev,
1700 ATOM_DEVICE_TV1_SUPPORT,
1701 2),
1702 ATOM_DEVICE_TV1_SUPPORT);
1703 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1704 DRM_MODE_CONNECTOR_SVIDEO,
1705 &ddc_i2c,
1706 CONNECTOR_OBJECT_ID_SVIDEO,
1707 &hpd);
1708 break;
1709 case CT_POWERBOOK_INTERNAL:
1710 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1711 rdev->mode_info.connector_table);
1712 /* LVDS */
1713 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1714 hpd.hpd = RADEON_HPD_NONE;
1715 radeon_add_legacy_encoder(dev,
1716 radeon_get_encoder_enum(dev,
1717 ATOM_DEVICE_LCD1_SUPPORT,
1718 0),
1719 ATOM_DEVICE_LCD1_SUPPORT);
1720 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1721 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1722 CONNECTOR_OBJECT_ID_LVDS,
1723 &hpd);
1724 /* DVI-I - primary dac, int tmds */
1725 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1726 hpd.hpd = RADEON_HPD_1; /* ??? */
1727 radeon_add_legacy_encoder(dev,
1728 radeon_get_encoder_enum(dev,
1729 ATOM_DEVICE_DFP1_SUPPORT,
1730 0),
1731 ATOM_DEVICE_DFP1_SUPPORT);
1732 radeon_add_legacy_encoder(dev,
1733 radeon_get_encoder_enum(dev,
1734 ATOM_DEVICE_CRT1_SUPPORT,
1735 1),
1736 ATOM_DEVICE_CRT1_SUPPORT);
1737 radeon_add_legacy_connector(dev, 1,
1738 ATOM_DEVICE_DFP1_SUPPORT |
1739 ATOM_DEVICE_CRT1_SUPPORT,
1740 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1741 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1742 &hpd);
1743 /* TV - TV DAC */
1744 ddc_i2c.valid = false;
1745 hpd.hpd = RADEON_HPD_NONE;
1746 radeon_add_legacy_encoder(dev,
1747 radeon_get_encoder_enum(dev,
1748 ATOM_DEVICE_TV1_SUPPORT,
1749 2),
1750 ATOM_DEVICE_TV1_SUPPORT);
1751 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1752 DRM_MODE_CONNECTOR_SVIDEO,
1753 &ddc_i2c,
1754 CONNECTOR_OBJECT_ID_SVIDEO,
1755 &hpd);
1756 break;
1757 case CT_POWERBOOK_VGA:
1758 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1759 rdev->mode_info.connector_table);
1760 /* LVDS */
1761 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1762 hpd.hpd = RADEON_HPD_NONE;
1763 radeon_add_legacy_encoder(dev,
1764 radeon_get_encoder_enum(dev,
1765 ATOM_DEVICE_LCD1_SUPPORT,
1766 0),
1767 ATOM_DEVICE_LCD1_SUPPORT);
1768 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1769 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1770 CONNECTOR_OBJECT_ID_LVDS,
1771 &hpd);
1772 /* VGA - primary dac */
1773 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1774 hpd.hpd = RADEON_HPD_NONE;
1775 radeon_add_legacy_encoder(dev,
1776 radeon_get_encoder_enum(dev,
1777 ATOM_DEVICE_CRT1_SUPPORT,
1778 1),
1779 ATOM_DEVICE_CRT1_SUPPORT);
1780 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1781 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1782 CONNECTOR_OBJECT_ID_VGA,
1783 &hpd);
1784 /* TV - TV DAC */
1785 ddc_i2c.valid = false;
1786 hpd.hpd = RADEON_HPD_NONE;
1787 radeon_add_legacy_encoder(dev,
1788 radeon_get_encoder_enum(dev,
1789 ATOM_DEVICE_TV1_SUPPORT,
1790 2),
1791 ATOM_DEVICE_TV1_SUPPORT);
1792 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1793 DRM_MODE_CONNECTOR_SVIDEO,
1794 &ddc_i2c,
1795 CONNECTOR_OBJECT_ID_SVIDEO,
1796 &hpd);
1797 break;
1798 case CT_MINI_EXTERNAL:
1799 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1800 rdev->mode_info.connector_table);
1801 /* DVI-I - tv dac, ext tmds */
1802 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1803 hpd.hpd = RADEON_HPD_2; /* ??? */
1804 radeon_add_legacy_encoder(dev,
1805 radeon_get_encoder_enum(dev,
1806 ATOM_DEVICE_DFP2_SUPPORT,
1807 0),
1808 ATOM_DEVICE_DFP2_SUPPORT);
1809 radeon_add_legacy_encoder(dev,
1810 radeon_get_encoder_enum(dev,
1811 ATOM_DEVICE_CRT2_SUPPORT,
1812 2),
1813 ATOM_DEVICE_CRT2_SUPPORT);
1814 radeon_add_legacy_connector(dev, 0,
1815 ATOM_DEVICE_DFP2_SUPPORT |
1816 ATOM_DEVICE_CRT2_SUPPORT,
1817 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1818 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1819 &hpd);
1820 /* TV - TV DAC */
1821 ddc_i2c.valid = false;
1822 hpd.hpd = RADEON_HPD_NONE;
1823 radeon_add_legacy_encoder(dev,
1824 radeon_get_encoder_enum(dev,
1825 ATOM_DEVICE_TV1_SUPPORT,
1826 2),
1827 ATOM_DEVICE_TV1_SUPPORT);
1828 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1829 DRM_MODE_CONNECTOR_SVIDEO,
1830 &ddc_i2c,
1831 CONNECTOR_OBJECT_ID_SVIDEO,
1832 &hpd);
1833 break;
1834 case CT_MINI_INTERNAL:
1835 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1836 rdev->mode_info.connector_table);
1837 /* DVI-I - tv dac, int tmds */
1838 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1839 hpd.hpd = RADEON_HPD_1; /* ??? */
1840 radeon_add_legacy_encoder(dev,
1841 radeon_get_encoder_enum(dev,
1842 ATOM_DEVICE_DFP1_SUPPORT,
1843 0),
1844 ATOM_DEVICE_DFP1_SUPPORT);
1845 radeon_add_legacy_encoder(dev,
1846 radeon_get_encoder_enum(dev,
1847 ATOM_DEVICE_CRT2_SUPPORT,
1848 2),
1849 ATOM_DEVICE_CRT2_SUPPORT);
1850 radeon_add_legacy_connector(dev, 0,
1851 ATOM_DEVICE_DFP1_SUPPORT |
1852 ATOM_DEVICE_CRT2_SUPPORT,
1853 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1854 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1855 &hpd);
1856 /* TV - TV DAC */
1857 ddc_i2c.valid = false;
1858 hpd.hpd = RADEON_HPD_NONE;
1859 radeon_add_legacy_encoder(dev,
1860 radeon_get_encoder_enum(dev,
1861 ATOM_DEVICE_TV1_SUPPORT,
1862 2),
1863 ATOM_DEVICE_TV1_SUPPORT);
1864 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1865 DRM_MODE_CONNECTOR_SVIDEO,
1866 &ddc_i2c,
1867 CONNECTOR_OBJECT_ID_SVIDEO,
1868 &hpd);
1869 break;
1870 case CT_IMAC_G5_ISIGHT:
1871 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1872 rdev->mode_info.connector_table);
1873 /* DVI-D - int tmds */
1874 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1875 hpd.hpd = RADEON_HPD_1; /* ??? */
1876 radeon_add_legacy_encoder(dev,
1877 radeon_get_encoder_enum(dev,
1878 ATOM_DEVICE_DFP1_SUPPORT,
1879 0),
1880 ATOM_DEVICE_DFP1_SUPPORT);
1881 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1882 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1883 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1884 &hpd);
1885 /* VGA - tv dac */
1886 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1887 hpd.hpd = RADEON_HPD_NONE;
1888 radeon_add_legacy_encoder(dev,
1889 radeon_get_encoder_enum(dev,
1890 ATOM_DEVICE_CRT2_SUPPORT,
1891 2),
1892 ATOM_DEVICE_CRT2_SUPPORT);
1893 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1894 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1895 CONNECTOR_OBJECT_ID_VGA,
1896 &hpd);
1897 /* TV - TV DAC */
1898 ddc_i2c.valid = false;
1899 hpd.hpd = RADEON_HPD_NONE;
1900 radeon_add_legacy_encoder(dev,
1901 radeon_get_encoder_enum(dev,
1902 ATOM_DEVICE_TV1_SUPPORT,
1903 2),
1904 ATOM_DEVICE_TV1_SUPPORT);
1905 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1906 DRM_MODE_CONNECTOR_SVIDEO,
1907 &ddc_i2c,
1908 CONNECTOR_OBJECT_ID_SVIDEO,
1909 &hpd);
1910 break;
1911 case CT_EMAC:
1912 DRM_INFO("Connector Table: %d (emac)\n",
1913 rdev->mode_info.connector_table);
1914 /* VGA - primary dac */
1915 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1916 hpd.hpd = RADEON_HPD_NONE;
1917 radeon_add_legacy_encoder(dev,
1918 radeon_get_encoder_enum(dev,
1919 ATOM_DEVICE_CRT1_SUPPORT,
1920 1),
1921 ATOM_DEVICE_CRT1_SUPPORT);
1922 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1923 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1924 CONNECTOR_OBJECT_ID_VGA,
1925 &hpd);
1926 /* VGA - tv dac */
1927 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1928 hpd.hpd = RADEON_HPD_NONE;
1929 radeon_add_legacy_encoder(dev,
1930 radeon_get_encoder_enum(dev,
1931 ATOM_DEVICE_CRT2_SUPPORT,
1932 2),
1933 ATOM_DEVICE_CRT2_SUPPORT);
1934 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1935 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1936 CONNECTOR_OBJECT_ID_VGA,
1937 &hpd);
1938 /* TV - TV DAC */
1939 ddc_i2c.valid = false;
1940 hpd.hpd = RADEON_HPD_NONE;
1941 radeon_add_legacy_encoder(dev,
1942 radeon_get_encoder_enum(dev,
1943 ATOM_DEVICE_TV1_SUPPORT,
1944 2),
1945 ATOM_DEVICE_TV1_SUPPORT);
1946 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1947 DRM_MODE_CONNECTOR_SVIDEO,
1948 &ddc_i2c,
1949 CONNECTOR_OBJECT_ID_SVIDEO,
1950 &hpd);
1951 break;
1952 case CT_RN50_POWER:
1953 DRM_INFO("Connector Table: %d (rn50-power)\n",
1954 rdev->mode_info.connector_table);
1955 /* VGA - primary dac */
1956 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1957 hpd.hpd = RADEON_HPD_NONE;
1958 radeon_add_legacy_encoder(dev,
1959 radeon_get_encoder_enum(dev,
1960 ATOM_DEVICE_CRT1_SUPPORT,
1961 1),
1962 ATOM_DEVICE_CRT1_SUPPORT);
1963 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1964 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1965 CONNECTOR_OBJECT_ID_VGA,
1966 &hpd);
1967 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1968 hpd.hpd = RADEON_HPD_NONE;
1969 radeon_add_legacy_encoder(dev,
1970 radeon_get_encoder_enum(dev,
1971 ATOM_DEVICE_CRT2_SUPPORT,
1972 2),
1973 ATOM_DEVICE_CRT2_SUPPORT);
1974 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1975 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1976 CONNECTOR_OBJECT_ID_VGA,
1977 &hpd);
1978 break;
1979 case CT_MAC_X800:
1980 DRM_INFO("Connector Table: %d (mac x800)\n",
1981 rdev->mode_info.connector_table);
1982 /* DVI - primary dac, internal tmds */
1983 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1984 hpd.hpd = RADEON_HPD_1; /* ??? */
1985 radeon_add_legacy_encoder(dev,
1986 radeon_get_encoder_enum(dev,
1987 ATOM_DEVICE_DFP1_SUPPORT,
1988 0),
1989 ATOM_DEVICE_DFP1_SUPPORT);
1990 radeon_add_legacy_encoder(dev,
1991 radeon_get_encoder_enum(dev,
1992 ATOM_DEVICE_CRT1_SUPPORT,
1993 1),
1994 ATOM_DEVICE_CRT1_SUPPORT);
1995 radeon_add_legacy_connector(dev, 0,
1996 ATOM_DEVICE_DFP1_SUPPORT |
1997 ATOM_DEVICE_CRT1_SUPPORT,
1998 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1999 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2000 &hpd);
2001 /* DVI - tv dac, dvo */
2002 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2003 hpd.hpd = RADEON_HPD_2; /* ??? */
2004 radeon_add_legacy_encoder(dev,
2005 radeon_get_encoder_enum(dev,
2006 ATOM_DEVICE_DFP2_SUPPORT,
2007 0),
2008 ATOM_DEVICE_DFP2_SUPPORT);
2009 radeon_add_legacy_encoder(dev,
2010 radeon_get_encoder_enum(dev,
2011 ATOM_DEVICE_CRT2_SUPPORT,
2012 2),
2013 ATOM_DEVICE_CRT2_SUPPORT);
2014 radeon_add_legacy_connector(dev, 1,
2015 ATOM_DEVICE_DFP2_SUPPORT |
2016 ATOM_DEVICE_CRT2_SUPPORT,
2017 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2018 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2019 &hpd);
2020 break;
2021 default:
2022 DRM_INFO("Connector table: %d (invalid)\n",
2023 rdev->mode_info.connector_table);
2024 return false;
2025 }
2026
2027 radeon_link_encoder_connector(dev);
2028
2029 return true;
2030 }
2031
2032 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2033 int bios_index,
2034 enum radeon_combios_connector
2035 *legacy_connector,
2036 struct radeon_i2c_bus_rec *ddc_i2c,
2037 struct radeon_hpd *hpd)
2038 {
2039
2040 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2041 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2042 if (dev->pdev->device == 0x515e &&
2043 dev->pdev->subsystem_vendor == 0x1014) {
2044 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2045 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2046 return false;
2047 }
2048
2049 /* X300 card with extra non-existent DVI port */
2050 if (dev->pdev->device == 0x5B60 &&
2051 dev->pdev->subsystem_vendor == 0x17af &&
2052 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2053 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2054 return false;
2055 }
2056
2057 return true;
2058 }
2059
2060 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2061 {
2062 /* Acer 5102 has non-existent TV port */
2063 if (dev->pdev->device == 0x5975 &&
2064 dev->pdev->subsystem_vendor == 0x1025 &&
2065 dev->pdev->subsystem_device == 0x009f)
2066 return false;
2067
2068 /* HP dc5750 has non-existent TV port */
2069 if (dev->pdev->device == 0x5974 &&
2070 dev->pdev->subsystem_vendor == 0x103c &&
2071 dev->pdev->subsystem_device == 0x280a)
2072 return false;
2073
2074 /* MSI S270 has non-existent TV port */
2075 if (dev->pdev->device == 0x5955 &&
2076 dev->pdev->subsystem_vendor == 0x1462 &&
2077 dev->pdev->subsystem_device == 0x0131)
2078 return false;
2079
2080 return true;
2081 }
2082
2083 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2084 {
2085 struct radeon_device *rdev = dev->dev_private;
2086 uint32_t ext_tmds_info;
2087
2088 if (rdev->flags & RADEON_IS_IGP) {
2089 if (is_dvi_d)
2090 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2091 else
2092 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2093 }
2094 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2095 if (ext_tmds_info) {
2096 uint8_t rev = RBIOS8(ext_tmds_info);
2097 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2098 if (rev >= 3) {
2099 if (is_dvi_d)
2100 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2101 else
2102 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2103 } else {
2104 if (flags & 1) {
2105 if (is_dvi_d)
2106 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2107 else
2108 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2109 }
2110 }
2111 }
2112 if (is_dvi_d)
2113 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2114 else
2115 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2116 }
2117
2118 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2119 {
2120 struct radeon_device *rdev = dev->dev_private;
2121 uint32_t conn_info, entry, devices;
2122 uint16_t tmp, connector_object_id;
2123 enum radeon_combios_ddc ddc_type;
2124 enum radeon_combios_connector connector;
2125 int i = 0;
2126 struct radeon_i2c_bus_rec ddc_i2c;
2127 struct radeon_hpd hpd;
2128
2129 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2130 if (conn_info) {
2131 for (i = 0; i < 4; i++) {
2132 entry = conn_info + 2 + i * 2;
2133
2134 if (!RBIOS16(entry))
2135 break;
2136
2137 tmp = RBIOS16(entry);
2138
2139 connector = (tmp >> 12) & 0xf;
2140
2141 ddc_type = (tmp >> 8) & 0xf;
2142 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2143
2144 switch (connector) {
2145 case CONNECTOR_PROPRIETARY_LEGACY:
2146 case CONNECTOR_DVI_I_LEGACY:
2147 case CONNECTOR_DVI_D_LEGACY:
2148 if ((tmp >> 4) & 0x1)
2149 hpd.hpd = RADEON_HPD_2;
2150 else
2151 hpd.hpd = RADEON_HPD_1;
2152 break;
2153 default:
2154 hpd.hpd = RADEON_HPD_NONE;
2155 break;
2156 }
2157
2158 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2159 &ddc_i2c, &hpd))
2160 continue;
2161
2162 switch (connector) {
2163 case CONNECTOR_PROPRIETARY_LEGACY:
2164 if ((tmp >> 4) & 0x1)
2165 devices = ATOM_DEVICE_DFP2_SUPPORT;
2166 else
2167 devices = ATOM_DEVICE_DFP1_SUPPORT;
2168 radeon_add_legacy_encoder(dev,
2169 radeon_get_encoder_enum
2170 (dev, devices, 0),
2171 devices);
2172 radeon_add_legacy_connector(dev, i, devices,
2173 legacy_connector_convert
2174 [connector],
2175 &ddc_i2c,
2176 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2177 &hpd);
2178 break;
2179 case CONNECTOR_CRT_LEGACY:
2180 if (tmp & 0x1) {
2181 devices = ATOM_DEVICE_CRT2_SUPPORT;
2182 radeon_add_legacy_encoder(dev,
2183 radeon_get_encoder_enum
2184 (dev,
2185 ATOM_DEVICE_CRT2_SUPPORT,
2186 2),
2187 ATOM_DEVICE_CRT2_SUPPORT);
2188 } else {
2189 devices = ATOM_DEVICE_CRT1_SUPPORT;
2190 radeon_add_legacy_encoder(dev,
2191 radeon_get_encoder_enum
2192 (dev,
2193 ATOM_DEVICE_CRT1_SUPPORT,
2194 1),
2195 ATOM_DEVICE_CRT1_SUPPORT);
2196 }
2197 radeon_add_legacy_connector(dev,
2198 i,
2199 devices,
2200 legacy_connector_convert
2201 [connector],
2202 &ddc_i2c,
2203 CONNECTOR_OBJECT_ID_VGA,
2204 &hpd);
2205 break;
2206 case CONNECTOR_DVI_I_LEGACY:
2207 devices = 0;
2208 if (tmp & 0x1) {
2209 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2210 radeon_add_legacy_encoder(dev,
2211 radeon_get_encoder_enum
2212 (dev,
2213 ATOM_DEVICE_CRT2_SUPPORT,
2214 2),
2215 ATOM_DEVICE_CRT2_SUPPORT);
2216 } else {
2217 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2218 radeon_add_legacy_encoder(dev,
2219 radeon_get_encoder_enum
2220 (dev,
2221 ATOM_DEVICE_CRT1_SUPPORT,
2222 1),
2223 ATOM_DEVICE_CRT1_SUPPORT);
2224 }
2225 if ((tmp >> 4) & 0x1) {
2226 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2227 radeon_add_legacy_encoder(dev,
2228 radeon_get_encoder_enum
2229 (dev,
2230 ATOM_DEVICE_DFP2_SUPPORT,
2231 0),
2232 ATOM_DEVICE_DFP2_SUPPORT);
2233 connector_object_id = combios_check_dl_dvi(dev, 0);
2234 } else {
2235 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2236 radeon_add_legacy_encoder(dev,
2237 radeon_get_encoder_enum
2238 (dev,
2239 ATOM_DEVICE_DFP1_SUPPORT,
2240 0),
2241 ATOM_DEVICE_DFP1_SUPPORT);
2242 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2243 }
2244 radeon_add_legacy_connector(dev,
2245 i,
2246 devices,
2247 legacy_connector_convert
2248 [connector],
2249 &ddc_i2c,
2250 connector_object_id,
2251 &hpd);
2252 break;
2253 case CONNECTOR_DVI_D_LEGACY:
2254 if ((tmp >> 4) & 0x1) {
2255 devices = ATOM_DEVICE_DFP2_SUPPORT;
2256 connector_object_id = combios_check_dl_dvi(dev, 1);
2257 } else {
2258 devices = ATOM_DEVICE_DFP1_SUPPORT;
2259 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2260 }
2261 radeon_add_legacy_encoder(dev,
2262 radeon_get_encoder_enum
2263 (dev, devices, 0),
2264 devices);
2265 radeon_add_legacy_connector(dev, i, devices,
2266 legacy_connector_convert
2267 [connector],
2268 &ddc_i2c,
2269 connector_object_id,
2270 &hpd);
2271 break;
2272 case CONNECTOR_CTV_LEGACY:
2273 case CONNECTOR_STV_LEGACY:
2274 radeon_add_legacy_encoder(dev,
2275 radeon_get_encoder_enum
2276 (dev,
2277 ATOM_DEVICE_TV1_SUPPORT,
2278 2),
2279 ATOM_DEVICE_TV1_SUPPORT);
2280 radeon_add_legacy_connector(dev, i,
2281 ATOM_DEVICE_TV1_SUPPORT,
2282 legacy_connector_convert
2283 [connector],
2284 &ddc_i2c,
2285 CONNECTOR_OBJECT_ID_SVIDEO,
2286 &hpd);
2287 break;
2288 default:
2289 DRM_ERROR("Unknown connector type: %d\n",
2290 connector);
2291 continue;
2292 }
2293
2294 }
2295 } else {
2296 uint16_t tmds_info =
2297 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2298 if (tmds_info) {
2299 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2300
2301 radeon_add_legacy_encoder(dev,
2302 radeon_get_encoder_enum(dev,
2303 ATOM_DEVICE_CRT1_SUPPORT,
2304 1),
2305 ATOM_DEVICE_CRT1_SUPPORT);
2306 radeon_add_legacy_encoder(dev,
2307 radeon_get_encoder_enum(dev,
2308 ATOM_DEVICE_DFP1_SUPPORT,
2309 0),
2310 ATOM_DEVICE_DFP1_SUPPORT);
2311
2312 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2313 hpd.hpd = RADEON_HPD_1;
2314 radeon_add_legacy_connector(dev,
2315 0,
2316 ATOM_DEVICE_CRT1_SUPPORT |
2317 ATOM_DEVICE_DFP1_SUPPORT,
2318 DRM_MODE_CONNECTOR_DVII,
2319 &ddc_i2c,
2320 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2321 &hpd);
2322 } else {
2323 uint16_t crt_info =
2324 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2325 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2326 if (crt_info) {
2327 radeon_add_legacy_encoder(dev,
2328 radeon_get_encoder_enum(dev,
2329 ATOM_DEVICE_CRT1_SUPPORT,
2330 1),
2331 ATOM_DEVICE_CRT1_SUPPORT);
2332 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2333 hpd.hpd = RADEON_HPD_NONE;
2334 radeon_add_legacy_connector(dev,
2335 0,
2336 ATOM_DEVICE_CRT1_SUPPORT,
2337 DRM_MODE_CONNECTOR_VGA,
2338 &ddc_i2c,
2339 CONNECTOR_OBJECT_ID_VGA,
2340 &hpd);
2341 } else {
2342 DRM_DEBUG_KMS("No connector info found\n");
2343 return false;
2344 }
2345 }
2346 }
2347
2348 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2349 uint16_t lcd_info =
2350 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2351 if (lcd_info) {
2352 uint16_t lcd_ddc_info =
2353 combios_get_table_offset(dev,
2354 COMBIOS_LCD_DDC_INFO_TABLE);
2355
2356 radeon_add_legacy_encoder(dev,
2357 radeon_get_encoder_enum(dev,
2358 ATOM_DEVICE_LCD1_SUPPORT,
2359 0),
2360 ATOM_DEVICE_LCD1_SUPPORT);
2361
2362 if (lcd_ddc_info) {
2363 ddc_type = RBIOS8(lcd_ddc_info + 2);
2364 switch (ddc_type) {
2365 case DDC_LCD:
2366 ddc_i2c =
2367 combios_setup_i2c_bus(rdev,
2368 DDC_LCD,
2369 RBIOS32(lcd_ddc_info + 3),
2370 RBIOS32(lcd_ddc_info + 7));
2371 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2372 break;
2373 case DDC_GPIO:
2374 ddc_i2c =
2375 combios_setup_i2c_bus(rdev,
2376 DDC_GPIO,
2377 RBIOS32(lcd_ddc_info + 3),
2378 RBIOS32(lcd_ddc_info + 7));
2379 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2380 break;
2381 default:
2382 ddc_i2c =
2383 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2384 break;
2385 }
2386 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2387 } else
2388 ddc_i2c.valid = false;
2389
2390 hpd.hpd = RADEON_HPD_NONE;
2391 radeon_add_legacy_connector(dev,
2392 5,
2393 ATOM_DEVICE_LCD1_SUPPORT,
2394 DRM_MODE_CONNECTOR_LVDS,
2395 &ddc_i2c,
2396 CONNECTOR_OBJECT_ID_LVDS,
2397 &hpd);
2398 }
2399 }
2400
2401 /* check TV table */
2402 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2403 uint32_t tv_info =
2404 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2405 if (tv_info) {
2406 if (RBIOS8(tv_info + 6) == 'T') {
2407 if (radeon_apply_legacy_tv_quirks(dev)) {
2408 hpd.hpd = RADEON_HPD_NONE;
2409 ddc_i2c.valid = false;
2410 radeon_add_legacy_encoder(dev,
2411 radeon_get_encoder_enum
2412 (dev,
2413 ATOM_DEVICE_TV1_SUPPORT,
2414 2),
2415 ATOM_DEVICE_TV1_SUPPORT);
2416 radeon_add_legacy_connector(dev, 6,
2417 ATOM_DEVICE_TV1_SUPPORT,
2418 DRM_MODE_CONNECTOR_SVIDEO,
2419 &ddc_i2c,
2420 CONNECTOR_OBJECT_ID_SVIDEO,
2421 &hpd);
2422 }
2423 }
2424 }
2425 }
2426
2427 radeon_link_encoder_connector(dev);
2428
2429 return true;
2430 }
2431
2432 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2433 {
2434 struct drm_device *dev = rdev->ddev;
2435 u16 offset, misc, misc2 = 0;
2436 u8 rev, blocks, tmp;
2437 int state_index = 0;
2438
2439 rdev->pm.default_power_state_index = -1;
2440
2441 if (rdev->flags & RADEON_IS_MOBILITY) {
2442 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2443 if (offset) {
2444 rev = RBIOS8(offset);
2445 blocks = RBIOS8(offset + 0x2);
2446 /* power mode 0 tends to be the only valid one */
2447 rdev->pm.power_state[state_index].num_clock_modes = 1;
2448 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2449 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2450 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2451 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2452 goto default_mode;
2453 rdev->pm.power_state[state_index].type =
2454 POWER_STATE_TYPE_BATTERY;
2455 misc = RBIOS16(offset + 0x5 + 0x0);
2456 if (rev > 4)
2457 misc2 = RBIOS16(offset + 0x5 + 0xe);
2458 rdev->pm.power_state[state_index].misc = misc;
2459 rdev->pm.power_state[state_index].misc2 = misc2;
2460 if (misc & 0x4) {
2461 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2462 if (misc & 0x8)
2463 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2464 true;
2465 else
2466 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2467 false;
2468 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2469 if (rev < 6) {
2470 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2471 RBIOS16(offset + 0x5 + 0xb) * 4;
2472 tmp = RBIOS8(offset + 0x5 + 0xd);
2473 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2474 } else {
2475 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2476 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2477 if (entries && voltage_table_offset) {
2478 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2479 RBIOS16(voltage_table_offset) * 4;
2480 tmp = RBIOS8(voltage_table_offset + 0x2);
2481 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2482 } else
2483 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2484 }
2485 switch ((misc2 & 0x700) >> 8) {
2486 case 0:
2487 default:
2488 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2489 break;
2490 case 1:
2491 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2492 break;
2493 case 2:
2494 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2495 break;
2496 case 3:
2497 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2498 break;
2499 case 4:
2500 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2501 break;
2502 }
2503 } else
2504 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2505 if (rev > 6)
2506 rdev->pm.power_state[state_index].pcie_lanes =
2507 RBIOS8(offset + 0x5 + 0x10);
2508 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2509 state_index++;
2510 } else {
2511 }
2512 } else {
2513 }
2514
2515 default_mode:
2516 /* add the default mode */
2517 rdev->pm.power_state[state_index].type =
2518 POWER_STATE_TYPE_DEFAULT;
2519 rdev->pm.power_state[state_index].num_clock_modes = 1;
2520 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2521 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2522 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2523 if ((state_index > 0) &&
2524 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2525 rdev->pm.power_state[state_index].clock_info[0].voltage =
2526 rdev->pm.power_state[0].clock_info[0].voltage;
2527 else
2528 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2529 rdev->pm.power_state[state_index].pcie_lanes = 16;
2530 rdev->pm.power_state[state_index].flags = 0;
2531 rdev->pm.default_power_state_index = state_index;
2532 rdev->pm.num_power_states = state_index + 1;
2533
2534 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2535 rdev->pm.current_clock_mode_index = 0;
2536 }
2537
2538 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2539 {
2540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2541 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2542
2543 if (!tmds)
2544 return;
2545
2546 switch (tmds->dvo_chip) {
2547 case DVO_SIL164:
2548 /* sil 164 */
2549 radeon_i2c_put_byte(tmds->i2c_bus,
2550 tmds->slave_addr,
2551 0x08, 0x30);
2552 radeon_i2c_put_byte(tmds->i2c_bus,
2553 tmds->slave_addr,
2554 0x09, 0x00);
2555 radeon_i2c_put_byte(tmds->i2c_bus,
2556 tmds->slave_addr,
2557 0x0a, 0x90);
2558 radeon_i2c_put_byte(tmds->i2c_bus,
2559 tmds->slave_addr,
2560 0x0c, 0x89);
2561 radeon_i2c_put_byte(tmds->i2c_bus,
2562 tmds->slave_addr,
2563 0x08, 0x3b);
2564 break;
2565 case DVO_SIL1178:
2566 /* sil 1178 - untested */
2567 /*
2568 * 0x0f, 0x44
2569 * 0x0f, 0x4c
2570 * 0x0e, 0x01
2571 * 0x0a, 0x80
2572 * 0x09, 0x30
2573 * 0x0c, 0xc9
2574 * 0x0d, 0x70
2575 * 0x08, 0x32
2576 * 0x08, 0x33
2577 */
2578 break;
2579 default:
2580 break;
2581 }
2582
2583 }
2584
2585 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2586 {
2587 struct drm_device *dev = encoder->dev;
2588 struct radeon_device *rdev = dev->dev_private;
2589 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2590 uint16_t offset;
2591 uint8_t blocks, slave_addr, rev;
2592 uint32_t index, id;
2593 uint32_t reg, val, and_mask, or_mask;
2594 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2595
2596 if (!tmds)
2597 return false;
2598
2599 if (rdev->flags & RADEON_IS_IGP) {
2600 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2601 rev = RBIOS8(offset);
2602 if (offset) {
2603 rev = RBIOS8(offset);
2604 if (rev > 1) {
2605 blocks = RBIOS8(offset + 3);
2606 index = offset + 4;
2607 while (blocks > 0) {
2608 id = RBIOS16(index);
2609 index += 2;
2610 switch (id >> 13) {
2611 case 0:
2612 reg = (id & 0x1fff) * 4;
2613 val = RBIOS32(index);
2614 index += 4;
2615 WREG32(reg, val);
2616 break;
2617 case 2:
2618 reg = (id & 0x1fff) * 4;
2619 and_mask = RBIOS32(index);
2620 index += 4;
2621 or_mask = RBIOS32(index);
2622 index += 4;
2623 val = RREG32(reg);
2624 val = (val & and_mask) | or_mask;
2625 WREG32(reg, val);
2626 break;
2627 case 3:
2628 val = RBIOS16(index);
2629 index += 2;
2630 udelay(val);
2631 break;
2632 case 4:
2633 val = RBIOS16(index);
2634 index += 2;
2635 udelay(val * 1000);
2636 break;
2637 case 6:
2638 slave_addr = id & 0xff;
2639 slave_addr >>= 1; /* 7 bit addressing */
2640 index++;
2641 reg = RBIOS8(index);
2642 index++;
2643 val = RBIOS8(index);
2644 index++;
2645 radeon_i2c_put_byte(tmds->i2c_bus,
2646 slave_addr,
2647 reg, val);
2648 break;
2649 default:
2650 DRM_ERROR("Unknown id %d\n", id >> 13);
2651 break;
2652 }
2653 blocks--;
2654 }
2655 return true;
2656 }
2657 }
2658 } else {
2659 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2660 if (offset) {
2661 index = offset + 10;
2662 id = RBIOS16(index);
2663 while (id != 0xffff) {
2664 index += 2;
2665 switch (id >> 13) {
2666 case 0:
2667 reg = (id & 0x1fff) * 4;
2668 val = RBIOS32(index);
2669 WREG32(reg, val);
2670 break;
2671 case 2:
2672 reg = (id & 0x1fff) * 4;
2673 and_mask = RBIOS32(index);
2674 index += 4;
2675 or_mask = RBIOS32(index);
2676 index += 4;
2677 val = RREG32(reg);
2678 val = (val & and_mask) | or_mask;
2679 WREG32(reg, val);
2680 break;
2681 case 4:
2682 val = RBIOS16(index);
2683 index += 2;
2684 udelay(val);
2685 break;
2686 case 5:
2687 reg = id & 0x1fff;
2688 and_mask = RBIOS32(index);
2689 index += 4;
2690 or_mask = RBIOS32(index);
2691 index += 4;
2692 val = RREG32_PLL(reg);
2693 val = (val & and_mask) | or_mask;
2694 WREG32_PLL(reg, val);
2695 break;
2696 case 6:
2697 reg = id & 0x1fff;
2698 val = RBIOS8(index);
2699 index += 1;
2700 radeon_i2c_put_byte(tmds->i2c_bus,
2701 tmds->slave_addr,
2702 reg, val);
2703 break;
2704 default:
2705 DRM_ERROR("Unknown id %d\n", id >> 13);
2706 break;
2707 }
2708 id = RBIOS16(index);
2709 }
2710 return true;
2711 }
2712 }
2713 return false;
2714 }
2715
2716 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2717 {
2718 struct radeon_device *rdev = dev->dev_private;
2719
2720 if (offset) {
2721 while (RBIOS16(offset)) {
2722 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2723 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2724 uint32_t val, and_mask, or_mask;
2725 uint32_t tmp;
2726
2727 offset += 2;
2728 switch (cmd) {
2729 case 0:
2730 val = RBIOS32(offset);
2731 offset += 4;
2732 WREG32(addr, val);
2733 break;
2734 case 1:
2735 val = RBIOS32(offset);
2736 offset += 4;
2737 WREG32(addr, val);
2738 break;
2739 case 2:
2740 and_mask = RBIOS32(offset);
2741 offset += 4;
2742 or_mask = RBIOS32(offset);
2743 offset += 4;
2744 tmp = RREG32(addr);
2745 tmp &= and_mask;
2746 tmp |= or_mask;
2747 WREG32(addr, tmp);
2748 break;
2749 case 3:
2750 and_mask = RBIOS32(offset);
2751 offset += 4;
2752 or_mask = RBIOS32(offset);
2753 offset += 4;
2754 tmp = RREG32(addr);
2755 tmp &= and_mask;
2756 tmp |= or_mask;
2757 WREG32(addr, tmp);
2758 break;
2759 case 4:
2760 val = RBIOS16(offset);
2761 offset += 2;
2762 udelay(val);
2763 break;
2764 case 5:
2765 val = RBIOS16(offset);
2766 offset += 2;
2767 switch (addr) {
2768 case 8:
2769 while (val--) {
2770 if (!
2771 (RREG32_PLL
2772 (RADEON_CLK_PWRMGT_CNTL) &
2773 RADEON_MC_BUSY))
2774 break;
2775 }
2776 break;
2777 case 9:
2778 while (val--) {
2779 if ((RREG32(RADEON_MC_STATUS) &
2780 RADEON_MC_IDLE))
2781 break;
2782 }
2783 break;
2784 default:
2785 break;
2786 }
2787 break;
2788 default:
2789 break;
2790 }
2791 }
2792 }
2793 }
2794
2795 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2796 {
2797 struct radeon_device *rdev = dev->dev_private;
2798
2799 if (offset) {
2800 while (RBIOS8(offset)) {
2801 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2802 uint8_t addr = (RBIOS8(offset) & 0x3f);
2803 uint32_t val, shift, tmp;
2804 uint32_t and_mask, or_mask;
2805
2806 offset++;
2807 switch (cmd) {
2808 case 0:
2809 val = RBIOS32(offset);
2810 offset += 4;
2811 WREG32_PLL(addr, val);
2812 break;
2813 case 1:
2814 shift = RBIOS8(offset) * 8;
2815 offset++;
2816 and_mask = RBIOS8(offset) << shift;
2817 and_mask |= ~(0xff << shift);
2818 offset++;
2819 or_mask = RBIOS8(offset) << shift;
2820 offset++;
2821 tmp = RREG32_PLL(addr);
2822 tmp &= and_mask;
2823 tmp |= or_mask;
2824 WREG32_PLL(addr, tmp);
2825 break;
2826 case 2:
2827 case 3:
2828 tmp = 1000;
2829 switch (addr) {
2830 case 1:
2831 udelay(150);
2832 break;
2833 case 2:
2834 udelay(1000);
2835 break;
2836 case 3:
2837 while (tmp--) {
2838 if (!
2839 (RREG32_PLL
2840 (RADEON_CLK_PWRMGT_CNTL) &
2841 RADEON_MC_BUSY))
2842 break;
2843 }
2844 break;
2845 case 4:
2846 while (tmp--) {
2847 if (RREG32_PLL
2848 (RADEON_CLK_PWRMGT_CNTL) &
2849 RADEON_DLL_READY)
2850 break;
2851 }
2852 break;
2853 case 5:
2854 tmp =
2855 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2856 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2857 WREG32_PLL
2858 (RADEON_CLK_PWRMGT_CNTL,
2859 tmp &
2860 ~RADEON_CG_NO1_DEBUG_0);
2861 udelay(10000);
2862 }
2863 break;
2864 default:
2865 break;
2866 }
2867 break;
2868 default:
2869 break;
2870 }
2871 }
2872 }
2873 }
2874
2875 static void combios_parse_ram_reset_table(struct drm_device *dev,
2876 uint16_t offset)
2877 {
2878 struct radeon_device *rdev = dev->dev_private;
2879 uint32_t tmp;
2880
2881 if (offset) {
2882 uint8_t val = RBIOS8(offset);
2883 while (val != 0xff) {
2884 offset++;
2885
2886 if (val == 0x0f) {
2887 uint32_t channel_complete_mask;
2888
2889 if (ASIC_IS_R300(rdev))
2890 channel_complete_mask =
2891 R300_MEM_PWRUP_COMPLETE;
2892 else
2893 channel_complete_mask =
2894 RADEON_MEM_PWRUP_COMPLETE;
2895 tmp = 20000;
2896 while (tmp--) {
2897 if ((RREG32(RADEON_MEM_STR_CNTL) &
2898 channel_complete_mask) ==
2899 channel_complete_mask)
2900 break;
2901 }
2902 } else {
2903 uint32_t or_mask = RBIOS16(offset);
2904 offset += 2;
2905
2906 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2907 tmp &= RADEON_SDRAM_MODE_MASK;
2908 tmp |= or_mask;
2909 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2910
2911 or_mask = val << 24;
2912 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2913 tmp &= RADEON_B3MEM_RESET_MASK;
2914 tmp |= or_mask;
2915 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2916 }
2917 val = RBIOS8(offset);
2918 }
2919 }
2920 }
2921
2922 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2923 int mem_addr_mapping)
2924 {
2925 struct radeon_device *rdev = dev->dev_private;
2926 uint32_t mem_cntl;
2927 uint32_t mem_size;
2928 uint32_t addr = 0;
2929
2930 mem_cntl = RREG32(RADEON_MEM_CNTL);
2931 if (mem_cntl & RV100_HALF_MODE)
2932 ram /= 2;
2933 mem_size = ram;
2934 mem_cntl &= ~(0xff << 8);
2935 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2936 WREG32(RADEON_MEM_CNTL, mem_cntl);
2937 RREG32(RADEON_MEM_CNTL);
2938
2939 /* sdram reset ? */
2940
2941 /* something like this???? */
2942 while (ram--) {
2943 addr = ram * 1024 * 1024;
2944 /* write to each page */
2945 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2946 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2947 /* read back and verify */
2948 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2949 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2950 return 0;
2951 }
2952
2953 return mem_size;
2954 }
2955
2956 static void combios_write_ram_size(struct drm_device *dev)
2957 {
2958 struct radeon_device *rdev = dev->dev_private;
2959 uint8_t rev;
2960 uint16_t offset;
2961 uint32_t mem_size = 0;
2962 uint32_t mem_cntl = 0;
2963
2964 /* should do something smarter here I guess... */
2965 if (rdev->flags & RADEON_IS_IGP)
2966 return;
2967
2968 /* first check detected mem table */
2969 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2970 if (offset) {
2971 rev = RBIOS8(offset);
2972 if (rev < 3) {
2973 mem_cntl = RBIOS32(offset + 1);
2974 mem_size = RBIOS16(offset + 5);
2975 if ((rdev->family < CHIP_R200) &&
2976 !ASIC_IS_RN50(rdev))
2977 WREG32(RADEON_MEM_CNTL, mem_cntl);
2978 }
2979 }
2980
2981 if (!mem_size) {
2982 offset =
2983 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2984 if (offset) {
2985 rev = RBIOS8(offset - 1);
2986 if (rev < 1) {
2987 if ((rdev->family < CHIP_R200)
2988 && !ASIC_IS_RN50(rdev)) {
2989 int ram = 0;
2990 int mem_addr_mapping = 0;
2991
2992 while (RBIOS8(offset)) {
2993 ram = RBIOS8(offset);
2994 mem_addr_mapping =
2995 RBIOS8(offset + 1);
2996 if (mem_addr_mapping != 0x25)
2997 ram *= 2;
2998 mem_size =
2999 combios_detect_ram(dev, ram,
3000 mem_addr_mapping);
3001 if (mem_size)
3002 break;
3003 offset += 2;
3004 }
3005 } else
3006 mem_size = RBIOS8(offset);
3007 } else {
3008 mem_size = RBIOS8(offset);
3009 mem_size *= 2; /* convert to MB */
3010 }
3011 }
3012 }
3013
3014 mem_size *= (1024 * 1024); /* convert to bytes */
3015 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3016 }
3017
3018 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3019 {
3020 uint16_t dyn_clk_info =
3021 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3022
3023 if (dyn_clk_info)
3024 combios_parse_pll_table(dev, dyn_clk_info);
3025 }
3026
3027 void radeon_combios_asic_init(struct drm_device *dev)
3028 {
3029 struct radeon_device *rdev = dev->dev_private;
3030 uint16_t table;
3031
3032 /* port hardcoded mac stuff from radeonfb */
3033 if (rdev->bios == NULL)
3034 return;
3035
3036 /* ASIC INIT 1 */
3037 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3038 if (table)
3039 combios_parse_mmio_table(dev, table);
3040
3041 /* PLL INIT */
3042 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3043 if (table)
3044 combios_parse_pll_table(dev, table);
3045
3046 /* ASIC INIT 2 */
3047 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3048 if (table)
3049 combios_parse_mmio_table(dev, table);
3050
3051 if (!(rdev->flags & RADEON_IS_IGP)) {
3052 /* ASIC INIT 4 */
3053 table =
3054 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3055 if (table)
3056 combios_parse_mmio_table(dev, table);
3057
3058 /* RAM RESET */
3059 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3060 if (table)
3061 combios_parse_ram_reset_table(dev, table);
3062
3063 /* ASIC INIT 3 */
3064 table =
3065 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3066 if (table)
3067 combios_parse_mmio_table(dev, table);
3068
3069 /* write CONFIG_MEMSIZE */
3070 combios_write_ram_size(dev);
3071 }
3072
3073 /* quirk for rs4xx HP nx6125 laptop to make it resume
3074 * - it hangs on resume inside the dynclk 1 table.
3075 */
3076 if (rdev->family == CHIP_RS480 &&
3077 rdev->pdev->subsystem_vendor == 0x103c &&
3078 rdev->pdev->subsystem_device == 0x308b)
3079 return;
3080
3081 /* quirk for rs4xx HP dv5000 laptop to make it resume
3082 * - it hangs on resume inside the dynclk 1 table.
3083 */
3084 if (rdev->family == CHIP_RS480 &&
3085 rdev->pdev->subsystem_vendor == 0x103c &&
3086 rdev->pdev->subsystem_device == 0x30a4)
3087 return;
3088
3089 /* DYN CLK 1 */
3090 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3091 if (table)
3092 combios_parse_pll_table(dev, table);
3093
3094 }
3095
3096 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3097 {
3098 struct radeon_device *rdev = dev->dev_private;
3099 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3100
3101 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3102 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3103 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3104
3105 /* let the bios control the backlight */
3106 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3107
3108 /* tell the bios not to handle mode switching */
3109 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3110 RADEON_ACC_MODE_CHANGE);
3111
3112 /* tell the bios a driver is loaded */
3113 bios_7_scratch |= RADEON_DRV_LOADED;
3114
3115 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3116 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3117 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3118 }
3119
3120 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3121 {
3122 struct drm_device *dev = encoder->dev;
3123 struct radeon_device *rdev = dev->dev_private;
3124 uint32_t bios_6_scratch;
3125
3126 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3127
3128 if (lock)
3129 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3130 else
3131 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3132
3133 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3134 }
3135
3136 void
3137 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3138 struct drm_encoder *encoder,
3139 bool connected)
3140 {
3141 struct drm_device *dev = connector->dev;
3142 struct radeon_device *rdev = dev->dev_private;
3143 struct radeon_connector *radeon_connector =
3144 to_radeon_connector(connector);
3145 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3146 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3147 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3148
3149 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3150 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3151 if (connected) {
3152 DRM_DEBUG_KMS("TV1 connected\n");
3153 /* fix me */
3154 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3155 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3156 bios_5_scratch |= RADEON_TV1_ON;
3157 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3158 } else {
3159 DRM_DEBUG_KMS("TV1 disconnected\n");
3160 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3161 bios_5_scratch &= ~RADEON_TV1_ON;
3162 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3163 }
3164 }
3165 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3166 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3167 if (connected) {
3168 DRM_DEBUG_KMS("LCD1 connected\n");
3169 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3170 bios_5_scratch |= RADEON_LCD1_ON;
3171 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3172 } else {
3173 DRM_DEBUG_KMS("LCD1 disconnected\n");
3174 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3175 bios_5_scratch &= ~RADEON_LCD1_ON;
3176 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3177 }
3178 }
3179 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3180 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3181 if (connected) {
3182 DRM_DEBUG_KMS("CRT1 connected\n");
3183 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3184 bios_5_scratch |= RADEON_CRT1_ON;
3185 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3186 } else {
3187 DRM_DEBUG_KMS("CRT1 disconnected\n");
3188 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3189 bios_5_scratch &= ~RADEON_CRT1_ON;
3190 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3191 }
3192 }
3193 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3194 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3195 if (connected) {
3196 DRM_DEBUG_KMS("CRT2 connected\n");
3197 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3198 bios_5_scratch |= RADEON_CRT2_ON;
3199 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3200 } else {
3201 DRM_DEBUG_KMS("CRT2 disconnected\n");
3202 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3203 bios_5_scratch &= ~RADEON_CRT2_ON;
3204 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3205 }
3206 }
3207 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3208 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3209 if (connected) {
3210 DRM_DEBUG_KMS("DFP1 connected\n");
3211 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3212 bios_5_scratch |= RADEON_DFP1_ON;
3213 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3214 } else {
3215 DRM_DEBUG_KMS("DFP1 disconnected\n");
3216 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3217 bios_5_scratch &= ~RADEON_DFP1_ON;
3218 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3219 }
3220 }
3221 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3222 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3223 if (connected) {
3224 DRM_DEBUG_KMS("DFP2 connected\n");
3225 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3226 bios_5_scratch |= RADEON_DFP2_ON;
3227 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3228 } else {
3229 DRM_DEBUG_KMS("DFP2 disconnected\n");
3230 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3231 bios_5_scratch &= ~RADEON_DFP2_ON;
3232 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3233 }
3234 }
3235 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3236 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3237 }
3238
3239 void
3240 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3241 {
3242 struct drm_device *dev = encoder->dev;
3243 struct radeon_device *rdev = dev->dev_private;
3244 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3245 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3246
3247 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3248 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3249 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3250 }
3251 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3252 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3253 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3254 }
3255 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3256 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3257 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3258 }
3259 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3260 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3261 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3262 }
3263 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3264 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3265 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3266 }
3267 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3268 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3269 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3270 }
3271 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3272 }
3273
3274 void
3275 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3276 {
3277 struct drm_device *dev = encoder->dev;
3278 struct radeon_device *rdev = dev->dev_private;
3279 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3280 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3281
3282 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3283 if (on)
3284 bios_6_scratch |= RADEON_TV_DPMS_ON;
3285 else
3286 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3287 }
3288 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3289 if (on)
3290 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3291 else
3292 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3293 }
3294 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3295 if (on)
3296 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3297 else
3298 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3299 }
3300 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3301 if (on)
3302 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3303 else
3304 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3305 }
3306 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3307 }
Tomato firmware and modifications.