2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
,
52 struct radeon_router
*router
);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
57 uint32_t supported_device
);
59 union atom_supported_devices
{
60 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
65 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
68 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
69 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
70 struct radeon_i2c_bus_rec i2c
;
71 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
72 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 uint16_t data_offset
, size
;
76 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
79 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
82 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
85 for (i
= 0; i
< num_indices
; i
++) {
86 gpio
= &i2c_info
->asGPIO_Info
[i
];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev
)) {
91 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
92 (gpio
->sucI2cId
.ucAccess
== 0)) {
93 gpio
->sucI2cId
.ucAccess
= 0x97;
94 gpio
->ucDataMaskShift
= 8;
95 gpio
->ucDataEnShift
= 8;
96 gpio
->ucDataY_Shift
= 8;
97 gpio
->ucDataA_Shift
= 8;
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev
)) {
104 (gpio
->usClkMaskRegisterIndex
== 0x1fda) &&
105 (gpio
->sucI2cId
.ucAccess
== 0x94))
106 gpio
->sucI2cId
.ucAccess
= 0x14;
109 if (gpio
->sucI2cId
.ucAccess
== id
) {
110 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
111 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
112 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
113 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
114 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
115 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
116 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
117 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
118 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
119 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
120 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
121 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
122 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
123 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
124 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
125 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
127 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
128 i2c
.hw_capable
= true;
130 i2c
.hw_capable
= false;
132 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
137 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
139 if (i2c
.mask_clk_reg
)
149 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
151 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
152 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
153 struct radeon_i2c_bus_rec i2c
;
154 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
155 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
156 uint16_t data_offset
, size
;
160 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
162 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
163 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
165 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
168 for (i
= 0; i
< num_indices
; i
++) {
169 gpio
= &i2c_info
->asGPIO_Info
[i
];
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev
)) {
175 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
176 (gpio
->sucI2cId
.ucAccess
== 0)) {
177 gpio
->sucI2cId
.ucAccess
= 0x97;
178 gpio
->ucDataMaskShift
= 8;
179 gpio
->ucDataEnShift
= 8;
180 gpio
->ucDataY_Shift
= 8;
181 gpio
->ucDataA_Shift
= 8;
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev
)) {
188 (gpio
->usClkMaskRegisterIndex
== 0x1fda) &&
189 (gpio
->sucI2cId
.ucAccess
== 0x94))
190 gpio
->sucI2cId
.ucAccess
= 0x14;
193 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
194 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
195 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
196 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
197 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
198 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
199 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
200 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
201 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
202 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
203 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
204 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
205 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
206 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
207 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
208 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
210 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
211 i2c
.hw_capable
= true;
213 i2c
.hw_capable
= false;
215 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
220 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
222 if (i2c
.mask_clk_reg
) {
224 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
225 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
231 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
234 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
235 struct radeon_gpio_rec gpio
;
236 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
237 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
238 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
239 u16 data_offset
, size
;
242 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
245 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
246 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
248 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
251 for (i
= 0; i
< num_indices
; i
++) {
252 pin
= &gpio_info
->asGPIO_Pin
[i
];
253 if (id
== pin
->ucGPIO_ID
) {
254 gpio
.id
= pin
->ucGPIO_ID
;
255 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
256 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
266 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
267 struct radeon_gpio_rec
*gpio
)
269 struct radeon_hpd hpd
;
272 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
274 if (ASIC_IS_DCE4(rdev
))
275 reg
= EVERGREEN_DC_GPIO_HPD_A
;
277 reg
= AVIVO_DC_GPIO_HPD_A
;
280 if (gpio
->reg
== reg
) {
283 hpd
.hpd
= RADEON_HPD_1
;
286 hpd
.hpd
= RADEON_HPD_2
;
289 hpd
.hpd
= RADEON_HPD_3
;
292 hpd
.hpd
= RADEON_HPD_4
;
295 hpd
.hpd
= RADEON_HPD_5
;
298 hpd
.hpd
= RADEON_HPD_6
;
301 hpd
.hpd
= RADEON_HPD_NONE
;
305 hpd
.hpd
= RADEON_HPD_NONE
;
309 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
310 uint32_t supported_device
,
312 struct radeon_i2c_bus_rec
*i2c_bus
,
314 struct radeon_hpd
*hpd
)
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev
->pdev
->device
== 0x791e) &&
319 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
320 (dev
->pdev
->subsystem_device
== 0x826d)) {
321 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
322 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
323 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev
->pdev
->device
== 0x7941) &&
328 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
329 (dev
->pdev
->subsystem_device
== 0x7941)) {
330 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
331 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
332 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev
->pdev
->device
== 0x796e) &&
337 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
338 (dev
->pdev
->subsystem_device
== 0x7302)) {
339 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
340 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev
->pdev
->device
== 0x7941) &&
346 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
347 (dev
->pdev
->subsystem_device
== 0x2412)) {
348 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev
->pdev
->device
== 0x5653) &&
354 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
355 (dev
->pdev
->subsystem_device
== 0x0291)) {
356 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
357 i2c_bus
->valid
= false;
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev
->pdev
->device
== 0x7146) &&
364 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
365 (dev
->pdev
->subsystem_device
== 0x2058)) {
366 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev
->pdev
->device
== 0x7142) &&
372 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
373 (dev
->pdev
->subsystem_device
== 0x2134)) {
374 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
380 if ((dev
->pdev
->device
== 0x71C5) &&
381 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
382 (dev
->pdev
->subsystem_device
== 0x0080)) {
383 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
384 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
386 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
390 /* mac rv630, rv730, others */
391 if ((supported_device
== ATOM_DEVICE_TV1_SUPPORT
) &&
392 (*connector_type
== DRM_MODE_CONNECTOR_DVII
)) {
393 *connector_type
= DRM_MODE_CONNECTOR_9PinDIN
;
394 *line_mux
= CONNECTOR_7PIN_DIN_ENUM_ID1
;
397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev
->pdev
->device
== 0x9598) &&
399 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
400 (dev
->pdev
->subsystem_device
== 0x01da)) {
401 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
402 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev
->pdev
->device
== 0x9598) &&
408 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
409 (dev
->pdev
->subsystem_device
== 0x01e4)) {
410 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
411 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev
->pdev
->device
== 0x95C5) &&
417 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
418 (dev
->pdev
->subsystem_device
== 0x01e2)) {
419 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
420 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
427 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
428 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
429 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
434 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
443 if ((dev
->pdev
->device
== 0x95c4) &&
444 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
445 (dev
->pdev
->subsystem_device
== 0x013c)) {
446 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
447 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
448 /* actually it's a DVI-D port not DVI-I */
449 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
457 if ((dev
->pdev
->device
== 0x9498) &&
458 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
459 (dev
->pdev
->subsystem_device
== 0x2452)) {
460 struct radeon_device
*rdev
= dev
->dev_private
;
461 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
466 const int supported_devices_connector_convert
[] = {
467 DRM_MODE_CONNECTOR_Unknown
,
468 DRM_MODE_CONNECTOR_VGA
,
469 DRM_MODE_CONNECTOR_DVII
,
470 DRM_MODE_CONNECTOR_DVID
,
471 DRM_MODE_CONNECTOR_DVIA
,
472 DRM_MODE_CONNECTOR_SVIDEO
,
473 DRM_MODE_CONNECTOR_Composite
,
474 DRM_MODE_CONNECTOR_LVDS
,
475 DRM_MODE_CONNECTOR_Unknown
,
476 DRM_MODE_CONNECTOR_Unknown
,
477 DRM_MODE_CONNECTOR_HDMIA
,
478 DRM_MODE_CONNECTOR_HDMIB
,
479 DRM_MODE_CONNECTOR_Unknown
,
480 DRM_MODE_CONNECTOR_Unknown
,
481 DRM_MODE_CONNECTOR_9PinDIN
,
482 DRM_MODE_CONNECTOR_DisplayPort
485 const uint16_t supported_devices_connector_object_id_convert
[] = {
486 CONNECTOR_OBJECT_ID_NONE
,
487 CONNECTOR_OBJECT_ID_VGA
,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE
,
492 CONNECTOR_OBJECT_ID_SVIDEO
,
493 CONNECTOR_OBJECT_ID_LVDS
,
494 CONNECTOR_OBJECT_ID_9PIN_DIN
,
495 CONNECTOR_OBJECT_ID_9PIN_DIN
,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
499 CONNECTOR_OBJECT_ID_SVIDEO
502 const int object_connector_convert
[] = {
503 DRM_MODE_CONNECTOR_Unknown
,
504 DRM_MODE_CONNECTOR_DVII
,
505 DRM_MODE_CONNECTOR_DVII
,
506 DRM_MODE_CONNECTOR_DVID
,
507 DRM_MODE_CONNECTOR_DVID
,
508 DRM_MODE_CONNECTOR_VGA
,
509 DRM_MODE_CONNECTOR_Composite
,
510 DRM_MODE_CONNECTOR_SVIDEO
,
511 DRM_MODE_CONNECTOR_Unknown
,
512 DRM_MODE_CONNECTOR_Unknown
,
513 DRM_MODE_CONNECTOR_9PinDIN
,
514 DRM_MODE_CONNECTOR_Unknown
,
515 DRM_MODE_CONNECTOR_HDMIA
,
516 DRM_MODE_CONNECTOR_HDMIB
,
517 DRM_MODE_CONNECTOR_LVDS
,
518 DRM_MODE_CONNECTOR_9PinDIN
,
519 DRM_MODE_CONNECTOR_Unknown
,
520 DRM_MODE_CONNECTOR_Unknown
,
521 DRM_MODE_CONNECTOR_Unknown
,
522 DRM_MODE_CONNECTOR_DisplayPort
,
523 DRM_MODE_CONNECTOR_eDP
,
524 DRM_MODE_CONNECTOR_Unknown
527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
529 struct radeon_device
*rdev
= dev
->dev_private
;
530 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
531 struct atom_context
*ctx
= mode_info
->atom_context
;
532 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
533 u16 size
, data_offset
;
535 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
536 ATOM_OBJECT_TABLE
*router_obj
;
537 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
538 ATOM_OBJECT_HEADER
*obj_header
;
539 int i
, j
, k
, path_size
, device_support
;
541 u16 igp_lane_info
, conn_id
, connector_object_id
;
542 struct radeon_i2c_bus_rec ddc_bus
;
543 struct radeon_router router
;
544 struct radeon_gpio_rec gpio
;
545 struct radeon_hpd hpd
;
547 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
553 router
.valid
= false;
555 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
556 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
557 (ctx
->bios
+ data_offset
+
558 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
559 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
560 (ctx
->bios
+ data_offset
+
561 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
562 router_obj
= (ATOM_OBJECT_TABLE
*)
563 (ctx
->bios
+ data_offset
+
564 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
565 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
568 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
569 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
570 ATOM_DISPLAY_OBJECT_PATH
*path
;
572 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
573 path_size
+= le16_to_cpu(path
->usSize
);
575 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
576 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
579 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
582 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
585 (le16_to_cpu(path
->usConnObjectId
) &
586 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
588 /* TODO CV support */
589 if (le16_to_cpu(path
->usDeviceTag
) ==
590 ATOM_DEVICE_CV_SUPPORT
)
594 if ((rdev
->flags
& RADEON_IS_IGP
) &&
596 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
597 uint16_t igp_offset
= 0;
598 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
601 GetIndexIntoMasterTable(DATA
,
602 IntegratedSystemInfo
);
604 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
605 &crev
, &igp_offset
)) {
609 (ATOM_INTEGRATED_SYSTEM_INFO_V2
610 *) (ctx
->bios
+ igp_offset
);
613 uint32_t slot_config
, ct
;
615 if (con_obj_num
== 1)
624 ct
= (slot_config
>> 16) & 0xff;
626 object_connector_convert
628 connector_object_id
= ct
;
630 slot_config
& 0xffff;
638 object_connector_convert
[con_obj_id
];
639 connector_object_id
= con_obj_id
;
644 object_connector_convert
[con_obj_id
];
645 connector_object_id
= con_obj_id
;
648 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
651 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
652 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
655 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
656 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
658 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
659 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
661 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
662 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
664 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
665 u16 encoder_obj
= le16_to_cpu(path
->usGraphicObjIds
[j
]);
667 radeon_add_atom_encoder(dev
,
673 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
674 router
.valid
= false;
675 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
676 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[j
].usObjectID
);
677 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
678 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
679 (ctx
->bios
+ data_offset
+
680 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
681 ATOM_I2C_RECORD
*i2c_record
;
682 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
683 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
684 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
685 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
686 (ctx
->bios
+ data_offset
+
687 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
690 router
.router_id
= router_obj_id
;
691 for (enum_id
= 0; enum_id
< router_src_dst_table
->ucNumberOfDst
;
693 if (le16_to_cpu(path
->usConnObjectId
) ==
694 le16_to_cpu(router_src_dst_table
->usDstObjectID
[enum_id
]))
698 while (record
->ucRecordType
> 0 &&
699 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
700 switch (record
->ucRecordType
) {
701 case ATOM_I2C_RECORD_TYPE
:
706 (ATOM_I2C_ID_CONFIG_ACCESS
*)
707 &i2c_record
->sucI2cId
;
709 radeon_lookup_i2c_gpio(rdev
,
712 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
714 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
715 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
718 router
.mux_type
= ddc_path
->ucMuxType
;
719 router
.mux_control_pin
= ddc_path
->ucMuxControlPin
;
720 router
.mux_state
= ddc_path
->ucMuxState
[enum_id
];
723 record
= (ATOM_COMMON_RECORD_HEADER
*)
724 ((char *)record
+ record
->ucRecordSize
);
731 /* look up gpio for ddc, hpd */
732 ddc_bus
.valid
= false;
733 hpd
.hpd
= RADEON_HPD_NONE
;
734 if ((le16_to_cpu(path
->usDeviceTag
) &
735 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
736 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
737 if (le16_to_cpu(path
->usConnObjectId
) ==
738 le16_to_cpu(con_obj
->asObjects
[j
].
740 ATOM_COMMON_RECORD_HEADER
742 (ATOM_COMMON_RECORD_HEADER
744 (ctx
->bios
+ data_offset
+
745 le16_to_cpu(con_obj
->
748 ATOM_I2C_RECORD
*i2c_record
;
749 ATOM_HPD_INT_RECORD
*hpd_record
;
750 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
752 while (record
->ucRecordType
> 0
755 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
756 switch (record
->ucRecordType
) {
757 case ATOM_I2C_RECORD_TYPE
:
762 (ATOM_I2C_ID_CONFIG_ACCESS
*)
763 &i2c_record
->sucI2cId
;
764 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
768 case ATOM_HPD_INT_RECORD_TYPE
:
770 (ATOM_HPD_INT_RECORD
*)
772 gpio
= radeon_lookup_gpio(rdev
,
773 hpd_record
->ucHPDIntGPIOID
);
774 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
775 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
779 (ATOM_COMMON_RECORD_HEADER
790 /* needed for aux chan transactions */
791 ddc_bus
.hpd
= hpd
.hpd
;
793 conn_id
= le16_to_cpu(path
->usConnObjectId
);
795 if (!radeon_atom_apply_quirks
796 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
797 &ddc_bus
, &conn_id
, &hpd
))
800 radeon_add_atom_connector(dev
,
804 connector_type
, &ddc_bus
,
813 radeon_link_encoder_connector(dev
);
818 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
822 struct radeon_device
*rdev
= dev
->dev_private
;
824 if (rdev
->flags
& RADEON_IS_IGP
) {
825 return supported_devices_connector_object_id_convert
827 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
828 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
829 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
830 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
831 struct atom_context
*ctx
= mode_info
->atom_context
;
832 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
833 uint16_t size
, data_offset
;
835 ATOM_XTMDS_INFO
*xtmds
;
837 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
838 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
840 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
841 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
842 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
844 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
846 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
847 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
849 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
852 return supported_devices_connector_object_id_convert
855 return supported_devices_connector_object_id_convert
860 struct bios_connector
{
865 struct radeon_i2c_bus_rec ddc_bus
;
866 struct radeon_hpd hpd
;
869 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
873 struct radeon_device
*rdev
= dev
->dev_private
;
874 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
875 struct atom_context
*ctx
= mode_info
->atom_context
;
876 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
877 uint16_t size
, data_offset
;
879 uint16_t device_support
;
881 union atom_supported_devices
*supported_devices
;
882 int i
, j
, max_device
;
883 struct bios_connector
*bios_connectors
;
884 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
885 struct radeon_router router
;
887 router
.valid
= false;
889 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
890 if (!bios_connectors
)
893 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
895 kfree(bios_connectors
);
900 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
902 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
905 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
907 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
909 for (i
= 0; i
< max_device
; i
++) {
910 ATOM_CONNECTOR_INFO_I2C ci
=
911 supported_devices
->info
.asConnInfo
[i
];
913 bios_connectors
[i
].valid
= false;
915 if (!(device_support
& (1 << i
))) {
919 if (i
== ATOM_DEVICE_CV_INDEX
) {
920 DRM_DEBUG_KMS("Skipping Component Video\n");
924 bios_connectors
[i
].connector_type
=
925 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
929 if (bios_connectors
[i
].connector_type
==
930 DRM_MODE_CONNECTOR_Unknown
)
933 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
935 bios_connectors
[i
].line_mux
=
936 ci
.sucI2cId
.ucAccess
;
938 /* give tv unique connector ids */
939 if (i
== ATOM_DEVICE_TV1_INDEX
) {
940 bios_connectors
[i
].ddc_bus
.valid
= false;
941 bios_connectors
[i
].line_mux
= 50;
942 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
943 bios_connectors
[i
].ddc_bus
.valid
= false;
944 bios_connectors
[i
].line_mux
= 51;
945 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
946 bios_connectors
[i
].ddc_bus
.valid
= false;
947 bios_connectors
[i
].line_mux
= 52;
949 bios_connectors
[i
].ddc_bus
=
950 radeon_lookup_i2c_gpio(rdev
,
951 bios_connectors
[i
].line_mux
);
953 if ((crev
> 1) && (frev
> 1)) {
954 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
957 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
960 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
963 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
967 if (i
== ATOM_DEVICE_DFP1_INDEX
)
968 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
969 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
970 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
972 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
975 /* Always set the connector type to VGA for CRT1/CRT2. if they are
976 * shared with a DVI port, we'll pick up the DVI connector when we
977 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
979 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
980 bios_connectors
[i
].connector_type
=
981 DRM_MODE_CONNECTOR_VGA
;
983 if (!radeon_atom_apply_quirks
984 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
985 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
986 &bios_connectors
[i
].hpd
))
989 bios_connectors
[i
].valid
= true;
990 bios_connectors
[i
].devices
= (1 << i
);
992 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
993 radeon_add_atom_encoder(dev
,
994 radeon_get_encoder_enum(dev
,
999 radeon_add_legacy_encoder(dev
,
1000 radeon_get_encoder_enum(dev
,
1006 /* combine shared connectors */
1007 for (i
= 0; i
< max_device
; i
++) {
1008 if (bios_connectors
[i
].valid
) {
1009 for (j
= 0; j
< max_device
; j
++) {
1010 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
1011 if (bios_connectors
[i
].line_mux
==
1012 bios_connectors
[j
].line_mux
) {
1013 /* make sure not to combine LVDS */
1014 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1015 bios_connectors
[i
].line_mux
= 53;
1016 bios_connectors
[i
].ddc_bus
.valid
= false;
1019 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1020 bios_connectors
[j
].line_mux
= 53;
1021 bios_connectors
[j
].ddc_bus
.valid
= false;
1024 /* combine analog and digital for DVI-I */
1025 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1026 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1027 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1028 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1029 bios_connectors
[i
].devices
|=
1030 bios_connectors
[j
].devices
;
1031 bios_connectors
[i
].connector_type
=
1032 DRM_MODE_CONNECTOR_DVII
;
1033 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1034 bios_connectors
[i
].hpd
=
1035 bios_connectors
[j
].hpd
;
1036 bios_connectors
[j
].valid
= false;
1044 /* add the connectors */
1045 for (i
= 0; i
< max_device
; i
++) {
1046 if (bios_connectors
[i
].valid
) {
1047 uint16_t connector_object_id
=
1048 atombios_get_connector_object_id(dev
,
1049 bios_connectors
[i
].connector_type
,
1050 bios_connectors
[i
].devices
);
1051 radeon_add_atom_connector(dev
,
1052 bios_connectors
[i
].line_mux
,
1053 bios_connectors
[i
].devices
,
1056 &bios_connectors
[i
].ddc_bus
,
1058 connector_object_id
,
1059 &bios_connectors
[i
].hpd
,
1064 radeon_link_encoder_connector(dev
);
1066 kfree(bios_connectors
);
1070 union firmware_info
{
1071 ATOM_FIRMWARE_INFO info
;
1072 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1073 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1074 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1075 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1078 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1080 struct radeon_device
*rdev
= dev
->dev_private
;
1081 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1082 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1083 union firmware_info
*firmware_info
;
1085 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1086 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1087 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1088 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1089 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1090 uint16_t data_offset
;
1092 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1093 &frev
, &crev
, &data_offset
)) {
1095 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1098 p1pll
->reference_freq
=
1099 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1100 p1pll
->reference_div
= 0;
1103 p1pll
->pll_out_min
=
1104 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1106 p1pll
->pll_out_min
=
1107 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1108 p1pll
->pll_out_max
=
1109 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1112 p1pll
->lcd_pll_out_min
=
1113 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1114 if (p1pll
->lcd_pll_out_min
== 0)
1115 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1116 p1pll
->lcd_pll_out_max
=
1117 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1118 if (p1pll
->lcd_pll_out_max
== 0)
1119 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1121 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1122 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1125 if (p1pll
->pll_out_min
== 0) {
1126 if (ASIC_IS_AVIVO(rdev
))
1127 p1pll
->pll_out_min
= 64800;
1129 p1pll
->pll_out_min
= 20000;
1130 } else if (p1pll
->pll_out_min
> 64800) {
1131 /* Limiting the pll output range is a good thing generally as
1132 * it limits the number of possible pll combinations for a given
1133 * frequency presumably to the ones that work best on each card.
1134 * However, certain duallink DVI monitors seem to like
1135 * pll combinations that would be limited by this at least on
1136 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1139 if (!radeon_new_pll
)
1140 p1pll
->pll_out_min
= 64800;
1144 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1146 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1151 spll
->reference_freq
=
1152 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1153 spll
->reference_div
= 0;
1156 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1158 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1161 if (spll
->pll_out_min
== 0) {
1162 if (ASIC_IS_AVIVO(rdev
))
1163 spll
->pll_out_min
= 64800;
1165 spll
->pll_out_min
= 20000;
1169 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1171 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1174 mpll
->reference_freq
=
1175 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1176 mpll
->reference_div
= 0;
1179 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1181 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1184 if (mpll
->pll_out_min
== 0) {
1185 if (ASIC_IS_AVIVO(rdev
))
1186 mpll
->pll_out_min
= 64800;
1188 mpll
->pll_out_min
= 20000;
1192 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1194 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1196 rdev
->clock
.default_sclk
=
1197 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1198 rdev
->clock
.default_mclk
=
1199 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1201 if (ASIC_IS_DCE4(rdev
)) {
1202 rdev
->clock
.default_dispclk
=
1203 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1204 if (rdev
->clock
.default_dispclk
== 0)
1205 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1206 rdev
->clock
.dp_extclk
=
1207 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1218 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1219 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1222 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1224 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1225 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1226 union igp_info
*igp_info
;
1230 /* sideport is AMD only */
1231 if (rdev
->family
== CHIP_RS600
)
1234 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1235 &frev
, &crev
, &data_offset
)) {
1236 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1240 if (igp_info
->info
.ulBootUpMemoryClock
)
1244 if (igp_info
->info_2
.ulBootUpSidePortClock
)
1248 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1255 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1256 struct radeon_encoder_int_tmds
*tmds
)
1258 struct drm_device
*dev
= encoder
->base
.dev
;
1259 struct radeon_device
*rdev
= dev
->dev_private
;
1260 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1261 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1262 uint16_t data_offset
;
1263 struct _ATOM_TMDS_INFO
*tmds_info
;
1268 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1269 &frev
, &crev
, &data_offset
)) {
1271 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1274 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1275 for (i
= 0; i
< 4; i
++) {
1276 tmds
->tmds_pll
[i
].freq
=
1277 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1278 tmds
->tmds_pll
[i
].value
=
1279 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1280 tmds
->tmds_pll
[i
].value
|=
1281 (tmds_info
->asMiscInfo
[i
].
1282 ucPLL_VCO_Gain
& 0x3f) << 6;
1283 tmds
->tmds_pll
[i
].value
|=
1284 (tmds_info
->asMiscInfo
[i
].
1285 ucPLL_DutyCycle
& 0xf) << 12;
1286 tmds
->tmds_pll
[i
].value
|=
1287 (tmds_info
->asMiscInfo
[i
].
1288 ucPLL_VoltageSwing
& 0xf) << 16;
1290 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1291 tmds
->tmds_pll
[i
].freq
,
1292 tmds
->tmds_pll
[i
].value
);
1294 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1295 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1304 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
1309 struct drm_device
*dev
= encoder
->base
.dev
;
1310 struct radeon_device
*rdev
= dev
->dev_private
;
1311 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1312 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1313 uint16_t data_offset
;
1314 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1316 struct radeon_atom_ss
*ss
= NULL
;
1319 if (id
> ATOM_MAX_SS_ENTRY
)
1322 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1323 &frev
, &crev
, &data_offset
)) {
1325 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1328 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
1333 for (i
= 0; i
< ATOM_MAX_SS_ENTRY
; i
++) {
1334 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1336 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1337 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1338 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1339 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1340 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1341 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1350 struct _ATOM_LVDS_INFO info
;
1351 struct _ATOM_LVDS_INFO_V12 info_12
;
1354 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1358 struct drm_device
*dev
= encoder
->base
.dev
;
1359 struct radeon_device
*rdev
= dev
->dev_private
;
1360 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1361 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1362 uint16_t data_offset
, misc
;
1363 union lvds_info
*lvds_info
;
1365 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1366 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1368 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1369 &frev
, &crev
, &data_offset
)) {
1371 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1373 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1378 lvds
->native_mode
.clock
=
1379 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1380 lvds
->native_mode
.hdisplay
=
1381 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1382 lvds
->native_mode
.vdisplay
=
1383 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1384 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1385 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1386 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1387 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1388 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1389 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1390 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1391 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1392 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1393 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1394 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1395 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1396 lvds
->panel_pwr_delay
=
1397 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1398 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
1400 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1401 if (misc
& ATOM_VSYNC_POLARITY
)
1402 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1403 if (misc
& ATOM_HSYNC_POLARITY
)
1404 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1405 if (misc
& ATOM_COMPOSITESYNC
)
1406 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1407 if (misc
& ATOM_INTERLACE
)
1408 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1409 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1410 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1412 /* set crtc values */
1413 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1415 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
1417 if (ASIC_IS_AVIVO(rdev
)) {
1418 if (radeon_new_pll
== 0)
1419 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1421 lvds
->pll_algo
= PLL_ALGO_NEW
;
1423 if (radeon_new_pll
== 1)
1424 lvds
->pll_algo
= PLL_ALGO_NEW
;
1426 lvds
->pll_algo
= PLL_ALGO_LEGACY
;
1429 encoder
->native_mode
= lvds
->native_mode
;
1431 if (encoder_enum
== 2)
1434 lvds
->linkb
= false;
1440 struct radeon_encoder_primary_dac
*
1441 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1443 struct drm_device
*dev
= encoder
->base
.dev
;
1444 struct radeon_device
*rdev
= dev
->dev_private
;
1445 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1446 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1447 uint16_t data_offset
;
1448 struct _COMPASSIONATE_DATA
*dac_info
;
1451 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1453 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1454 &frev
, &crev
, &data_offset
)) {
1455 dac_info
= (struct _COMPASSIONATE_DATA
*)
1456 (mode_info
->atom_context
->bios
+ data_offset
);
1458 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1463 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1464 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1465 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1471 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1472 struct drm_display_mode
*mode
)
1474 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1475 ATOM_ANALOG_TV_INFO
*tv_info
;
1476 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1477 ATOM_DTD_FORMAT
*dtd_timings
;
1478 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1480 u16 data_offset
, misc
;
1482 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1483 &frev
, &crev
, &data_offset
))
1488 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1489 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1492 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1493 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1494 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1495 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1496 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1498 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1499 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1500 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1501 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1502 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1505 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1506 if (misc
& ATOM_VSYNC_POLARITY
)
1507 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1508 if (misc
& ATOM_HSYNC_POLARITY
)
1509 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1510 if (misc
& ATOM_COMPOSITESYNC
)
1511 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1512 if (misc
& ATOM_INTERLACE
)
1513 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1514 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1515 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1517 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1520 /* PAL timings appear to have wrong values for totals */
1521 mode
->crtc_htotal
-= 1;
1522 mode
->crtc_vtotal
-= 1;
1526 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1527 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1530 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1531 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1532 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1533 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1534 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1535 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1536 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1537 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1539 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1540 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1541 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1542 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1543 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1544 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1545 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1548 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1549 if (misc
& ATOM_VSYNC_POLARITY
)
1550 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1551 if (misc
& ATOM_HSYNC_POLARITY
)
1552 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1553 if (misc
& ATOM_COMPOSITESYNC
)
1554 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1555 if (misc
& ATOM_INTERLACE
)
1556 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1557 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1558 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1560 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1567 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1569 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1570 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1571 uint16_t data_offset
;
1573 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1574 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1576 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1577 &frev
, &crev
, &data_offset
)) {
1579 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1580 (mode_info
->atom_context
->bios
+ data_offset
);
1582 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1584 tv_std
= TV_STD_NTSC
;
1585 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1588 tv_std
= TV_STD_NTSC_J
;
1589 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1592 tv_std
= TV_STD_PAL
;
1593 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1596 tv_std
= TV_STD_PAL_M
;
1597 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1600 tv_std
= TV_STD_PAL_N
;
1601 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1604 tv_std
= TV_STD_PAL_CN
;
1605 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1608 tv_std
= TV_STD_PAL_60
;
1609 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1612 tv_std
= TV_STD_SECAM
;
1613 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1616 tv_std
= TV_STD_NTSC
;
1617 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1624 struct radeon_encoder_tv_dac
*
1625 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1627 struct drm_device
*dev
= encoder
->base
.dev
;
1628 struct radeon_device
*rdev
= dev
->dev_private
;
1629 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1630 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1631 uint16_t data_offset
;
1632 struct _COMPASSIONATE_DATA
*dac_info
;
1635 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1637 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1638 &frev
, &crev
, &data_offset
)) {
1640 dac_info
= (struct _COMPASSIONATE_DATA
*)
1641 (mode_info
->atom_context
->bios
+ data_offset
);
1643 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1648 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1649 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1650 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1652 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1653 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1654 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1656 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1657 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1658 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1660 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1665 static const char *thermal_controller_names
[] = {
1676 static const char *pp_lib_thermal_controller_names
[] = {
1689 "adt7473 with internal",
1694 struct _ATOM_POWERPLAY_INFO info
;
1695 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1696 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1697 struct _ATOM_PPLIB_POWERPLAYTABLE info_4
;
1700 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
1702 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1703 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1706 u32 misc
, misc2
= 0, sclk
, mclk
;
1707 union power_info
*power_info
;
1708 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
1709 struct _ATOM_PPLIB_STATE
*power_state
;
1710 int num_modes
= 0, i
, j
;
1711 int state_index
= 0, mode_index
= 0;
1712 struct radeon_i2c_bus_rec i2c_bus
;
1714 rdev
->pm
.default_power_state_index
= -1;
1716 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1717 &frev
, &crev
, &data_offset
)) {
1718 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1720 /* add the i2c bus for thermal/fan chip */
1721 if (power_info
->info
.ucOverdriveThermalController
> 0) {
1722 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1723 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
1724 power_info
->info
.ucOverdriveControllerAddress
>> 1);
1725 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
1726 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1727 if (rdev
->pm
.i2c_bus
) {
1728 struct i2c_board_info info
= { };
1729 const char *name
= thermal_controller_names
[power_info
->info
.
1730 ucOverdriveThermalController
];
1731 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
1732 strlcpy(info
.type
, name
, sizeof(info
.type
));
1733 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
1736 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
1737 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
1738 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
1739 /* last mode is usually default, array is low to high */
1740 for (i
= 0; i
< num_modes
; i
++) {
1741 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1744 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1745 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1746 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
1747 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1748 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
1749 /* skip invalid modes */
1750 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1751 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1753 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1754 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1755 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
1756 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1757 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1758 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1760 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1761 radeon_lookup_gpio(rdev
,
1762 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1763 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1764 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1767 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1769 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1770 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1772 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1773 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1775 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1776 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1777 /* order matters! */
1778 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1779 rdev
->pm
.power_state
[state_index
].type
=
1780 POWER_STATE_TYPE_POWERSAVE
;
1781 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1782 rdev
->pm
.power_state
[state_index
].type
=
1783 POWER_STATE_TYPE_BATTERY
;
1784 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1785 rdev
->pm
.power_state
[state_index
].type
=
1786 POWER_STATE_TYPE_BATTERY
;
1787 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1788 rdev
->pm
.power_state
[state_index
].type
=
1789 POWER_STATE_TYPE_BALANCED
;
1790 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1791 rdev
->pm
.power_state
[state_index
].type
=
1792 POWER_STATE_TYPE_PERFORMANCE
;
1793 rdev
->pm
.power_state
[state_index
].flags
&=
1794 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1796 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1797 rdev
->pm
.power_state
[state_index
].type
=
1798 POWER_STATE_TYPE_DEFAULT
;
1799 rdev
->pm
.default_power_state_index
= state_index
;
1800 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1801 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1802 rdev
->pm
.power_state
[state_index
].flags
&=
1803 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1804 } else if (state_index
== 0) {
1805 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1806 RADEON_PM_MODE_NO_DISPLAY
;
1811 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1812 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1813 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
1814 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1815 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
1816 /* skip invalid modes */
1817 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1818 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1820 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1821 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1822 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
1823 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1824 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1825 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1826 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1828 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1829 radeon_lookup_gpio(rdev
,
1830 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1831 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1832 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1835 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1837 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1838 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1840 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1841 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1843 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1844 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1845 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1846 /* order matters! */
1847 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1848 rdev
->pm
.power_state
[state_index
].type
=
1849 POWER_STATE_TYPE_POWERSAVE
;
1850 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1851 rdev
->pm
.power_state
[state_index
].type
=
1852 POWER_STATE_TYPE_BATTERY
;
1853 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1854 rdev
->pm
.power_state
[state_index
].type
=
1855 POWER_STATE_TYPE_BATTERY
;
1856 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1857 rdev
->pm
.power_state
[state_index
].type
=
1858 POWER_STATE_TYPE_BALANCED
;
1859 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1860 rdev
->pm
.power_state
[state_index
].type
=
1861 POWER_STATE_TYPE_PERFORMANCE
;
1862 rdev
->pm
.power_state
[state_index
].flags
&=
1863 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1865 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1866 rdev
->pm
.power_state
[state_index
].type
=
1867 POWER_STATE_TYPE_BALANCED
;
1868 if (misc2
& ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT
)
1869 rdev
->pm
.power_state
[state_index
].flags
&=
1870 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1871 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1872 rdev
->pm
.power_state
[state_index
].type
=
1873 POWER_STATE_TYPE_DEFAULT
;
1874 rdev
->pm
.default_power_state_index
= state_index
;
1875 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1876 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1877 rdev
->pm
.power_state
[state_index
].flags
&=
1878 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1879 } else if (state_index
== 0) {
1880 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1881 RADEON_PM_MODE_NO_DISPLAY
;
1886 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1887 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1888 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
1889 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1890 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
1891 /* skip invalid modes */
1892 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1893 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1895 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1896 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1897 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
1898 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1899 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1900 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1901 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1903 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1904 radeon_lookup_gpio(rdev
,
1905 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1906 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1907 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1910 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1912 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1913 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1915 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1916 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1917 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
1918 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
1920 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
1921 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
1924 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1925 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1926 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1927 /* order matters! */
1928 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1929 rdev
->pm
.power_state
[state_index
].type
=
1930 POWER_STATE_TYPE_POWERSAVE
;
1931 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1932 rdev
->pm
.power_state
[state_index
].type
=
1933 POWER_STATE_TYPE_BATTERY
;
1934 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1935 rdev
->pm
.power_state
[state_index
].type
=
1936 POWER_STATE_TYPE_BATTERY
;
1937 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1938 rdev
->pm
.power_state
[state_index
].type
=
1939 POWER_STATE_TYPE_BALANCED
;
1940 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1941 rdev
->pm
.power_state
[state_index
].type
=
1942 POWER_STATE_TYPE_PERFORMANCE
;
1943 rdev
->pm
.power_state
[state_index
].flags
&=
1944 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1946 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1947 rdev
->pm
.power_state
[state_index
].type
=
1948 POWER_STATE_TYPE_BALANCED
;
1949 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1950 rdev
->pm
.power_state
[state_index
].type
=
1951 POWER_STATE_TYPE_DEFAULT
;
1952 rdev
->pm
.default_power_state_index
= state_index
;
1953 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1954 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1955 } else if (state_index
== 0) {
1956 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1957 RADEON_PM_MODE_NO_DISPLAY
;
1963 /* last mode is usually default */
1964 if (rdev
->pm
.default_power_state_index
== -1) {
1965 rdev
->pm
.power_state
[state_index
- 1].type
=
1966 POWER_STATE_TYPE_DEFAULT
;
1967 rdev
->pm
.default_power_state_index
= state_index
- 1;
1968 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
1969 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
1970 rdev
->pm
.power_state
[state_index
].flags
&=
1971 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1972 rdev
->pm
.power_state
[state_index
].misc
= 0;
1973 rdev
->pm
.power_state
[state_index
].misc2
= 0;
1976 int fw_index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1977 uint8_t fw_frev
, fw_crev
;
1978 uint16_t fw_data_offset
, vddc
= 0;
1979 union firmware_info
*firmware_info
;
1980 ATOM_PPLIB_THERMALCONTROLLER
*controller
= &power_info
->info_4
.sThermalController
;
1982 if (atom_parse_data_header(mode_info
->atom_context
, fw_index
, NULL
,
1983 &fw_frev
, &fw_crev
, &fw_data_offset
)) {
1985 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1987 vddc
= firmware_info
->info_14
.usBootUpVDDCVoltage
;
1990 /* add the i2c bus for thermal/fan chip */
1991 if (controller
->ucType
> 0) {
1992 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
1993 DRM_INFO("Internal thermal controller %s fan control\n",
1994 (controller
->ucFanParameters
&
1995 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
1996 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
1997 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
1998 DRM_INFO("Internal thermal controller %s fan control\n",
1999 (controller
->ucFanParameters
&
2000 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2001 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2002 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2003 DRM_INFO("Internal thermal controller %s fan control\n",
2004 (controller
->ucFanParameters
&
2005 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2006 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2007 } else if ((controller
->ucType
==
2008 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) ||
2009 (controller
->ucType
==
2010 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
)) {
2011 DRM_INFO("Special thermal controller config\n");
2013 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2014 pp_lib_thermal_controller_names
[controller
->ucType
],
2015 controller
->ucI2cAddress
>> 1,
2016 (controller
->ucFanParameters
&
2017 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2018 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2019 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2020 if (rdev
->pm
.i2c_bus
) {
2021 struct i2c_board_info info
= { };
2022 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2023 info
.addr
= controller
->ucI2cAddress
>> 1;
2024 strlcpy(info
.type
, name
, sizeof(info
.type
));
2025 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2030 /* first mode is usually default, followed by low to high */
2031 for (i
= 0; i
< power_info
->info_4
.ucNumStates
; i
++) {
2033 power_state
= (struct _ATOM_PPLIB_STATE
*)
2034 (mode_info
->atom_context
->bios
+
2036 le16_to_cpu(power_info
->info_4
.usStateArrayOffset
) +
2037 i
* power_info
->info_4
.ucStateEntrySize
);
2038 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2039 (mode_info
->atom_context
->bios
+
2041 le16_to_cpu(power_info
->info_4
.usNonClockInfoArrayOffset
) +
2042 (power_state
->ucNonClockStateIndex
*
2043 power_info
->info_4
.ucNonClockSize
));
2044 for (j
= 0; j
< (power_info
->info_4
.ucStateEntrySize
- 1); j
++) {
2045 if (rdev
->flags
& RADEON_IS_IGP
) {
2046 struct _ATOM_PPLIB_RS780_CLOCK_INFO
*clock_info
=
2047 (struct _ATOM_PPLIB_RS780_CLOCK_INFO
*)
2048 (mode_info
->atom_context
->bios
+
2050 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2051 (power_state
->ucClockStateIndices
[j
] *
2052 power_info
->info_4
.ucClockInfoSize
));
2053 sclk
= le16_to_cpu(clock_info
->usLowEngineClockLow
);
2054 sclk
|= clock_info
->ucLowEngineClockHigh
<< 16;
2055 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2056 /* skip invalid modes */
2057 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2059 /* voltage works differently on IGPs */
2061 } else if (ASIC_IS_DCE4(rdev
)) {
2062 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
*clock_info
=
2063 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
*)
2064 (mode_info
->atom_context
->bios
+
2066 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2067 (power_state
->ucClockStateIndices
[j
] *
2068 power_info
->info_4
.ucClockInfoSize
));
2069 sclk
= le16_to_cpu(clock_info
->usEngineClockLow
);
2070 sclk
|= clock_info
->ucEngineClockHigh
<< 16;
2071 mclk
= le16_to_cpu(clock_info
->usMemoryClockLow
);
2072 mclk
|= clock_info
->ucMemoryClockHigh
<< 16;
2073 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2074 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2075 /* skip invalid modes */
2076 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2077 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2079 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2081 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2085 struct _ATOM_PPLIB_R600_CLOCK_INFO
*clock_info
=
2086 (struct _ATOM_PPLIB_R600_CLOCK_INFO
*)
2087 (mode_info
->atom_context
->bios
+
2089 le16_to_cpu(power_info
->info_4
.usClockInfoArrayOffset
) +
2090 (power_state
->ucClockStateIndices
[j
] *
2091 power_info
->info_4
.ucClockInfoSize
));
2092 sclk
= le16_to_cpu(clock_info
->usEngineClockLow
);
2093 sclk
|= clock_info
->ucEngineClockHigh
<< 16;
2094 mclk
= le16_to_cpu(clock_info
->usMemoryClockLow
);
2095 mclk
|= clock_info
->ucMemoryClockHigh
<< 16;
2096 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2097 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2098 /* skip invalid modes */
2099 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2100 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2102 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2104 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2109 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2111 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2112 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2113 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2114 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2115 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2116 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2117 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2118 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2119 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2120 rdev
->pm
.power_state
[state_index
].type
=
2121 POWER_STATE_TYPE_BATTERY
;
2123 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2124 rdev
->pm
.power_state
[state_index
].type
=
2125 POWER_STATE_TYPE_BALANCED
;
2127 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2128 rdev
->pm
.power_state
[state_index
].type
=
2129 POWER_STATE_TYPE_PERFORMANCE
;
2131 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2132 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2133 rdev
->pm
.power_state
[state_index
].type
=
2134 POWER_STATE_TYPE_PERFORMANCE
;
2137 rdev
->pm
.power_state
[state_index
].flags
= 0;
2138 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2139 rdev
->pm
.power_state
[state_index
].flags
|=
2140 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2141 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2142 rdev
->pm
.power_state
[state_index
].type
=
2143 POWER_STATE_TYPE_DEFAULT
;
2144 rdev
->pm
.default_power_state_index
= state_index
;
2145 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2146 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2147 /* patch the table values with the default slck/mclk from firmware info */
2148 for (j
= 0; j
< mode_index
; j
++) {
2149 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2150 rdev
->clock
.default_mclk
;
2151 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2152 rdev
->clock
.default_sclk
;
2154 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2161 /* if multiple clock modes, mark the lowest as no display */
2162 for (i
= 0; i
< state_index
; i
++) {
2163 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2164 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2165 RADEON_PM_MODE_NO_DISPLAY
;
2167 /* first mode is usually default */
2168 if (rdev
->pm
.default_power_state_index
== -1) {
2169 rdev
->pm
.power_state
[0].type
=
2170 POWER_STATE_TYPE_DEFAULT
;
2171 rdev
->pm
.default_power_state_index
= 0;
2172 rdev
->pm
.power_state
[0].default_clock_mode
=
2173 &rdev
->pm
.power_state
[0].clock_info
[0];
2177 /* add the default mode */
2178 rdev
->pm
.power_state
[state_index
].type
=
2179 POWER_STATE_TYPE_DEFAULT
;
2180 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2181 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2182 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2183 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2184 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2185 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2186 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2187 rdev
->pm
.default_power_state_index
= state_index
;
2188 rdev
->pm
.power_state
[state_index
].flags
= 0;
2192 rdev
->pm
.num_power_states
= state_index
;
2194 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2195 rdev
->pm
.current_clock_mode_index
= 0;
2196 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2199 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2201 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2202 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2204 args
.ucEnable
= enable
;
2206 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2209 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2211 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2212 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2214 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2215 return args
.ulReturnEngineClock
;
2218 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2220 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2221 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2223 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2224 return args
.ulReturnMemoryClock
;
2227 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2230 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2231 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2233 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
2235 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2238 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2241 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2242 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
2244 if (rdev
->flags
& RADEON_IS_IGP
)
2247 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
2249 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2253 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
2254 struct _SET_VOLTAGE_PARAMETERS v1
;
2255 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
2258 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 level
)
2260 union set_voltage args
;
2261 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2262 u8 frev
, crev
, volt_index
= level
;
2264 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2269 args
.v1
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2270 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
2271 args
.v1
.ucVoltageIndex
= volt_index
;
2274 args
.v2
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2275 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
2276 args
.v2
.usVoltageLevel
= cpu_to_le16(level
);
2279 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2283 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2288 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
2290 struct radeon_device
*rdev
= dev
->dev_private
;
2291 uint32_t bios_2_scratch
, bios_6_scratch
;
2293 if (rdev
->family
>= CHIP_R600
) {
2294 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2295 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2297 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2298 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2301 /* let the bios control the backlight */
2302 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
2304 /* tell the bios not to handle mode switching */
2305 bios_6_scratch
|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
;
2307 if (rdev
->family
>= CHIP_R600
) {
2308 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2309 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2311 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
2312 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2317 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
2319 uint32_t scratch_reg
;
2322 if (rdev
->family
>= CHIP_R600
)
2323 scratch_reg
= R600_BIOS_0_SCRATCH
;
2325 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2327 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2328 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
2331 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
2333 uint32_t scratch_reg
;
2336 if (rdev
->family
>= CHIP_R600
)
2337 scratch_reg
= R600_BIOS_0_SCRATCH
;
2339 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2341 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2342 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
2345 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
2347 struct drm_device
*dev
= encoder
->dev
;
2348 struct radeon_device
*rdev
= dev
->dev_private
;
2349 uint32_t bios_6_scratch
;
2351 if (rdev
->family
>= CHIP_R600
)
2352 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2354 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2357 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
2358 bios_6_scratch
&= ~ATOM_S6_ACC_MODE
;
2360 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
2361 bios_6_scratch
|= ATOM_S6_ACC_MODE
;
2364 if (rdev
->family
>= CHIP_R600
)
2365 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2367 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2370 /* at some point we may want to break this out into individual functions */
2372 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
2373 struct drm_encoder
*encoder
,
2376 struct drm_device
*dev
= connector
->dev
;
2377 struct radeon_device
*rdev
= dev
->dev_private
;
2378 struct radeon_connector
*radeon_connector
=
2379 to_radeon_connector(connector
);
2380 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2381 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
2383 if (rdev
->family
>= CHIP_R600
) {
2384 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2385 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2386 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2388 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2389 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2390 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2393 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
2394 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
2396 DRM_DEBUG_KMS("TV1 connected\n");
2397 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
2398 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
2400 DRM_DEBUG_KMS("TV1 disconnected\n");
2401 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
2402 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
2403 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
2406 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
2407 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
2409 DRM_DEBUG_KMS("CV connected\n");
2410 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
2411 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
2413 DRM_DEBUG_KMS("CV disconnected\n");
2414 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
2415 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
2416 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
2419 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
2420 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
2422 DRM_DEBUG_KMS("LCD1 connected\n");
2423 bios_0_scratch
|= ATOM_S0_LCD1
;
2424 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
2425 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
2427 DRM_DEBUG_KMS("LCD1 disconnected\n");
2428 bios_0_scratch
&= ~ATOM_S0_LCD1
;
2429 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
2430 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
2433 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
2434 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
2436 DRM_DEBUG_KMS("CRT1 connected\n");
2437 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
2438 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
2439 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
2441 DRM_DEBUG_KMS("CRT1 disconnected\n");
2442 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
2443 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
2444 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
2447 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
2448 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
2450 DRM_DEBUG_KMS("CRT2 connected\n");
2451 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
2452 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
2453 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
2455 DRM_DEBUG_KMS("CRT2 disconnected\n");
2456 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
2457 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
2458 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
2461 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
2462 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
2464 DRM_DEBUG_KMS("DFP1 connected\n");
2465 bios_0_scratch
|= ATOM_S0_DFP1
;
2466 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
2467 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
2469 DRM_DEBUG_KMS("DFP1 disconnected\n");
2470 bios_0_scratch
&= ~ATOM_S0_DFP1
;
2471 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
2472 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
2475 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2476 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2478 DRM_DEBUG_KMS("DFP2 connected\n");
2479 bios_0_scratch
|= ATOM_S0_DFP2
;
2480 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
2481 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
2483 DRM_DEBUG_KMS("DFP2 disconnected\n");
2484 bios_0_scratch
&= ~ATOM_S0_DFP2
;
2485 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
2486 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
2489 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
2490 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
2492 DRM_DEBUG_KMS("DFP3 connected\n");
2493 bios_0_scratch
|= ATOM_S0_DFP3
;
2494 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
2495 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
2497 DRM_DEBUG_KMS("DFP3 disconnected\n");
2498 bios_0_scratch
&= ~ATOM_S0_DFP3
;
2499 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
2500 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
2503 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
2504 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
2506 DRM_DEBUG_KMS("DFP4 connected\n");
2507 bios_0_scratch
|= ATOM_S0_DFP4
;
2508 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
2509 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
2511 DRM_DEBUG_KMS("DFP4 disconnected\n");
2512 bios_0_scratch
&= ~ATOM_S0_DFP4
;
2513 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
2514 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
2517 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
2518 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
2520 DRM_DEBUG_KMS("DFP5 connected\n");
2521 bios_0_scratch
|= ATOM_S0_DFP5
;
2522 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
2523 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
2525 DRM_DEBUG_KMS("DFP5 disconnected\n");
2526 bios_0_scratch
&= ~ATOM_S0_DFP5
;
2527 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
2528 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
2532 if (rdev
->family
>= CHIP_R600
) {
2533 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
2534 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2535 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2537 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2538 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2539 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2544 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2546 struct drm_device
*dev
= encoder
->dev
;
2547 struct radeon_device
*rdev
= dev
->dev_private
;
2548 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2549 uint32_t bios_3_scratch
;
2551 if (rdev
->family
>= CHIP_R600
)
2552 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2554 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2556 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2557 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
2558 bios_3_scratch
|= (crtc
<< 18);
2560 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2561 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
2562 bios_3_scratch
|= (crtc
<< 24);
2564 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2565 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
2566 bios_3_scratch
|= (crtc
<< 16);
2568 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2569 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
2570 bios_3_scratch
|= (crtc
<< 20);
2572 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2573 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
2574 bios_3_scratch
|= (crtc
<< 17);
2576 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2577 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
2578 bios_3_scratch
|= (crtc
<< 19);
2580 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2581 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
2582 bios_3_scratch
|= (crtc
<< 23);
2584 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2585 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
2586 bios_3_scratch
|= (crtc
<< 25);
2589 if (rdev
->family
>= CHIP_R600
)
2590 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2592 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2596 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2598 struct drm_device
*dev
= encoder
->dev
;
2599 struct radeon_device
*rdev
= dev
->dev_private
;
2600 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2601 uint32_t bios_2_scratch
;
2603 if (rdev
->family
>= CHIP_R600
)
2604 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2606 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2608 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2610 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
2612 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
2614 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2616 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
2618 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
2620 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2622 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
2624 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
2626 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2628 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
2630 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
2632 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2634 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
2636 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
2638 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2640 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
2642 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
2644 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2646 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
2648 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
2650 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2652 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
2654 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
2656 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
2658 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
2660 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
2662 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
2664 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
2666 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
2669 if (rdev
->family
>= CHIP_R600
)
2670 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2672 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);