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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / radeon / evergreen_cs.c
blob7d73834be4fb9ace61d6f9f588a1c71f090c9093
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "evergreend.h"
31 #include "evergreen_reg_safe.h"
32
33 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc);
35
36 struct evergreen_cs_track {
37 u32 group_size;
38 u32 nbanks;
39 u32 npipes;
40 /* value we track */
41 u32 nsamples;
42 u32 cb_color_base_last[12];
43 struct radeon_bo *cb_color_bo[12];
44 u32 cb_color_bo_offset[12];
45 struct radeon_bo *cb_color_fmask_bo[8];
46 struct radeon_bo *cb_color_cmask_bo[8];
47 u32 cb_color_info[12];
48 u32 cb_color_view[12];
49 u32 cb_color_pitch_idx[12];
50 u32 cb_color_slice_idx[12];
51 u32 cb_color_dim_idx[12];
52 u32 cb_color_dim[12];
53 u32 cb_color_pitch[12];
54 u32 cb_color_slice[12];
55 u32 cb_color_cmask_slice[8];
56 u32 cb_color_fmask_slice[8];
57 u32 cb_target_mask;
58 u32 cb_shader_mask;
59 u32 vgt_strmout_config;
60 u32 vgt_strmout_buffer_config;
61 u32 db_depth_control;
62 u32 db_depth_view;
63 u32 db_depth_size;
64 u32 db_depth_size_idx;
65 u32 db_z_info;
66 u32 db_z_idx;
67 u32 db_z_read_offset;
68 u32 db_z_write_offset;
69 struct radeon_bo *db_z_read_bo;
70 struct radeon_bo *db_z_write_bo;
71 u32 db_s_info;
72 u32 db_s_idx;
73 u32 db_s_read_offset;
74 u32 db_s_write_offset;
75 struct radeon_bo *db_s_read_bo;
76 struct radeon_bo *db_s_write_bo;
77 };
78
79 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
80 {
81 int i;
82
83 for (i = 0; i < 8; i++) {
84 track->cb_color_fmask_bo[i] = NULL;
85 track->cb_color_cmask_bo[i] = NULL;
86 track->cb_color_cmask_slice[i] = 0;
87 track->cb_color_fmask_slice[i] = 0;
88 }
89
90 for (i = 0; i < 12; i++) {
91 track->cb_color_base_last[i] = 0;
92 track->cb_color_bo[i] = NULL;
93 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
94 track->cb_color_info[i] = 0;
95 track->cb_color_view[i] = 0;
96 track->cb_color_pitch_idx[i] = 0;
97 track->cb_color_slice_idx[i] = 0;
98 track->cb_color_dim[i] = 0;
99 track->cb_color_pitch[i] = 0;
100 track->cb_color_slice[i] = 0;
101 track->cb_color_dim[i] = 0;
102 }
103 track->cb_target_mask = 0xFFFFFFFF;
104 track->cb_shader_mask = 0xFFFFFFFF;
105
106 track->db_depth_view = 0xFFFFC000;
107 track->db_depth_size = 0xFFFFFFFF;
108 track->db_depth_size_idx = 0;
109 track->db_depth_control = 0xFFFFFFFF;
110 track->db_z_info = 0xFFFFFFFF;
111 track->db_z_idx = 0xFFFFFFFF;
112 track->db_z_read_offset = 0xFFFFFFFF;
113 track->db_z_write_offset = 0xFFFFFFFF;
114 track->db_z_read_bo = NULL;
115 track->db_z_write_bo = NULL;
116 track->db_s_info = 0xFFFFFFFF;
117 track->db_s_idx = 0xFFFFFFFF;
118 track->db_s_read_offset = 0xFFFFFFFF;
119 track->db_s_write_offset = 0xFFFFFFFF;
120 track->db_s_read_bo = NULL;
121 track->db_s_write_bo = NULL;
122 }
123
124 static inline int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
125 {
126 return 0;
127 }
128
129 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
130 {
131 struct evergreen_cs_track *track = p->track;
132
133 /* we don't support stream out buffer yet */
134 if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) {
135 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
136 return -EINVAL;
137 }
138
139 return 0;
140 }
141
142 /**
143 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
144 * @parser: parser structure holding parsing context.
145 * @pkt: where to store packet informations
146 *
147 * Assume that chunk_ib_index is properly set. Will return -EINVAL
148 * if packet is bigger than remaining ib size. or if packets is unknown.
149 **/
150 int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
151 struct radeon_cs_packet *pkt,
152 unsigned idx)
153 {
154 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
155 uint32_t header;
156
157 if (idx >= ib_chunk->length_dw) {
158 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
159 idx, ib_chunk->length_dw);
160 return -EINVAL;
161 }
162 header = radeon_get_ib_value(p, idx);
163 pkt->idx = idx;
164 pkt->type = CP_PACKET_GET_TYPE(header);
165 pkt->count = CP_PACKET_GET_COUNT(header);
166 pkt->one_reg_wr = 0;
167 switch (pkt->type) {
168 case PACKET_TYPE0:
169 pkt->reg = CP_PACKET0_GET_REG(header);
170 break;
171 case PACKET_TYPE3:
172 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
173 break;
174 case PACKET_TYPE2:
175 pkt->count = -1;
176 break;
177 default:
178 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
179 return -EINVAL;
180 }
181 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
182 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
183 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
184 return -EINVAL;
185 }
186 return 0;
187 }
188
189 /**
190 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
191 * @parser: parser structure holding parsing context.
192 * @data: pointer to relocation data
193 * @offset_start: starting offset
194 * @offset_mask: offset mask (to align start offset on)
195 * @reloc: reloc informations
196 *
197 * Check next packet is relocation packet3, do bo validation and compute
198 * GPU offset using the provided start.
199 **/
200 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
201 struct radeon_cs_reloc **cs_reloc)
202 {
203 struct radeon_cs_chunk *relocs_chunk;
204 struct radeon_cs_packet p3reloc;
205 unsigned idx;
206 int r;
207
208 if (p->chunk_relocs_idx == -1) {
209 DRM_ERROR("No relocation chunk !\n");
210 return -EINVAL;
211 }
212 *cs_reloc = NULL;
213 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
214 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
215 if (r) {
216 return r;
217 }
218 p->idx += p3reloc.count + 2;
219 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
220 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
221 p3reloc.idx);
222 return -EINVAL;
223 }
224 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
225 if (idx >= relocs_chunk->length_dw) {
226 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
227 idx, relocs_chunk->length_dw);
228 return -EINVAL;
229 }
230 *cs_reloc = p->relocs_ptr[(idx / 4)];
231 return 0;
232 }
233
234 /**
235 * evergreen_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
236 * @parser: parser structure holding parsing context.
237 *
238 * Check next packet is relocation packet3, do bo validation and compute
239 * GPU offset using the provided start.
240 **/
241 static inline int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
242 {
243 struct radeon_cs_packet p3reloc;
244 int r;
245
246 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
247 if (r) {
248 return 0;
249 }
250 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
251 return 0;
252 }
253 return 1;
254 }
255
256 /**
257 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
258 * @parser: parser structure holding parsing context.
259 *
260 * Userspace sends a special sequence for VLINE waits.
261 * PACKET0 - VLINE_START_END + value
262 * PACKET3 - WAIT_REG_MEM poll vline status reg
263 * RELOC (P3) - crtc_id in reloc.
264 *
265 * This function parses this and relocates the VLINE START END
266 * and WAIT_REG_MEM packets to the correct crtc.
267 * It also detects a switched off crtc and nulls out the
268 * wait in that case.
269 */
270 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
271 {
272 struct drm_mode_object *obj;
273 struct drm_crtc *crtc;
274 struct radeon_crtc *radeon_crtc;
275 struct radeon_cs_packet p3reloc, wait_reg_mem;
276 int crtc_id;
277 int r;
278 uint32_t header, h_idx, reg, wait_reg_mem_info;
279 volatile uint32_t *ib;
280
281 ib = p->ib->ptr;
282
283 /* parse the WAIT_REG_MEM */
284 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
285 if (r)
286 return r;
287
288 /* check its a WAIT_REG_MEM */
289 if (wait_reg_mem.type != PACKET_TYPE3 ||
290 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
291 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
292 r = -EINVAL;
293 return r;
294 }
295
296 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
297 /* bit 4 is reg (0) or mem (1) */
298 if (wait_reg_mem_info & 0x10) {
299 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
300 r = -EINVAL;
301 return r;
302 }
303 /* waiting for value to be equal */
304 if ((wait_reg_mem_info & 0x7) != 0x3) {
305 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
306 r = -EINVAL;
307 return r;
308 }
309 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
310 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
311 r = -EINVAL;
312 return r;
313 }
314
315 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
316 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
317 r = -EINVAL;
318 return r;
319 }
320
321 /* jump over the NOP */
322 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
323 if (r)
324 return r;
325
326 h_idx = p->idx - 2;
327 p->idx += wait_reg_mem.count + 2;
328 p->idx += p3reloc.count + 2;
329
330 header = radeon_get_ib_value(p, h_idx);
331 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
332 reg = CP_PACKET0_GET_REG(header);
333 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
334 if (!obj) {
335 DRM_ERROR("cannot find crtc %d\n", crtc_id);
336 r = -EINVAL;
337 goto out;
338 }
339 crtc = obj_to_crtc(obj);
340 radeon_crtc = to_radeon_crtc(crtc);
341 crtc_id = radeon_crtc->crtc_id;
342
343 if (!crtc->enabled) {
344 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
345 ib[h_idx + 2] = PACKET2(0);
346 ib[h_idx + 3] = PACKET2(0);
347 ib[h_idx + 4] = PACKET2(0);
348 ib[h_idx + 5] = PACKET2(0);
349 ib[h_idx + 6] = PACKET2(0);
350 ib[h_idx + 7] = PACKET2(0);
351 ib[h_idx + 8] = PACKET2(0);
352 } else {
353 switch (reg) {
354 case EVERGREEN_VLINE_START_END:
355 header &= ~R600_CP_PACKET0_REG_MASK;
356 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
357 ib[h_idx] = header;
358 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
359 break;
360 default:
361 DRM_ERROR("unknown crtc reloc\n");
362 r = -EINVAL;
363 goto out;
364 }
365 }
366 out:
367 return r;
368 }
369
370 static int evergreen_packet0_check(struct radeon_cs_parser *p,
371 struct radeon_cs_packet *pkt,
372 unsigned idx, unsigned reg)
373 {
374 int r;
375
376 switch (reg) {
377 case EVERGREEN_VLINE_START_END:
378 r = evergreen_cs_packet_parse_vline(p);
379 if (r) {
380 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
381 idx, reg);
382 return r;
383 }
384 break;
385 default:
386 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
387 reg, idx);
388 return -EINVAL;
389 }
390 return 0;
391 }
392
393 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
394 struct radeon_cs_packet *pkt)
395 {
396 unsigned reg, i;
397 unsigned idx;
398 int r;
399
400 idx = pkt->idx + 1;
401 reg = pkt->reg;
402 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
403 r = evergreen_packet0_check(p, pkt, idx, reg);
404 if (r) {
405 return r;
406 }
407 }
408 return 0;
409 }
410
411 /**
412 * evergreen_cs_check_reg() - check if register is authorized or not
413 * @parser: parser structure holding parsing context
414 * @reg: register we are testing
415 * @idx: index into the cs buffer
416 *
417 * This function will test against evergreen_reg_safe_bm and return 0
418 * if register is safe. If register is not flag as safe this function
419 * will test it against a list of register needind special handling.
420 */
421 static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
422 {
423 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
424 struct radeon_cs_reloc *reloc;
425 u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
426 u32 m, i, tmp, *ib;
427 int r;
428
429 i = (reg >> 7);
430 if (i > last_reg) {
431 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
432 return -EINVAL;
433 }
434 m = 1 << ((reg >> 2) & 31);
435 if (!(evergreen_reg_safe_bm[i] & m))
436 return 0;
437 ib = p->ib->ptr;
438 switch (reg) {
439 /* force following reg to 0 in an attemp to disable out buffer
440 * which will need us to better understand how it works to perform
441 * security check on it (Jerome)
442 */
443 case SQ_ESGS_RING_SIZE:
444 case SQ_GSVS_RING_SIZE:
445 case SQ_ESTMP_RING_SIZE:
446 case SQ_GSTMP_RING_SIZE:
447 case SQ_HSTMP_RING_SIZE:
448 case SQ_LSTMP_RING_SIZE:
449 case SQ_PSTMP_RING_SIZE:
450 case SQ_VSTMP_RING_SIZE:
451 case SQ_ESGS_RING_ITEMSIZE:
452 case SQ_ESTMP_RING_ITEMSIZE:
453 case SQ_GSTMP_RING_ITEMSIZE:
454 case SQ_GSVS_RING_ITEMSIZE:
455 case SQ_GS_VERT_ITEMSIZE:
456 case SQ_GS_VERT_ITEMSIZE_1:
457 case SQ_GS_VERT_ITEMSIZE_2:
458 case SQ_GS_VERT_ITEMSIZE_3:
459 case SQ_GSVS_RING_OFFSET_1:
460 case SQ_GSVS_RING_OFFSET_2:
461 case SQ_GSVS_RING_OFFSET_3:
462 case SQ_HSTMP_RING_ITEMSIZE:
463 case SQ_LSTMP_RING_ITEMSIZE:
464 case SQ_PSTMP_RING_ITEMSIZE:
465 case SQ_VSTMP_RING_ITEMSIZE:
466 case VGT_TF_RING_SIZE:
467 /* get value to populate the IB don't remove */
468 tmp =radeon_get_ib_value(p, idx);
469 ib[idx] = 0;
470 break;
471 case DB_DEPTH_CONTROL:
472 track->db_depth_control = radeon_get_ib_value(p, idx);
473 break;
474 case DB_Z_INFO:
475 r = evergreen_cs_packet_next_reloc(p, &reloc);
476 if (r) {
477 dev_warn(p->dev, "bad SET_CONTEXT_REG "
478 "0x%04X\n", reg);
479 return -EINVAL;
480 }
481 track->db_z_info = radeon_get_ib_value(p, idx);
482 ib[idx] &= ~Z_ARRAY_MODE(0xf);
483 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
484 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
485 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
486 track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
487 } else {
488 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
489 track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
490 }
491 break;
492 case DB_STENCIL_INFO:
493 track->db_s_info = radeon_get_ib_value(p, idx);
494 break;
495 case DB_DEPTH_VIEW:
496 track->db_depth_view = radeon_get_ib_value(p, idx);
497 break;
498 case DB_DEPTH_SIZE:
499 track->db_depth_size = radeon_get_ib_value(p, idx);
500 track->db_depth_size_idx = idx;
501 break;
502 case DB_Z_READ_BASE:
503 r = evergreen_cs_packet_next_reloc(p, &reloc);
504 if (r) {
505 dev_warn(p->dev, "bad SET_CONTEXT_REG "
506 "0x%04X\n", reg);
507 return -EINVAL;
508 }
509 track->db_z_read_offset = radeon_get_ib_value(p, idx);
510 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
511 track->db_z_read_bo = reloc->robj;
512 break;
513 case DB_Z_WRITE_BASE:
514 r = evergreen_cs_packet_next_reloc(p, &reloc);
515 if (r) {
516 dev_warn(p->dev, "bad SET_CONTEXT_REG "
517 "0x%04X\n", reg);
518 return -EINVAL;
519 }
520 track->db_z_write_offset = radeon_get_ib_value(p, idx);
521 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
522 track->db_z_write_bo = reloc->robj;
523 break;
524 case DB_STENCIL_READ_BASE:
525 r = evergreen_cs_packet_next_reloc(p, &reloc);
526 if (r) {
527 dev_warn(p->dev, "bad SET_CONTEXT_REG "
528 "0x%04X\n", reg);
529 return -EINVAL;
530 }
531 track->db_s_read_offset = radeon_get_ib_value(p, idx);
532 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
533 track->db_s_read_bo = reloc->robj;
534 break;
535 case DB_STENCIL_WRITE_BASE:
536 r = evergreen_cs_packet_next_reloc(p, &reloc);
537 if (r) {
538 dev_warn(p->dev, "bad SET_CONTEXT_REG "
539 "0x%04X\n", reg);
540 return -EINVAL;
541 }
542 track->db_s_write_offset = radeon_get_ib_value(p, idx);
543 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
544 track->db_s_write_bo = reloc->robj;
545 break;
546 case VGT_STRMOUT_CONFIG:
547 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
548 break;
549 case VGT_STRMOUT_BUFFER_CONFIG:
550 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
551 break;
552 case CB_TARGET_MASK:
553 track->cb_target_mask = radeon_get_ib_value(p, idx);
554 break;
555 case CB_SHADER_MASK:
556 track->cb_shader_mask = radeon_get_ib_value(p, idx);
557 break;
558 case PA_SC_AA_CONFIG:
559 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
560 track->nsamples = 1 << tmp;
561 break;
562 case CB_COLOR0_VIEW:
563 case CB_COLOR1_VIEW:
564 case CB_COLOR2_VIEW:
565 case CB_COLOR3_VIEW:
566 case CB_COLOR4_VIEW:
567 case CB_COLOR5_VIEW:
568 case CB_COLOR6_VIEW:
569 case CB_COLOR7_VIEW:
570 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
571 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
572 break;
573 case CB_COLOR8_VIEW:
574 case CB_COLOR9_VIEW:
575 case CB_COLOR10_VIEW:
576 case CB_COLOR11_VIEW:
577 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
578 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
579 break;
580 case CB_COLOR0_INFO:
581 case CB_COLOR1_INFO:
582 case CB_COLOR2_INFO:
583 case CB_COLOR3_INFO:
584 case CB_COLOR4_INFO:
585 case CB_COLOR5_INFO:
586 case CB_COLOR6_INFO:
587 case CB_COLOR7_INFO:
588 r = evergreen_cs_packet_next_reloc(p, &reloc);
589 if (r) {
590 dev_warn(p->dev, "bad SET_CONTEXT_REG "
591 "0x%04X\n", reg);
592 return -EINVAL;
593 }
594 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
595 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
597 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
598 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
599 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
600 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
601 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
602 }
603 break;
604 case CB_COLOR8_INFO:
605 case CB_COLOR9_INFO:
606 case CB_COLOR10_INFO:
607 case CB_COLOR11_INFO:
608 r = evergreen_cs_packet_next_reloc(p, &reloc);
609 if (r) {
610 dev_warn(p->dev, "bad SET_CONTEXT_REG "
611 "0x%04X\n", reg);
612 return -EINVAL;
613 }
614 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
615 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
616 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
617 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
618 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
619 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
620 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
621 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
622 }
623 break;
624 case CB_COLOR0_PITCH:
625 case CB_COLOR1_PITCH:
626 case CB_COLOR2_PITCH:
627 case CB_COLOR3_PITCH:
628 case CB_COLOR4_PITCH:
629 case CB_COLOR5_PITCH:
630 case CB_COLOR6_PITCH:
631 case CB_COLOR7_PITCH:
632 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
633 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
634 track->cb_color_pitch_idx[tmp] = idx;
635 break;
636 case CB_COLOR8_PITCH:
637 case CB_COLOR9_PITCH:
638 case CB_COLOR10_PITCH:
639 case CB_COLOR11_PITCH:
640 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
641 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
642 track->cb_color_pitch_idx[tmp] = idx;
643 break;
644 case CB_COLOR0_SLICE:
645 case CB_COLOR1_SLICE:
646 case CB_COLOR2_SLICE:
647 case CB_COLOR3_SLICE:
648 case CB_COLOR4_SLICE:
649 case CB_COLOR5_SLICE:
650 case CB_COLOR6_SLICE:
651 case CB_COLOR7_SLICE:
652 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
653 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
654 track->cb_color_slice_idx[tmp] = idx;
655 break;
656 case CB_COLOR8_SLICE:
657 case CB_COLOR9_SLICE:
658 case CB_COLOR10_SLICE:
659 case CB_COLOR11_SLICE:
660 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
661 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
662 track->cb_color_slice_idx[tmp] = idx;
663 break;
664 case CB_COLOR0_ATTRIB:
665 case CB_COLOR1_ATTRIB:
666 case CB_COLOR2_ATTRIB:
667 case CB_COLOR3_ATTRIB:
668 case CB_COLOR4_ATTRIB:
669 case CB_COLOR5_ATTRIB:
670 case CB_COLOR6_ATTRIB:
671 case CB_COLOR7_ATTRIB:
672 case CB_COLOR8_ATTRIB:
673 case CB_COLOR9_ATTRIB:
674 case CB_COLOR10_ATTRIB:
675 case CB_COLOR11_ATTRIB:
676 break;
677 case CB_COLOR0_DIM:
678 case CB_COLOR1_DIM:
679 case CB_COLOR2_DIM:
680 case CB_COLOR3_DIM:
681 case CB_COLOR4_DIM:
682 case CB_COLOR5_DIM:
683 case CB_COLOR6_DIM:
684 case CB_COLOR7_DIM:
685 tmp = (reg - CB_COLOR0_DIM) / 0x3c;
686 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
687 track->cb_color_dim_idx[tmp] = idx;
688 break;
689 case CB_COLOR8_DIM:
690 case CB_COLOR9_DIM:
691 case CB_COLOR10_DIM:
692 case CB_COLOR11_DIM:
693 tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8;
694 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
695 track->cb_color_dim_idx[tmp] = idx;
696 break;
697 case CB_COLOR0_FMASK:
698 case CB_COLOR1_FMASK:
699 case CB_COLOR2_FMASK:
700 case CB_COLOR3_FMASK:
701 case CB_COLOR4_FMASK:
702 case CB_COLOR5_FMASK:
703 case CB_COLOR6_FMASK:
704 case CB_COLOR7_FMASK:
705 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
706 r = evergreen_cs_packet_next_reloc(p, &reloc);
707 if (r) {
708 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
709 return -EINVAL;
710 }
711 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
712 track->cb_color_fmask_bo[tmp] = reloc->robj;
713 break;
714 case CB_COLOR0_CMASK:
715 case CB_COLOR1_CMASK:
716 case CB_COLOR2_CMASK:
717 case CB_COLOR3_CMASK:
718 case CB_COLOR4_CMASK:
719 case CB_COLOR5_CMASK:
720 case CB_COLOR6_CMASK:
721 case CB_COLOR7_CMASK:
722 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
723 r = evergreen_cs_packet_next_reloc(p, &reloc);
724 if (r) {
725 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
726 return -EINVAL;
727 }
728 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
729 track->cb_color_cmask_bo[tmp] = reloc->robj;
730 break;
731 case CB_COLOR0_FMASK_SLICE:
732 case CB_COLOR1_FMASK_SLICE:
733 case CB_COLOR2_FMASK_SLICE:
734 case CB_COLOR3_FMASK_SLICE:
735 case CB_COLOR4_FMASK_SLICE:
736 case CB_COLOR5_FMASK_SLICE:
737 case CB_COLOR6_FMASK_SLICE:
738 case CB_COLOR7_FMASK_SLICE:
739 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
740 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
741 break;
742 case CB_COLOR0_CMASK_SLICE:
743 case CB_COLOR1_CMASK_SLICE:
744 case CB_COLOR2_CMASK_SLICE:
745 case CB_COLOR3_CMASK_SLICE:
746 case CB_COLOR4_CMASK_SLICE:
747 case CB_COLOR5_CMASK_SLICE:
748 case CB_COLOR6_CMASK_SLICE:
749 case CB_COLOR7_CMASK_SLICE:
750 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
751 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
752 break;
753 case CB_COLOR0_BASE:
754 case CB_COLOR1_BASE:
755 case CB_COLOR2_BASE:
756 case CB_COLOR3_BASE:
757 case CB_COLOR4_BASE:
758 case CB_COLOR5_BASE:
759 case CB_COLOR6_BASE:
760 case CB_COLOR7_BASE:
761 r = evergreen_cs_packet_next_reloc(p, &reloc);
762 if (r) {
763 dev_warn(p->dev, "bad SET_CONTEXT_REG "
764 "0x%04X\n", reg);
765 return -EINVAL;
766 }
767 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
768 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
769 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
770 track->cb_color_base_last[tmp] = ib[idx];
771 track->cb_color_bo[tmp] = reloc->robj;
772 break;
773 case CB_COLOR8_BASE:
774 case CB_COLOR9_BASE:
775 case CB_COLOR10_BASE:
776 case CB_COLOR11_BASE:
777 r = evergreen_cs_packet_next_reloc(p, &reloc);
778 if (r) {
779 dev_warn(p->dev, "bad SET_CONTEXT_REG "
780 "0x%04X\n", reg);
781 return -EINVAL;
782 }
783 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
784 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
785 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
786 track->cb_color_base_last[tmp] = ib[idx];
787 track->cb_color_bo[tmp] = reloc->robj;
788 break;
789 case CB_IMMED0_BASE:
790 case CB_IMMED1_BASE:
791 case CB_IMMED2_BASE:
792 case CB_IMMED3_BASE:
793 case CB_IMMED4_BASE:
794 case CB_IMMED5_BASE:
795 case CB_IMMED6_BASE:
796 case CB_IMMED7_BASE:
797 case CB_IMMED8_BASE:
798 case CB_IMMED9_BASE:
799 case CB_IMMED10_BASE:
800 case CB_IMMED11_BASE:
801 case DB_HTILE_DATA_BASE:
802 case SQ_PGM_START_FS:
803 case SQ_PGM_START_ES:
804 case SQ_PGM_START_VS:
805 case SQ_PGM_START_GS:
806 case SQ_PGM_START_PS:
807 case SQ_PGM_START_HS:
808 case SQ_PGM_START_LS:
809 case GDS_ADDR_BASE:
810 case SQ_CONST_MEM_BASE:
811 case SQ_ALU_CONST_CACHE_GS_0:
812 case SQ_ALU_CONST_CACHE_GS_1:
813 case SQ_ALU_CONST_CACHE_GS_2:
814 case SQ_ALU_CONST_CACHE_GS_3:
815 case SQ_ALU_CONST_CACHE_GS_4:
816 case SQ_ALU_CONST_CACHE_GS_5:
817 case SQ_ALU_CONST_CACHE_GS_6:
818 case SQ_ALU_CONST_CACHE_GS_7:
819 case SQ_ALU_CONST_CACHE_GS_8:
820 case SQ_ALU_CONST_CACHE_GS_9:
821 case SQ_ALU_CONST_CACHE_GS_10:
822 case SQ_ALU_CONST_CACHE_GS_11:
823 case SQ_ALU_CONST_CACHE_GS_12:
824 case SQ_ALU_CONST_CACHE_GS_13:
825 case SQ_ALU_CONST_CACHE_GS_14:
826 case SQ_ALU_CONST_CACHE_GS_15:
827 case SQ_ALU_CONST_CACHE_PS_0:
828 case SQ_ALU_CONST_CACHE_PS_1:
829 case SQ_ALU_CONST_CACHE_PS_2:
830 case SQ_ALU_CONST_CACHE_PS_3:
831 case SQ_ALU_CONST_CACHE_PS_4:
832 case SQ_ALU_CONST_CACHE_PS_5:
833 case SQ_ALU_CONST_CACHE_PS_6:
834 case SQ_ALU_CONST_CACHE_PS_7:
835 case SQ_ALU_CONST_CACHE_PS_8:
836 case SQ_ALU_CONST_CACHE_PS_9:
837 case SQ_ALU_CONST_CACHE_PS_10:
838 case SQ_ALU_CONST_CACHE_PS_11:
839 case SQ_ALU_CONST_CACHE_PS_12:
840 case SQ_ALU_CONST_CACHE_PS_13:
841 case SQ_ALU_CONST_CACHE_PS_14:
842 case SQ_ALU_CONST_CACHE_PS_15:
843 case SQ_ALU_CONST_CACHE_VS_0:
844 case SQ_ALU_CONST_CACHE_VS_1:
845 case SQ_ALU_CONST_CACHE_VS_2:
846 case SQ_ALU_CONST_CACHE_VS_3:
847 case SQ_ALU_CONST_CACHE_VS_4:
848 case SQ_ALU_CONST_CACHE_VS_5:
849 case SQ_ALU_CONST_CACHE_VS_6:
850 case SQ_ALU_CONST_CACHE_VS_7:
851 case SQ_ALU_CONST_CACHE_VS_8:
852 case SQ_ALU_CONST_CACHE_VS_9:
853 case SQ_ALU_CONST_CACHE_VS_10:
854 case SQ_ALU_CONST_CACHE_VS_11:
855 case SQ_ALU_CONST_CACHE_VS_12:
856 case SQ_ALU_CONST_CACHE_VS_13:
857 case SQ_ALU_CONST_CACHE_VS_14:
858 case SQ_ALU_CONST_CACHE_VS_15:
859 case SQ_ALU_CONST_CACHE_HS_0:
860 case SQ_ALU_CONST_CACHE_HS_1:
861 case SQ_ALU_CONST_CACHE_HS_2:
862 case SQ_ALU_CONST_CACHE_HS_3:
863 case SQ_ALU_CONST_CACHE_HS_4:
864 case SQ_ALU_CONST_CACHE_HS_5:
865 case SQ_ALU_CONST_CACHE_HS_6:
866 case SQ_ALU_CONST_CACHE_HS_7:
867 case SQ_ALU_CONST_CACHE_HS_8:
868 case SQ_ALU_CONST_CACHE_HS_9:
869 case SQ_ALU_CONST_CACHE_HS_10:
870 case SQ_ALU_CONST_CACHE_HS_11:
871 case SQ_ALU_CONST_CACHE_HS_12:
872 case SQ_ALU_CONST_CACHE_HS_13:
873 case SQ_ALU_CONST_CACHE_HS_14:
874 case SQ_ALU_CONST_CACHE_HS_15:
875 case SQ_ALU_CONST_CACHE_LS_0:
876 case SQ_ALU_CONST_CACHE_LS_1:
877 case SQ_ALU_CONST_CACHE_LS_2:
878 case SQ_ALU_CONST_CACHE_LS_3:
879 case SQ_ALU_CONST_CACHE_LS_4:
880 case SQ_ALU_CONST_CACHE_LS_5:
881 case SQ_ALU_CONST_CACHE_LS_6:
882 case SQ_ALU_CONST_CACHE_LS_7:
883 case SQ_ALU_CONST_CACHE_LS_8:
884 case SQ_ALU_CONST_CACHE_LS_9:
885 case SQ_ALU_CONST_CACHE_LS_10:
886 case SQ_ALU_CONST_CACHE_LS_11:
887 case SQ_ALU_CONST_CACHE_LS_12:
888 case SQ_ALU_CONST_CACHE_LS_13:
889 case SQ_ALU_CONST_CACHE_LS_14:
890 case SQ_ALU_CONST_CACHE_LS_15:
891 r = evergreen_cs_packet_next_reloc(p, &reloc);
892 if (r) {
893 dev_warn(p->dev, "bad SET_CONTEXT_REG "
894 "0x%04X\n", reg);
895 return -EINVAL;
896 }
897 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
898 break;
899 default:
900 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
901 return -EINVAL;
902 }
903 return 0;
904 }
905
906 /**
907 * evergreen_check_texture_resource() - check if register is authorized or not
908 * @p: parser structure holding parsing context
909 * @idx: index into the cs buffer
910 * @texture: texture's bo structure
911 * @mipmap: mipmap's bo structure
912 *
913 * This function will check that the resource has valid field and that
914 * the texture and mipmap bo object are big enough to cover this resource.
915 */
916 static inline int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
917 struct radeon_bo *texture,
918 struct radeon_bo *mipmap)
919 {
920 return 0;
921 }
922
923 static int evergreen_packet3_check(struct radeon_cs_parser *p,
924 struct radeon_cs_packet *pkt)
925 {
926 struct radeon_cs_reloc *reloc;
927 struct evergreen_cs_track *track;
928 volatile u32 *ib;
929 unsigned idx;
930 unsigned i;
931 unsigned start_reg, end_reg, reg;
932 int r;
933 u32 idx_value;
934
935 track = (struct evergreen_cs_track *)p->track;
936 ib = p->ib->ptr;
937 idx = pkt->idx + 1;
938 idx_value = radeon_get_ib_value(p, idx);
939
940 switch (pkt->opcode) {
941 case PACKET3_CONTEXT_CONTROL:
942 if (pkt->count != 1) {
943 DRM_ERROR("bad CONTEXT_CONTROL\n");
944 return -EINVAL;
945 }
946 break;
947 case PACKET3_INDEX_TYPE:
948 case PACKET3_NUM_INSTANCES:
949 case PACKET3_CLEAR_STATE:
950 if (pkt->count) {
951 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
952 return -EINVAL;
953 }
954 break;
955 case PACKET3_INDEX_BASE:
956 if (pkt->count != 1) {
957 DRM_ERROR("bad INDEX_BASE\n");
958 return -EINVAL;
959 }
960 r = evergreen_cs_packet_next_reloc(p, &reloc);
961 if (r) {
962 DRM_ERROR("bad INDEX_BASE\n");
963 return -EINVAL;
964 }
965 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
966 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
967 r = evergreen_cs_track_check(p);
968 if (r) {
969 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
970 return r;
971 }
972 break;
973 case PACKET3_DRAW_INDEX:
974 if (pkt->count != 3) {
975 DRM_ERROR("bad DRAW_INDEX\n");
976 return -EINVAL;
977 }
978 r = evergreen_cs_packet_next_reloc(p, &reloc);
979 if (r) {
980 DRM_ERROR("bad DRAW_INDEX\n");
981 return -EINVAL;
982 }
983 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
984 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
985 r = evergreen_cs_track_check(p);
986 if (r) {
987 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
988 return r;
989 }
990 break;
991 case PACKET3_DRAW_INDEX_2:
992 if (pkt->count != 4) {
993 DRM_ERROR("bad DRAW_INDEX_2\n");
994 return -EINVAL;
995 }
996 r = evergreen_cs_packet_next_reloc(p, &reloc);
997 if (r) {
998 DRM_ERROR("bad DRAW_INDEX_2\n");
999 return -EINVAL;
1000 }
1001 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1002 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1003 r = evergreen_cs_track_check(p);
1004 if (r) {
1005 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1006 return r;
1007 }
1008 break;
1009 case PACKET3_DRAW_INDEX_AUTO:
1010 if (pkt->count != 1) {
1011 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1012 return -EINVAL;
1013 }
1014 r = evergreen_cs_track_check(p);
1015 if (r) {
1016 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1017 return r;
1018 }
1019 break;
1020 case PACKET3_DRAW_INDEX_MULTI_AUTO:
1021 if (pkt->count != 2) {
1022 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1023 return -EINVAL;
1024 }
1025 r = evergreen_cs_track_check(p);
1026 if (r) {
1027 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1028 return r;
1029 }
1030 break;
1031 case PACKET3_DRAW_INDEX_IMMD:
1032 if (pkt->count < 2) {
1033 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1034 return -EINVAL;
1035 }
1036 r = evergreen_cs_track_check(p);
1037 if (r) {
1038 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1039 return r;
1040 }
1041 break;
1042 case PACKET3_DRAW_INDEX_OFFSET:
1043 if (pkt->count != 2) {
1044 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1045 return -EINVAL;
1046 }
1047 r = evergreen_cs_track_check(p);
1048 if (r) {
1049 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1050 return r;
1051 }
1052 break;
1053 case PACKET3_DRAW_INDEX_OFFSET_2:
1054 if (pkt->count != 3) {
1055 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
1056 return -EINVAL;
1057 }
1058 r = evergreen_cs_track_check(p);
1059 if (r) {
1060 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1061 return r;
1062 }
1063 break;
1064 case PACKET3_WAIT_REG_MEM:
1065 if (pkt->count != 5) {
1066 DRM_ERROR("bad WAIT_REG_MEM\n");
1067 return -EINVAL;
1068 }
1069 /* bit 4 is reg (0) or mem (1) */
1070 if (idx_value & 0x10) {
1071 r = evergreen_cs_packet_next_reloc(p, &reloc);
1072 if (r) {
1073 DRM_ERROR("bad WAIT_REG_MEM\n");
1074 return -EINVAL;
1075 }
1076 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1077 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1078 }
1079 break;
1080 case PACKET3_SURFACE_SYNC:
1081 if (pkt->count != 3) {
1082 DRM_ERROR("bad SURFACE_SYNC\n");
1083 return -EINVAL;
1084 }
1085 /* 0xffffffff/0x0 is flush all cache flag */
1086 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1087 radeon_get_ib_value(p, idx + 2) != 0) {
1088 r = evergreen_cs_packet_next_reloc(p, &reloc);
1089 if (r) {
1090 DRM_ERROR("bad SURFACE_SYNC\n");
1091 return -EINVAL;
1092 }
1093 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1094 }
1095 break;
1096 case PACKET3_EVENT_WRITE:
1097 if (pkt->count != 2 && pkt->count != 0) {
1098 DRM_ERROR("bad EVENT_WRITE\n");
1099 return -EINVAL;
1100 }
1101 if (pkt->count) {
1102 r = evergreen_cs_packet_next_reloc(p, &reloc);
1103 if (r) {
1104 DRM_ERROR("bad EVENT_WRITE\n");
1105 return -EINVAL;
1106 }
1107 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1108 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1109 }
1110 break;
1111 case PACKET3_EVENT_WRITE_EOP:
1112 if (pkt->count != 4) {
1113 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1114 return -EINVAL;
1115 }
1116 r = evergreen_cs_packet_next_reloc(p, &reloc);
1117 if (r) {
1118 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1119 return -EINVAL;
1120 }
1121 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1122 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1123 break;
1124 case PACKET3_EVENT_WRITE_EOS:
1125 if (pkt->count != 3) {
1126 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1127 return -EINVAL;
1128 }
1129 r = evergreen_cs_packet_next_reloc(p, &reloc);
1130 if (r) {
1131 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1132 return -EINVAL;
1133 }
1134 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1135 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1136 break;
1137 case PACKET3_SET_CONFIG_REG:
1138 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
1139 end_reg = 4 * pkt->count + start_reg - 4;
1140 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
1141 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1142 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1143 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1144 return -EINVAL;
1145 }
1146 for (i = 0; i < pkt->count; i++) {
1147 reg = start_reg + (4 * i);
1148 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1149 if (r)
1150 return r;
1151 }
1152 break;
1153 case PACKET3_SET_CONTEXT_REG:
1154 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
1155 end_reg = 4 * pkt->count + start_reg - 4;
1156 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
1157 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1158 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1159 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1160 return -EINVAL;
1161 }
1162 for (i = 0; i < pkt->count; i++) {
1163 reg = start_reg + (4 * i);
1164 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1165 if (r)
1166 return r;
1167 }
1168 break;
1169 case PACKET3_SET_RESOURCE:
1170 if (pkt->count % 8) {
1171 DRM_ERROR("bad SET_RESOURCE\n");
1172 return -EINVAL;
1173 }
1174 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
1175 end_reg = 4 * pkt->count + start_reg - 4;
1176 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
1177 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1178 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1179 DRM_ERROR("bad SET_RESOURCE\n");
1180 return -EINVAL;
1181 }
1182 for (i = 0; i < (pkt->count / 8); i++) {
1183 struct radeon_bo *texture, *mipmap;
1184 u32 size, offset;
1185
1186 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
1187 case SQ_TEX_VTX_VALID_TEXTURE:
1188 /* tex base */
1189 r = evergreen_cs_packet_next_reloc(p, &reloc);
1190 if (r) {
1191 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1192 return -EINVAL;
1193 }
1194 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1195 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1196 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
1197 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1198 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
1199 texture = reloc->robj;
1200 /* tex mip base */
1201 r = evergreen_cs_packet_next_reloc(p, &reloc);
1202 if (r) {
1203 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1204 return -EINVAL;
1205 }
1206 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1207 mipmap = reloc->robj;
1208 r = evergreen_check_texture_resource(p, idx+1+(i*8),
1209 texture, mipmap);
1210 if (r)
1211 return r;
1212 break;
1213 case SQ_TEX_VTX_VALID_BUFFER:
1214 /* vtx base */
1215 r = evergreen_cs_packet_next_reloc(p, &reloc);
1216 if (r) {
1217 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
1218 return -EINVAL;
1219 }
1220 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
1221 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
1222 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1223 /* force size to size of the buffer */
1224 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1225 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1226 }
1227 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1228 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1229 break;
1230 case SQ_TEX_VTX_INVALID_TEXTURE:
1231 case SQ_TEX_VTX_INVALID_BUFFER:
1232 default:
1233 DRM_ERROR("bad SET_RESOURCE\n");
1234 return -EINVAL;
1235 }
1236 }
1237 break;
1238 case PACKET3_SET_ALU_CONST:
1239 break;
1240 case PACKET3_SET_BOOL_CONST:
1241 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
1242 end_reg = 4 * pkt->count + start_reg - 4;
1243 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
1244 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1245 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1246 DRM_ERROR("bad SET_BOOL_CONST\n");
1247 return -EINVAL;
1248 }
1249 break;
1250 case PACKET3_SET_LOOP_CONST:
1251 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
1252 end_reg = 4 * pkt->count + start_reg - 4;
1253 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
1254 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1255 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1256 DRM_ERROR("bad SET_LOOP_CONST\n");
1257 return -EINVAL;
1258 }
1259 break;
1260 case PACKET3_SET_CTL_CONST:
1261 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
1262 end_reg = 4 * pkt->count + start_reg - 4;
1263 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
1264 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1265 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1266 DRM_ERROR("bad SET_CTL_CONST\n");
1267 return -EINVAL;
1268 }
1269 break;
1270 case PACKET3_SET_SAMPLER:
1271 if (pkt->count % 3) {
1272 DRM_ERROR("bad SET_SAMPLER\n");
1273 return -EINVAL;
1274 }
1275 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
1276 end_reg = 4 * pkt->count + start_reg - 4;
1277 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
1278 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1279 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1280 DRM_ERROR("bad SET_SAMPLER\n");
1281 return -EINVAL;
1282 }
1283 break;
1284 case PACKET3_NOP:
1285 break;
1286 default:
1287 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1288 return -EINVAL;
1289 }
1290 return 0;
1291 }
1292
1293 int evergreen_cs_parse(struct radeon_cs_parser *p)
1294 {
1295 struct radeon_cs_packet pkt;
1296 struct evergreen_cs_track *track;
1297 int r;
1298
1299 if (p->track == NULL) {
1300 /* initialize tracker, we are in kms */
1301 track = kzalloc(sizeof(*track), GFP_KERNEL);
1302 if (track == NULL)
1303 return -ENOMEM;
1304 evergreen_cs_track_init(track);
1305 track->npipes = p->rdev->config.evergreen.tiling_npipes;
1306 track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
1307 track->group_size = p->rdev->config.evergreen.tiling_group_size;
1308 p->track = track;
1309 }
1310 do {
1311 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
1312 if (r) {
1313 kfree(p->track);
1314 p->track = NULL;
1315 return r;
1316 }
1317 p->idx += pkt.count + 2;
1318 switch (pkt.type) {
1319 case PACKET_TYPE0:
1320 r = evergreen_cs_parse_packet0(p, &pkt);
1321 break;
1322 case PACKET_TYPE2:
1323 break;
1324 case PACKET_TYPE3:
1325 r = evergreen_packet3_check(p, &pkt);
1326 break;
1327 default:
1328 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1329 kfree(p->track);
1330 p->track = NULL;
1331 return -EINVAL;
1332 }
1333 if (r) {
1334 kfree(p->track);
1335 p->track = NULL;
1336 return r;
1337 }
1338 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1339 kfree(p->track);
1340 p->track = NULL;
1341 return 0;
1342 }
Tomato firmware and modifications.