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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / ata / sata_fsl.c
blob5dba799ee1ff08033ecf7feb12a17a26d9a33d03
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_platform.h>
28
29 /* Controller information */
30 enum {
31 SATA_FSL_QUEUE_DEPTH = 16,
32 SATA_FSL_MAX_PRD = 63,
33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
35
36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
37 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
38 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
39
40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
43
44 /*
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contiguous) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
52 */
53
54 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
57 SATA_FSL_CMD_DESC_RSRVD = 16,
58
59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
60 SATA_FSL_CMD_DESC_SFIS_SZ +
61 SATA_FSL_CMD_DESC_ACMD_SZ +
62 SATA_FSL_CMD_DESC_RSRVD +
63 SATA_FSL_MAX_PRD * 16),
64
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
66 (SATA_FSL_CMD_DESC_CFIS_SZ +
67 SATA_FSL_CMD_DESC_SFIS_SZ +
68 SATA_FSL_CMD_DESC_ACMD_SZ +
69 SATA_FSL_CMD_DESC_RSRVD),
70
71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
73 SATA_FSL_CMD_DESC_AR_SZ),
74
75 /*
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
79 */
80
81 SATA_FSL_MAX_PORTS = 1,
82
83 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
84 };
85
86 /*
87 * Host Controller command register set - per port
88 */
89 enum {
90 CQ = 0,
91 CA = 8,
92 CC = 0x10,
93 CE = 0x18,
94 DE = 0x20,
95 CHBA = 0x24,
96 HSTATUS = 0x28,
97 HCONTROL = 0x2C,
98 CQPMP = 0x30,
99 SIGNATURE = 0x34,
100 ICC = 0x38,
101
102 /*
103 * Host Status Register (HStatus) bitdefs
104 */
105 ONLINE = (1 << 31),
106 GOING_OFFLINE = (1 << 30),
107 BIST_ERR = (1 << 29),
108
109 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
113 FATAL_ERR_DATA_OVERRUN = (1 << 12),
114 FATAL_ERR_CRC_ERR_TX = (1 << 11),
115 FATAL_ERR_CRC_ERR_RX = (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
118
119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
120 FATAL_ERR_PARITY_ERR_TX |
121 FATAL_ERR_PARITY_ERR_RX |
122 FATAL_ERR_DATA_UNDERRUN |
123 FATAL_ERR_DATA_OVERRUN |
124 FATAL_ERR_CRC_ERR_TX |
125 FATAL_ERR_CRC_ERR_RX |
126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
127
128 INT_ON_FATAL_ERR = (1 << 5),
129 INT_ON_PHYRDY_CHG = (1 << 4),
130
131 INT_ON_SIGNATURE_UPDATE = (1 << 3),
132 INT_ON_SNOTIFY_UPDATE = (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
134 INT_ON_CMD_COMPLETE = 1,
135
136 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
138
139 /*
140 * Host Control Register (HControl) bitdefs
141 */
142 HCONTROL_ONLINE_PHY_RST = (1 << 31),
143 HCONTROL_FORCE_OFFLINE = (1 << 30),
144 HCONTROL_PARITY_PROT_MOD = (1 << 14),
145 HCONTROL_DPATH_PARITY = (1 << 12),
146 HCONTROL_SNOOP_ENABLE = (1 << 10),
147 HCONTROL_PMP_ATTACHED = (1 << 9),
148 HCONTROL_COPYOUT_STATFIS = (1 << 8),
149 IE_ON_FATAL_ERR = (1 << 5),
150 IE_ON_PHYRDY_CHG = (1 << 4),
151 IE_ON_SIGNATURE_UPDATE = (1 << 3),
152 IE_ON_SNOTIFY_UPDATE = (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
154 IE_ON_CMD_COMPLETE = 1,
155
156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
157 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
159
160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
161 DATA_SNOOP_ENABLE = (1 << 22),
162 };
163
164 /*
165 * SATA Superset Registers
166 */
167 enum {
168 SSTATUS = 0,
169 SERROR = 4,
170 SCONTROL = 8,
171 SNOTIFY = 0xC,
172 };
173
174 /*
175 * Control Status Register Set
176 */
177 enum {
178 TRANSCFG = 0,
179 TRANSSTATUS = 4,
180 LINKCFG = 8,
181 LINKCFG1 = 0xC,
182 LINKCFG2 = 0x10,
183 LINKSTATUS = 0x14,
184 LINKSTATUS1 = 0x18,
185 PHYCTRLCFG = 0x1C,
186 COMMANDSTAT = 0x20,
187 };
188
189 /* PHY (link-layer) configuration control */
190 enum {
191 PHY_BIST_ENABLE = 0x01,
192 };
193
194 /*
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
197 */
198 struct cmdhdr_tbl_entry {
199 u32 cda;
200 u32 prde_fis_len;
201 u32 ttl;
202 u32 desc_info;
203 };
204
205 /*
206 * Description information bitdefs
207 */
208 enum {
209 CMD_DESC_RES = (1 << 11),
210 VENDOR_SPECIFIC_BIST = (1 << 10),
211 CMD_DESC_SNOOP_ENABLE = (1 << 9),
212 FPDMA_QUEUED_CMD = (1 << 8),
213 SRST_CMD = (1 << 7),
214 BIST = (1 << 6),
215 ATAPI_CMD = (1 << 5),
216 };
217
218 /*
219 * Command Descriptor
220 */
221 struct command_desc {
222 u8 cfis[8 * 4];
223 u8 sfis[8 * 4];
224 u8 acmd[4 * 4];
225 u8 fill[4 * 4];
226 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
227 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
228 };
229
230 /*
231 * Physical region table descriptor(PRD)
232 */
233
234 struct prde {
235 u32 dba;
236 u8 fill[2 * 4];
237 u32 ddc_and_ext;
238 };
239
240 /*
241 * ata_port private data
242 * This is our per-port instance data.
243 */
244 struct sata_fsl_port_priv {
245 struct cmdhdr_tbl_entry *cmdslot;
246 dma_addr_t cmdslot_paddr;
247 struct command_desc *cmdentry;
248 dma_addr_t cmdentry_paddr;
249 };
250
251 /*
252 * ata_port->host_set private data
253 */
254 struct sata_fsl_host_priv {
255 void __iomem *hcr_base;
256 void __iomem *ssr_base;
257 void __iomem *csr_base;
258 int irq;
259 };
260
261 static inline unsigned int sata_fsl_tag(unsigned int tag,
262 void __iomem *hcr_base)
263 {
264 /* We let libATA core do actual (queue) tag allocation */
265
266 /* all non NCQ/queued commands should have tag#0 */
267 if (ata_tag_internal(tag)) {
268 DPRINTK("mapping internal cmds to tag#0\n");
269 return 0;
270 }
271
272 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
273 DPRINTK("tag %d invalid : out of range\n", tag);
274 return 0;
275 }
276
277 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
278 DPRINTK("tag %d invalid : in use!!\n", tag);
279 return 0;
280 }
281
282 return tag;
283 }
284
285 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
286 unsigned int tag, u32 desc_info,
287 u32 data_xfer_len, u8 num_prde,
288 u8 fis_len)
289 {
290 dma_addr_t cmd_descriptor_address;
291
292 cmd_descriptor_address = pp->cmdentry_paddr +
293 tag * SATA_FSL_CMD_DESC_SIZE;
294
295 /* NOTE: both data_xfer_len & fis_len are Dword counts */
296
297 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
298 pp->cmdslot[tag].prde_fis_len =
299 cpu_to_le32((num_prde << 16) | (fis_len << 2));
300 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
301 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
302
303 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
304 pp->cmdslot[tag].cda,
305 pp->cmdslot[tag].prde_fis_len,
306 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
307
308 }
309
310 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
311 u32 *ttl, dma_addr_t cmd_desc_paddr)
312 {
313 struct scatterlist *sg;
314 unsigned int num_prde = 0;
315 u32 ttl_dwords = 0;
316
317 /*
318 * NOTE : direct & indirect prdt's are contiguously allocated
319 */
320 struct prde *prd = (struct prde *)&((struct command_desc *)
321 cmd_desc)->prdt;
322
323 struct prde *prd_ptr_to_indirect_ext = NULL;
324 unsigned indirect_ext_segment_sz = 0;
325 dma_addr_t indirect_ext_segment_paddr;
326 unsigned int si;
327
328 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
329
330 indirect_ext_segment_paddr = cmd_desc_paddr +
331 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
332
333 for_each_sg(qc->sg, sg, qc->n_elem, si) {
334 dma_addr_t sg_addr = sg_dma_address(sg);
335 u32 sg_len = sg_dma_len(sg);
336
337 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
338 (unsigned long long)sg_addr, sg_len);
339
340 /* warn if each s/g element is not dword aligned */
341 if (sg_addr & 0x03)
342 ata_port_printk(qc->ap, KERN_ERR,
343 "s/g addr unaligned : 0x%llx\n",
344 (unsigned long long)sg_addr);
345 if (sg_len & 0x03)
346 ata_port_printk(qc->ap, KERN_ERR,
347 "s/g len unaligned : 0x%x\n", sg_len);
348
349 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
350 sg_next(sg) != NULL) {
351 VPRINTK("setting indirect prde\n");
352 prd_ptr_to_indirect_ext = prd;
353 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
354 indirect_ext_segment_sz = 0;
355 ++prd;
356 ++num_prde;
357 }
358
359 ttl_dwords += sg_len;
360 prd->dba = cpu_to_le32(sg_addr);
361 prd->ddc_and_ext =
362 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
363
364 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
365 ttl_dwords, prd->dba, prd->ddc_and_ext);
366
367 ++num_prde;
368 ++prd;
369 if (prd_ptr_to_indirect_ext)
370 indirect_ext_segment_sz += sg_len;
371 }
372
373 if (prd_ptr_to_indirect_ext) {
374 /* set indirect extension flag along with indirect ext. size */
375 prd_ptr_to_indirect_ext->ddc_and_ext =
376 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
377 DATA_SNOOP_ENABLE |
378 (indirect_ext_segment_sz & ~0x03)));
379 }
380
381 *ttl = ttl_dwords;
382 return num_prde;
383 }
384
385 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
386 {
387 struct ata_port *ap = qc->ap;
388 struct sata_fsl_port_priv *pp = ap->private_data;
389 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
390 void __iomem *hcr_base = host_priv->hcr_base;
391 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
392 struct command_desc *cd;
393 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
394 u32 num_prde = 0;
395 u32 ttl_dwords = 0;
396 dma_addr_t cd_paddr;
397
398 cd = (struct command_desc *)pp->cmdentry + tag;
399 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
400
401 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
402
403 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
404 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
405
406 if (qc->tf.protocol == ATA_PROT_NCQ) {
407 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
408 cd->cfis[3], cd->cfis[11]);
409 }
410
411 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
412 if (ata_is_atapi(qc->tf.protocol)) {
413 desc_info |= ATAPI_CMD;
414 memset((void *)&cd->acmd, 0, 32);
415 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
416 }
417
418 if (qc->flags & ATA_QCFLAG_DMAMAP)
419 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
420 &ttl_dwords, cd_paddr);
421
422 if (qc->tf.protocol == ATA_PROT_NCQ)
423 desc_info |= FPDMA_QUEUED_CMD;
424
425 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
426 num_prde, 5);
427
428 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
429 desc_info, ttl_dwords, num_prde);
430 }
431
432 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
433 {
434 struct ata_port *ap = qc->ap;
435 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
436 void __iomem *hcr_base = host_priv->hcr_base;
437 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
438
439 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
440 ioread32(CQ + hcr_base),
441 ioread32(CA + hcr_base),
442 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
443
444 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
445
446 /* Simply queue command to the controller/device */
447 iowrite32(1 << tag, CQ + hcr_base);
448
449 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
450 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
451
452 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
453 ioread32(CE + hcr_base),
454 ioread32(DE + hcr_base),
455 ioread32(CC + hcr_base),
456 ioread32(COMMANDSTAT + host_priv->csr_base));
457
458 return 0;
459 }
460
461 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
462 {
463 struct sata_fsl_port_priv *pp = qc->ap->private_data;
464 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
465 void __iomem *hcr_base = host_priv->hcr_base;
466 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
467 struct command_desc *cd;
468
469 cd = pp->cmdentry + tag;
470
471 ata_tf_from_fis(cd->sfis, &qc->result_tf);
472 return true;
473 }
474
475 static int sata_fsl_scr_write(struct ata_link *link,
476 unsigned int sc_reg_in, u32 val)
477 {
478 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
479 void __iomem *ssr_base = host_priv->ssr_base;
480 unsigned int sc_reg;
481
482 switch (sc_reg_in) {
483 case SCR_STATUS:
484 case SCR_ERROR:
485 case SCR_CONTROL:
486 case SCR_ACTIVE:
487 sc_reg = sc_reg_in;
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
494
495 iowrite32(val, ssr_base + (sc_reg * 4));
496 return 0;
497 }
498
499 static int sata_fsl_scr_read(struct ata_link *link,
500 unsigned int sc_reg_in, u32 *val)
501 {
502 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
503 void __iomem *ssr_base = host_priv->ssr_base;
504 unsigned int sc_reg;
505
506 switch (sc_reg_in) {
507 case SCR_STATUS:
508 case SCR_ERROR:
509 case SCR_CONTROL:
510 case SCR_ACTIVE:
511 sc_reg = sc_reg_in;
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
518
519 *val = ioread32(ssr_base + (sc_reg * 4));
520 return 0;
521 }
522
523 static void sata_fsl_freeze(struct ata_port *ap)
524 {
525 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
526 void __iomem *hcr_base = host_priv->hcr_base;
527 u32 temp;
528
529 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
530 ioread32(CQ + hcr_base),
531 ioread32(CA + hcr_base),
532 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
533 VPRINTK("CmdStat = 0x%x\n",
534 ioread32(host_priv->csr_base + COMMANDSTAT));
535
536 /* disable interrupts on the controller/port */
537 temp = ioread32(hcr_base + HCONTROL);
538 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
539
540 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
541 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
542 }
543
544 static void sata_fsl_thaw(struct ata_port *ap)
545 {
546 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
547 void __iomem *hcr_base = host_priv->hcr_base;
548 u32 temp;
549
550 /* ack. any pending IRQs for this controller/port */
551 temp = ioread32(hcr_base + HSTATUS);
552
553 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
554
555 if (temp & 0x3F)
556 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
557
558 /* enable interrupts on the controller/port */
559 temp = ioread32(hcr_base + HCONTROL);
560 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
561
562 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
563 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
564 }
565
566 static void sata_fsl_pmp_attach(struct ata_port *ap)
567 {
568 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
569 void __iomem *hcr_base = host_priv->hcr_base;
570 u32 temp;
571
572 temp = ioread32(hcr_base + HCONTROL);
573 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
574 }
575
576 static void sata_fsl_pmp_detach(struct ata_port *ap)
577 {
578 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
579 void __iomem *hcr_base = host_priv->hcr_base;
580 u32 temp;
581
582 temp = ioread32(hcr_base + HCONTROL);
583 temp &= ~HCONTROL_PMP_ATTACHED;
584 iowrite32(temp, hcr_base + HCONTROL);
585
586 /* enable interrupts on the controller/port */
587 temp = ioread32(hcr_base + HCONTROL);
588 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
589
590 }
591
592 static int sata_fsl_port_start(struct ata_port *ap)
593 {
594 struct device *dev = ap->host->dev;
595 struct sata_fsl_port_priv *pp;
596 void *mem;
597 dma_addr_t mem_dma;
598 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
599 void __iomem *hcr_base = host_priv->hcr_base;
600 u32 temp;
601
602 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
603 if (!pp)
604 return -ENOMEM;
605
606 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
607 GFP_KERNEL);
608 if (!mem) {
609 kfree(pp);
610 return -ENOMEM;
611 }
612 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
613
614 pp->cmdslot = mem;
615 pp->cmdslot_paddr = mem_dma;
616
617 mem += SATA_FSL_CMD_SLOT_SIZE;
618 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
619
620 pp->cmdentry = mem;
621 pp->cmdentry_paddr = mem_dma;
622
623 ap->private_data = pp;
624
625 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
626 pp->cmdslot_paddr, pp->cmdentry_paddr);
627
628 /* Now, update the CHBA register in host controller cmd register set */
629 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
630
631 /*
632 * Now, we can bring the controller on-line & also initiate
633 * the COMINIT sequence, we simply return here and the boot-probing
634 * & device discovery process is re-initiated by libATA using a
635 * Softreset EH (dummy) session. Hence, boot probing and device
636 * discovey will be part of sata_fsl_softreset() callback.
637 */
638
639 temp = ioread32(hcr_base + HCONTROL);
640 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
641
642 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
643 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
644 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
645
646 #ifdef CONFIG_MPC8315_DS
647 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
648 temp &= ~(0xF << 4);
649 temp |= (0x1 << 4);
650 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
651
652 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
653 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
654 temp);
655 #endif
656
657 return 0;
658 }
659
660 static void sata_fsl_port_stop(struct ata_port *ap)
661 {
662 struct device *dev = ap->host->dev;
663 struct sata_fsl_port_priv *pp = ap->private_data;
664 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
665 void __iomem *hcr_base = host_priv->hcr_base;
666 u32 temp;
667
668 /*
669 * Force host controller to go off-line, aborting current operations
670 */
671 temp = ioread32(hcr_base + HCONTROL);
672 temp &= ~HCONTROL_ONLINE_PHY_RST;
673 temp |= HCONTROL_FORCE_OFFLINE;
674 iowrite32(temp, hcr_base + HCONTROL);
675
676 /* Poll for controller to go offline - should happen immediately */
677 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
678
679 ap->private_data = NULL;
680 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
681 pp->cmdslot, pp->cmdslot_paddr);
682
683 kfree(pp);
684 }
685
686 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
687 {
688 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
689 void __iomem *hcr_base = host_priv->hcr_base;
690 struct ata_taskfile tf;
691 u32 temp;
692
693 temp = ioread32(hcr_base + SIGNATURE);
694
695 VPRINTK("raw sig = 0x%x\n", temp);
696 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
697 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
698
699 tf.lbah = (temp >> 24) & 0xff;
700 tf.lbam = (temp >> 16) & 0xff;
701 tf.lbal = (temp >> 8) & 0xff;
702 tf.nsect = temp & 0xff;
703
704 return ata_dev_classify(&tf);
705 }
706
707 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
708 unsigned long deadline)
709 {
710 struct ata_port *ap = link->ap;
711 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
712 void __iomem *hcr_base = host_priv->hcr_base;
713 u32 temp;
714 int i = 0;
715 unsigned long start_jiffies;
716
717 DPRINTK("in xx_hardreset\n");
718
719 try_offline_again:
720 /*
721 * Force host controller to go off-line, aborting current operations
722 */
723 temp = ioread32(hcr_base + HCONTROL);
724 temp &= ~HCONTROL_ONLINE_PHY_RST;
725 iowrite32(temp, hcr_base + HCONTROL);
726
727 /* Poll for controller to go offline */
728 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
729
730 if (temp & ONLINE) {
731 ata_port_printk(ap, KERN_ERR,
732 "Hardreset failed, not off-lined %d\n", i);
733
734 /*
735 * Try to offline controller atleast twice
736 */
737 i++;
738 if (i == 2)
739 goto err;
740 else
741 goto try_offline_again;
742 }
743
744 DPRINTK("hardreset, controller off-lined\n");
745 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
746 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
747
748 /*
749 * PHY reset should remain asserted for atleast 1ms
750 */
751 msleep(1);
752
753 /*
754 * Now, bring the host controller online again, this can take time
755 * as PHY reset and communication establishment, 1st D2H FIS and
756 * device signature update is done, on safe side assume 500ms
757 * NOTE : Host online status may be indicated immediately!!
758 */
759
760 temp = ioread32(hcr_base + HCONTROL);
761 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
762 temp |= HCONTROL_PMP_ATTACHED;
763 iowrite32(temp, hcr_base + HCONTROL);
764
765 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
766
767 if (!(temp & ONLINE)) {
768 ata_port_printk(ap, KERN_ERR,
769 "Hardreset failed, not on-lined\n");
770 goto err;
771 }
772
773 DPRINTK("hardreset, controller off-lined & on-lined\n");
774 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
775 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
776
777 /*
778 * First, wait for the PHYRDY change to occur before waiting for
779 * the signature, and also verify if SStatus indicates device
780 * presence
781 */
782
783 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
784 if ((!(temp & 0x10)) || ata_link_offline(link)) {
785 ata_port_printk(ap, KERN_WARNING,
786 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
787 ioread32(hcr_base + HSTATUS));
788 *class = ATA_DEV_NONE;
789 return 0;
790 }
791
792 /*
793 * Wait for the first D2H from device,i.e,signature update notification
794 */
795 start_jiffies = jiffies;
796 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
797 500, jiffies_to_msecs(deadline - start_jiffies));
798
799 if ((temp & 0xFF) != 0x18) {
800 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
801 *class = ATA_DEV_NONE;
802 goto do_followup_srst;
803 } else {
804 ata_port_printk(ap, KERN_INFO,
805 "Signature Update detected @ %d msecs\n",
806 jiffies_to_msecs(jiffies - start_jiffies));
807 *class = sata_fsl_dev_classify(ap);
808 return 0;
809 }
810
811 do_followup_srst:
812 /*
813 * request libATA to perform follow-up softreset
814 */
815 return -EAGAIN;
816
817 err:
818 return -EIO;
819 }
820
821 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
822 unsigned long deadline)
823 {
824 struct ata_port *ap = link->ap;
825 struct sata_fsl_port_priv *pp = ap->private_data;
826 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
827 void __iomem *hcr_base = host_priv->hcr_base;
828 int pmp = sata_srst_pmp(link);
829 u32 temp;
830 struct ata_taskfile tf;
831 u8 *cfis;
832 u32 Serror;
833
834 DPRINTK("in xx_softreset\n");
835
836 if (ata_link_offline(link)) {
837 DPRINTK("PHY reports no device\n");
838 *class = ATA_DEV_NONE;
839 return 0;
840 }
841
842 /*
843 * Send a device reset (SRST) explicitly on command slot #0
844 * Check : will the command queue (reg) be cleared during offlining ??
845 * Also we will be online only if Phy commn. has been established
846 * and device presence has been detected, therefore if we have
847 * reached here, we can send a command to the target device
848 */
849
850 DPRINTK("Sending SRST/device reset\n");
851
852 ata_tf_init(link->device, &tf);
853 cfis = (u8 *) &pp->cmdentry->cfis;
854
855 /* device reset/SRST is a control register update FIS, uses tag0 */
856 sata_fsl_setup_cmd_hdr_entry(pp, 0,
857 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
858
859 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
860 ata_tf_to_fis(&tf, pmp, 0, cfis);
861
862 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
863 cfis[0], cfis[1], cfis[2], cfis[3]);
864
865 /*
866 * Queue SRST command to the controller/device, ensure that no
867 * other commands are active on the controller/device
868 */
869
870 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
871 ioread32(CQ + hcr_base),
872 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
873
874 iowrite32(0xFFFF, CC + hcr_base);
875 if (pmp != SATA_PMP_CTRL_PORT)
876 iowrite32(pmp, CQPMP + hcr_base);
877 iowrite32(1, CQ + hcr_base);
878
879 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
880 if (temp & 0x1) {
881 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
882
883 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
884 ioread32(CQ + hcr_base),
885 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
886
887 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
888
889 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
890 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
891 DPRINTK("Serror = 0x%x\n", Serror);
892 goto err;
893 }
894
895 msleep(1);
896
897 /*
898 * SATA device enters reset state after receving a Control register
899 * FIS with SRST bit asserted and it awaits another H2D Control reg.
900 * FIS with SRST bit cleared, then the device does internal diags &
901 * initialization, followed by indicating it's initialization status
902 * using ATA signature D2H register FIS to the host controller.
903 */
904
905 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
906 0, 0, 5);
907
908 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
909 ata_tf_to_fis(&tf, pmp, 0, cfis);
910
911 if (pmp != SATA_PMP_CTRL_PORT)
912 iowrite32(pmp, CQPMP + hcr_base);
913 iowrite32(1, CQ + hcr_base);
914 msleep(150); /* ?? */
915
916 /*
917 * The above command would have signalled an interrupt on command
918 * complete, which needs special handling, by clearing the Nth
919 * command bit of the CCreg
920 */
921 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
922
923 DPRINTK("SATA FSL : Now checking device signature\n");
924
925 *class = ATA_DEV_NONE;
926
927 /* Verify if SStatus indicates device presence */
928 if (ata_link_online(link)) {
929 /*
930 * if we are here, device presence has been detected,
931 * 1st D2H FIS would have been received, but sfis in
932 * command desc. is not updated, but signature register
933 * would have been updated
934 */
935
936 *class = sata_fsl_dev_classify(ap);
937
938 DPRINTK("class = %d\n", *class);
939 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
940 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
941 }
942
943 return 0;
944
945 err:
946 return -EIO;
947 }
948
949 static void sata_fsl_error_handler(struct ata_port *ap)
950 {
951
952 DPRINTK("in xx_error_handler\n");
953 sata_pmp_error_handler(ap);
954
955 }
956
957 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
958 {
959 if (qc->flags & ATA_QCFLAG_FAILED)
960 qc->err_mask |= AC_ERR_OTHER;
961
962 if (qc->err_mask) {
963 /* make DMA engine forget about the failed command */
964
965 }
966 }
967
968 static void sata_fsl_error_intr(struct ata_port *ap)
969 {
970 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
971 void __iomem *hcr_base = host_priv->hcr_base;
972 u32 hstatus, dereg=0, cereg = 0, SError = 0;
973 unsigned int err_mask = 0, action = 0;
974 int freeze = 0, abort=0;
975 struct ata_link *link = NULL;
976 struct ata_queued_cmd *qc = NULL;
977 struct ata_eh_info *ehi;
978
979 hstatus = ioread32(hcr_base + HSTATUS);
980 cereg = ioread32(hcr_base + CE);
981
982 /* first, analyze and record host port events */
983 link = &ap->link;
984 ehi = &link->eh_info;
985 ata_ehi_clear_desc(ehi);
986
987 /*
988 * Handle & Clear SError
989 */
990
991 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
992 if (unlikely(SError & 0xFFFF0000))
993 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
994
995 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
996 hstatus, cereg, ioread32(hcr_base + DE), SError);
997
998 /* handle fatal errors */
999 if (hstatus & FATAL_ERROR_DECODE) {
1000 ehi->err_mask |= AC_ERR_ATA_BUS;
1001 ehi->action |= ATA_EH_SOFTRESET;
1002
1003 freeze = 1;
1004 }
1005
1006 /* Handle SDB FIS receive & notify update */
1007 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1008 sata_async_notification(ap);
1009
1010 /* Handle PHYRDY change notification */
1011 if (hstatus & INT_ON_PHYRDY_CHG) {
1012 DPRINTK("SATA FSL: PHYRDY change indication\n");
1013
1014 /* Setup a soft-reset EH action */
1015 ata_ehi_hotplugged(ehi);
1016 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1017 freeze = 1;
1018 }
1019
1020 /* handle single device errors */
1021 if (cereg) {
1022 /*
1023 * clear the command error, also clears queue to the device
1024 * in error, and we can (re)issue commands to this device.
1025 * When a device is in error all commands queued into the
1026 * host controller and at the device are considered aborted
1027 * and the queue for that device is stopped. Now, after
1028 * clearing the device error, we can issue commands to the
1029 * device to interrogate it to find the source of the error.
1030 */
1031 abort = 1;
1032
1033 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1034 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1035
1036 /* find out the offending link and qc */
1037 if (ap->nr_pmp_links) {
1038 dereg = ioread32(hcr_base + DE);
1039 iowrite32(dereg, hcr_base + DE);
1040 iowrite32(cereg, hcr_base + CE);
1041
1042 if (dereg < ap->nr_pmp_links) {
1043 link = &ap->pmp_link[dereg];
1044 ehi = &link->eh_info;
1045 qc = ata_qc_from_tag(ap, link->active_tag);
1046 /*
1047 * We should consider this as non fatal error,
1048 * and TF must be updated as done below.
1049 */
1050
1051 err_mask |= AC_ERR_DEV;
1052
1053 } else {
1054 err_mask |= AC_ERR_HSM;
1055 action |= ATA_EH_HARDRESET;
1056 freeze = 1;
1057 }
1058 } else {
1059 dereg = ioread32(hcr_base + DE);
1060 iowrite32(dereg, hcr_base + DE);
1061 iowrite32(cereg, hcr_base + CE);
1062
1063 qc = ata_qc_from_tag(ap, link->active_tag);
1064 /*
1065 * We should consider this as non fatal error,
1066 * and TF must be updated as done below.
1067 */
1068 err_mask |= AC_ERR_DEV;
1069 }
1070 }
1071
1072 /* record error info */
1073 if (qc)
1074 qc->err_mask |= err_mask;
1075 else
1076 ehi->err_mask |= err_mask;
1077
1078 ehi->action |= action;
1079
1080 /* freeze or abort */
1081 if (freeze)
1082 ata_port_freeze(ap);
1083 else if (abort) {
1084 if (qc)
1085 ata_link_abort(qc->dev->link);
1086 else
1087 ata_port_abort(ap);
1088 }
1089 }
1090
1091 static void sata_fsl_host_intr(struct ata_port *ap)
1092 {
1093 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1094 void __iomem *hcr_base = host_priv->hcr_base;
1095 u32 hstatus, done_mask = 0;
1096 struct ata_queued_cmd *qc;
1097 u32 SError;
1098
1099 hstatus = ioread32(hcr_base + HSTATUS);
1100
1101 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1102
1103 if (unlikely(SError & 0xFFFF0000)) {
1104 DPRINTK("serror @host_intr : 0x%x\n", SError);
1105 sata_fsl_error_intr(ap);
1106 }
1107
1108 if (unlikely(hstatus & INT_ON_ERROR)) {
1109 DPRINTK("error interrupt!!\n");
1110 sata_fsl_error_intr(ap);
1111 return;
1112 }
1113
1114 /* Read command completed register */
1115 done_mask = ioread32(hcr_base + CC);
1116
1117 VPRINTK("Status of all queues :\n");
1118 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1119 done_mask,
1120 ioread32(hcr_base + CA),
1121 ioread32(hcr_base + CE),
1122 ioread32(hcr_base + CQ),
1123 ap->qc_active);
1124
1125 if (done_mask & ap->qc_active) {
1126 int i;
1127 /* clear CC bit, this will also complete the interrupt */
1128 iowrite32(done_mask, hcr_base + CC);
1129
1130 DPRINTK("Status of all queues :\n");
1131 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1132 done_mask, ioread32(hcr_base + CA),
1133 ioread32(hcr_base + CE));
1134
1135 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1136 if (done_mask & (1 << i)) {
1137 qc = ata_qc_from_tag(ap, i);
1138 if (qc) {
1139 ata_qc_complete(qc);
1140 }
1141 DPRINTK
1142 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1143 i, ioread32(hcr_base + CC),
1144 ioread32(hcr_base + CA));
1145 }
1146 }
1147 return;
1148
1149 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1150 iowrite32(1, hcr_base + CC);
1151 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1152
1153 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1154 ioread32(hcr_base + CC));
1155
1156 if (qc) {
1157 ata_qc_complete(qc);
1158 }
1159 } else {
1160 /* Spurious Interrupt!! */
1161 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1162 ioread32(hcr_base + CC));
1163 iowrite32(done_mask, hcr_base + CC);
1164 return;
1165 }
1166 }
1167
1168 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1169 {
1170 struct ata_host *host = dev_instance;
1171 struct sata_fsl_host_priv *host_priv = host->private_data;
1172 void __iomem *hcr_base = host_priv->hcr_base;
1173 u32 interrupt_enables;
1174 unsigned handled = 0;
1175 struct ata_port *ap;
1176
1177 /* ack. any pending IRQs for this controller/port */
1178 interrupt_enables = ioread32(hcr_base + HSTATUS);
1179 interrupt_enables &= 0x3F;
1180
1181 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1182
1183 if (!interrupt_enables)
1184 return IRQ_NONE;
1185
1186 spin_lock(&host->lock);
1187
1188 /* Assuming one port per host controller */
1189
1190 ap = host->ports[0];
1191 if (ap) {
1192 sata_fsl_host_intr(ap);
1193 } else {
1194 dev_printk(KERN_WARNING, host->dev,
1195 "interrupt on disabled port 0\n");
1196 }
1197
1198 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1199 handled = 1;
1200
1201 spin_unlock(&host->lock);
1202
1203 return IRQ_RETVAL(handled);
1204 }
1205
1206 /*
1207 * Multiple ports are represented by multiple SATA controllers with
1208 * one port per controller
1209 */
1210 static int sata_fsl_init_controller(struct ata_host *host)
1211 {
1212 struct sata_fsl_host_priv *host_priv = host->private_data;
1213 void __iomem *hcr_base = host_priv->hcr_base;
1214 u32 temp;
1215
1216 /*
1217 * NOTE : We cannot bring the controller online before setting
1218 * the CHBA, hence main controller initialization is done as
1219 * part of the port_start() callback
1220 */
1221
1222 /* ack. any pending IRQs for this controller/port */
1223 temp = ioread32(hcr_base + HSTATUS);
1224 if (temp & 0x3F)
1225 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1226
1227 /* Keep interrupts disabled on the controller */
1228 temp = ioread32(hcr_base + HCONTROL);
1229 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1230
1231 /* Disable interrupt coalescing control(icc), for the moment */
1232 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1233 iowrite32(0x01000000, hcr_base + ICC);
1234
1235 /* clear error registers, SError is cleared by libATA */
1236 iowrite32(0x00000FFFF, hcr_base + CE);
1237 iowrite32(0x00000FFFF, hcr_base + DE);
1238
1239 /*
1240 * host controller will be brought on-line, during xx_port_start()
1241 * callback, that should also initiate the OOB, COMINIT sequence
1242 */
1243
1244 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1245 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1246
1247 return 0;
1248 }
1249
1250 /*
1251 * scsi mid-layer and libata interface structures
1252 */
1253 static struct scsi_host_template sata_fsl_sht = {
1254 ATA_NCQ_SHT("sata_fsl"),
1255 .can_queue = SATA_FSL_QUEUE_DEPTH,
1256 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1257 .dma_boundary = ATA_DMA_BOUNDARY,
1258 };
1259
1260 static struct ata_port_operations sata_fsl_ops = {
1261 .inherits = &sata_pmp_port_ops,
1262
1263 .qc_defer = ata_std_qc_defer,
1264 .qc_prep = sata_fsl_qc_prep,
1265 .qc_issue = sata_fsl_qc_issue,
1266 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1267
1268 .scr_read = sata_fsl_scr_read,
1269 .scr_write = sata_fsl_scr_write,
1270
1271 .freeze = sata_fsl_freeze,
1272 .thaw = sata_fsl_thaw,
1273 .softreset = sata_fsl_softreset,
1274 .hardreset = sata_fsl_hardreset,
1275 .pmp_softreset = sata_fsl_softreset,
1276 .error_handler = sata_fsl_error_handler,
1277 .post_internal_cmd = sata_fsl_post_internal_cmd,
1278
1279 .port_start = sata_fsl_port_start,
1280 .port_stop = sata_fsl_port_stop,
1281
1282 .pmp_attach = sata_fsl_pmp_attach,
1283 .pmp_detach = sata_fsl_pmp_detach,
1284 };
1285
1286 static const struct ata_port_info sata_fsl_port_info[] = {
1287 {
1288 .flags = SATA_FSL_HOST_FLAGS,
1289 .pio_mask = ATA_PIO4,
1290 .udma_mask = ATA_UDMA6,
1291 .port_ops = &sata_fsl_ops,
1292 },
1293 };
1294
1295 static int sata_fsl_probe(struct platform_device *ofdev,
1296 const struct of_device_id *match)
1297 {
1298 int retval = -ENXIO;
1299 void __iomem *hcr_base = NULL;
1300 void __iomem *ssr_base = NULL;
1301 void __iomem *csr_base = NULL;
1302 struct sata_fsl_host_priv *host_priv = NULL;
1303 int irq;
1304 struct ata_host *host;
1305
1306 struct ata_port_info pi = sata_fsl_port_info[0];
1307 const struct ata_port_info *ppi[] = { &pi, NULL };
1308
1309 dev_printk(KERN_INFO, &ofdev->dev,
1310 "Sata FSL Platform/CSB Driver init\n");
1311
1312 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1313 if (!hcr_base)
1314 goto error_exit_with_cleanup;
1315
1316 ssr_base = hcr_base + 0x100;
1317 csr_base = hcr_base + 0x140;
1318
1319 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1320 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1321 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1322
1323 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1324 if (!host_priv)
1325 goto error_exit_with_cleanup;
1326
1327 host_priv->hcr_base = hcr_base;
1328 host_priv->ssr_base = ssr_base;
1329 host_priv->csr_base = csr_base;
1330
1331 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1332 if (irq < 0) {
1333 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1334 goto error_exit_with_cleanup;
1335 }
1336 host_priv->irq = irq;
1337
1338 /* allocate host structure */
1339 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1340
1341 /* host->iomap is not used currently */
1342 host->private_data = host_priv;
1343
1344 /* initialize host controller */
1345 sata_fsl_init_controller(host);
1346
1347 /*
1348 * Now, register with libATA core, this will also initiate the
1349 * device discovery process, invoking our port_start() handler &
1350 * error_handler() to execute a dummy Softreset EH session
1351 */
1352 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1353 &sata_fsl_sht);
1354
1355 dev_set_drvdata(&ofdev->dev, host);
1356
1357 return 0;
1358
1359 error_exit_with_cleanup:
1360
1361 if (hcr_base)
1362 iounmap(hcr_base);
1363 if (host_priv)
1364 kfree(host_priv);
1365
1366 return retval;
1367 }
1368
1369 static int sata_fsl_remove(struct platform_device *ofdev)
1370 {
1371 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1372 struct sata_fsl_host_priv *host_priv = host->private_data;
1373
1374 ata_host_detach(host);
1375
1376 dev_set_drvdata(&ofdev->dev, NULL);
1377
1378 irq_dispose_mapping(host_priv->irq);
1379 iounmap(host_priv->hcr_base);
1380 kfree(host_priv);
1381
1382 return 0;
1383 }
1384
1385 #ifdef CONFIG_PM
1386 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1387 {
1388 struct ata_host *host = dev_get_drvdata(&op->dev);
1389 return ata_host_suspend(host, state);
1390 }
1391
1392 static int sata_fsl_resume(struct platform_device *op)
1393 {
1394 struct ata_host *host = dev_get_drvdata(&op->dev);
1395 struct sata_fsl_host_priv *host_priv = host->private_data;
1396 int ret;
1397 void __iomem *hcr_base = host_priv->hcr_base;
1398 struct ata_port *ap = host->ports[0];
1399 struct sata_fsl_port_priv *pp = ap->private_data;
1400
1401 ret = sata_fsl_init_controller(host);
1402 if (ret) {
1403 dev_printk(KERN_ERR, &op->dev,
1404 "Error initialize hardware\n");
1405 return ret;
1406 }
1407
1408 /* Recovery the CHBA register in host controller cmd register set */
1409 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1410
1411 ata_host_resume(host);
1412 return 0;
1413 }
1414 #endif
1415
1416 static struct of_device_id fsl_sata_match[] = {
1417 {
1418 .compatible = "fsl,pq-sata",
1419 },
1420 {},
1421 };
1422
1423 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1424
1425 static struct of_platform_driver fsl_sata_driver = {
1426 .driver = {
1427 .name = "fsl-sata",
1428 .owner = THIS_MODULE,
1429 .of_match_table = fsl_sata_match,
1430 },
1431 .probe = sata_fsl_probe,
1432 .remove = sata_fsl_remove,
1433 #ifdef CONFIG_PM
1434 .suspend = sata_fsl_suspend,
1435 .resume = sata_fsl_resume,
1436 #endif
1437 };
1438
1439 static int __init sata_fsl_init(void)
1440 {
1441 of_register_platform_driver(&fsl_sata_driver);
1442 return 0;
1443 }
1444
1445 static void __exit sata_fsl_exit(void)
1446 {
1447 of_unregister_platform_driver(&fsl_sata_driver);
1448 }
1449
1450 MODULE_LICENSE("GPL");
1451 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1452 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1453 MODULE_VERSION("1.10");
1454
1455 module_init(sata_fsl_init);
1456 module_exit(sata_fsl_exit);
Tomato firmware and modifications.