release/src-rt-6.x.4708/linux/linux-2.6.36/arch/x86/pci/i386.c

   1 /*
   2  *      Low-Level PCI Access for i386 machines
   3  *
   4  * Copyright 1993, 1994 Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      Drew@Colorado.EDU
   8  *      +1 (303) 786-7975
   9  *
  10  * Drew's work was sponsored by:
  11  *      iX Multiuser Multitasking Magazine
  12  *      Hannover, Germany
  13  *      hm@ix.de
  14  *
  15  * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
  16  *
  17  * For more information, please consult the following manuals (look at
  18  * http://www.pcisig.com/ for how to get them):
  19  *
  20  * PCI BIOS Specification
  21  * PCI Local Bus Specification
  22  * PCI to PCI Bridge Specification
  23  * PCI System Design Guide
  24  *
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/errno.h>
  33 #include <linux/bootmem.h>
  34
  35 #include <asm/pat.h>
  36 #include <asm/e820.h>
  37 #include <asm/pci_x86.h>
  38 #include <asm/io_apic.h>
  39
  40
  41 static int
  42 skip_isa_ioresource_align(struct pci_dev *dev) {
  43
  44         if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
  45             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
  46                 return 1;
  47         return 0;
  48 }
  49
  50 /*
  51  * We need to avoid collisions with `mirrored' VGA ports
  52  * and other strange ISA hardware, so we always want the
  53  * addresses to be allocated in the 0x000-0x0ff region
  54  * modulo 0x400.
  55  *
  56  * Why? Because some silly external IO cards only decode
  57  * the low 10 bits of the IO address. The 0x00-0xff region
  58  * is reserved for motherboard devices that decode all 16
  59  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  60  * but we want to try to avoid allocating at 0x2900-0x2bff
  61  * which might have be mirrored at 0x0100-0x03ff..
  62  */
  63 resource_size_t
  64 pcibios_align_resource(void *data, const struct resource *res,
  65                         resource_size_t size, resource_size_t align)
  66 {
  67         struct pci_dev *dev = data;
  68         resource_size_t start = res->start;
  69
  70         if (res->flags & IORESOURCE_IO) {
  71                 if (skip_isa_ioresource_align(dev))
  72                         return start;
  73                 if (start & 0x300)
  74                         start = (start + 0x3ff) & ~0x3ff;
  75         } else if (res->flags & IORESOURCE_MEM) {
  76                 if (start < BIOS_END)
  77                         start = BIOS_END;
  78         }
  79         return start;
  80 }
  81 EXPORT_SYMBOL(pcibios_align_resource);
  82
  83
  84 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
  85 {
  86         struct pci_bus *bus;
  87         struct pci_dev *dev;
  88         int idx;
  89         struct resource *r;
  90
  91         /* Depth-First Search on bus tree */
  92         list_for_each_entry(bus, bus_list, node) {
  93                 if ((dev = bus->self)) {
  94                         for (idx = PCI_BRIDGE_RESOURCES;
  95                             idx < PCI_NUM_RESOURCES; idx++) {
  96                                 r = &dev->resource[idx];
  97                                 if (!r->flags)
  98                                         continue;
  99                                 if (!r->start ||
 100                                     pci_claim_resource(dev, idx) < 0) {
 101                                         /*
 102                                          * Something is wrong with the region.
 103                                          * Invalidate the resource to prevent
 104                                          * child resource allocations in this
 105                                          * range.
 106                                          */
 107                                         r->start = r->end = 0;
 108                                         r->flags = 0;
 109                                 }
 110                         }
 111                 }
 112                 pcibios_allocate_bus_resources(&bus->children);
 113         }
 114 }
 115
 116 struct pci_check_idx_range {
 117         int start;
 118         int end;
 119 };
 120
 121 static void __init pcibios_allocate_resources(int pass)
 122 {
 123         struct pci_dev *dev = NULL;
 124         int idx, disabled, i;
 125         u16 command;
 126         struct resource *r;
 127
 128         struct pci_check_idx_range idx_range[] = {
 129                 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
 130 #ifdef CONFIG_PCI_IOV
 131                 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
 132 #endif
 133         };
 134
 135         for_each_pci_dev(dev) {
 136                 pci_read_config_word(dev, PCI_COMMAND, &command);
 137                 for (i = 0; i < ARRAY_SIZE(idx_range); i++)
 138                 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
 139                         r = &dev->resource[idx];
 140                         if (r->parent)          /* Already allocated */
 141                                 continue;
 142                         if (!r->start)          /* Address not assigned at all */
 143                                 continue;
 144                         if (r->flags & IORESOURCE_IO)
 145                                 disabled = !(command & PCI_COMMAND_IO);
 146                         else
 147                                 disabled = !(command & PCI_COMMAND_MEMORY);
 148                         if (pass == disabled) {
 149                                 dev_dbg(&dev->dev,
 150                                         "BAR %d: reserving %pr (d=%d, p=%d)\n",
 151                                         idx, r, disabled, pass);
 152                                 if (pci_claim_resource(dev, idx) < 0) {
 153                                         /* We'll assign a new address later */
 154                                         dev->fw_addr[idx] = r->start;
 155                                         r->end -= r->start;
 156                                         r->start = 0;
 157                                 }
 158                         }
 159                 }
 160                 if (!pass) {
 161                         r = &dev->resource[PCI_ROM_RESOURCE];
 162                         if (r->flags & IORESOURCE_ROM_ENABLE) {
 163                                 /* Turn the ROM off, leave the resource region,
 164                                  * but keep it unregistered. */
 165                                 u32 reg;
 166                                 dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
 167                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 168                                 pci_read_config_dword(dev,
 169                                                 dev->rom_base_reg, &reg);
 170                                 pci_write_config_dword(dev, dev->rom_base_reg,
 171                                                 reg & ~PCI_ROM_ADDRESS_ENABLE);
 172                         }
 173                 }
 174         }
 175 }
 176
 177 static int __init pcibios_assign_resources(void)
 178 {
 179         struct pci_dev *dev = NULL;
 180         struct resource *r;
 181
 182         if (!(pci_probe & PCI_ASSIGN_ROMS)) {
 183                 /*
 184                  * Try to use BIOS settings for ROMs, otherwise let
 185                  * pci_assign_unassigned_resources() allocate the new
 186                  * addresses.
 187                  */
 188                 for_each_pci_dev(dev) {
 189                         r = &dev->resource[PCI_ROM_RESOURCE];
 190                         if (!r->flags || !r->start)
 191                                 continue;
 192                         if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
 193                                 r->end -= r->start;
 194                                 r->start = 0;
 195                         }
 196                 }
 197         }
 198
 199         pci_assign_unassigned_resources();
 200
 201         return 0;
 202 }
 203
 204 void __init pcibios_resource_survey(void)
 205 {
 206         DBG("PCI: Allocating resources\n");
 207         pcibios_allocate_bus_resources(&pci_root_buses);
 208         pcibios_allocate_resources(0);
 209         pcibios_allocate_resources(1);
 210
 211         e820_reserve_resources_late();
 212         /*
 213          * Insert the IO APIC resources after PCI initialization has
 214          * occured to handle IO APICS that are mapped in on a BAR in
 215          * PCI space, but before trying to assign unassigned pci res.
 216          */
 217         ioapic_insert_resources();
 218 }
 219
 220 /**
 221  * called in fs_initcall (one below subsys_initcall),
 222  * give a chance for motherboard reserve resources
 223  */
 224 fs_initcall(pcibios_assign_resources);
 225
 226 /*
 227  *  If we set up a device for bus mastering, we need to check the latency
 228  *  timer as certain crappy BIOSes forget to set it properly.
 229  */
 230 unsigned int pcibios_max_latency = 255;
 231
 232 void pcibios_set_master(struct pci_dev *dev)
 233 {
 234         u8 lat;
 235         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 236         if (lat < 16)
 237                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 238         else if (lat > pcibios_max_latency)
 239                 lat = pcibios_max_latency;
 240         else
 241                 return;
 242         dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
 243         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 244 }
 245
 246 static const struct vm_operations_struct pci_mmap_ops = {
 247         .access = generic_access_phys,
 248 };
 249
 250 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 251                         enum pci_mmap_state mmap_state, int write_combine)
 252 {
 253         unsigned long prot;
 254
 255         /* I/O space cannot be accessed via normal processor loads and
 256          * stores on this platform.
 257          */
 258         if (mmap_state == pci_mmap_io)
 259                 return -EINVAL;
 260
 261         prot = pgprot_val(vma->vm_page_prot);
 262
 263         /*
 264          * Return error if pat is not enabled and write_combine is requested.
 265          * Caller can followup with UC MINUS request and add a WC mtrr if there
 266          * is a free mtrr slot.
 267          */
 268         if (!pat_enabled && write_combine)
 269                 return -EINVAL;
 270
 271         if (pat_enabled && write_combine)
 272                 prot |= _PAGE_CACHE_WC;
 273         else if (pat_enabled || boot_cpu_data.x86 > 3)
 274                 /*
 275                  * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
 276                  * To avoid attribute conflicts, request UC MINUS here
 277                  * aswell.
 278                  */
 279                 prot |= _PAGE_CACHE_UC_MINUS;
 280
 281         vma->vm_page_prot = __pgprot(prot);
 282
 283         if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 284                                vma->vm_end - vma->vm_start,
 285                                vma->vm_page_prot))
 286                 return -EAGAIN;
 287
 288         vma->vm_ops = &pci_mmap_ops;
 289
 290         return 0;
 291 }