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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / x86 / kvm / svm.c
blob9bab4155d6e822b9108aebbbdb05b3e905758da1
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34
35 #include <asm/virtext.h>
36 #include "trace.h"
37
38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
39
40 MODULE_AUTHOR("Qumranet");
41 MODULE_LICENSE("GPL");
42
43 #define IOPM_ALLOC_ORDER 2
44 #define MSRPM_ALLOC_ORDER 1
45
46 #define SEG_TYPE_LDT 2
47 #define SEG_TYPE_BUSY_TSS16 3
48
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_FEATURE_SVML (1 << 2)
52 #define SVM_FEATURE_NRIP (1 << 3)
53 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
54
55 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
61 static bool erratum_383_found __read_mostly;
62
63 static const u32 host_save_user_msrs[] = {
64 #ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67 #endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69 };
70
71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73 struct kvm_vcpu;
74
75 struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
78 u64 vm_cr_msr;
79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
86 u64 vmcb_iopm;
87
88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
91 /*
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
94 */
95 unsigned long vmexit_rip;
96 unsigned long vmexit_rsp;
97 unsigned long vmexit_rax;
98
99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read;
101 u16 intercept_cr_write;
102 u16 intercept_dr_read;
103 u16 intercept_dr_write;
104 u32 intercept_exceptions;
105 u64 intercept;
106
107 };
108
109 #define MSRPM_OFFSETS 16
110 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
111
112 struct vcpu_svm {
113 struct kvm_vcpu vcpu;
114 struct vmcb *vmcb;
115 unsigned long vmcb_pa;
116 struct svm_cpu_data *svm_data;
117 uint64_t asid_generation;
118 uint64_t sysenter_esp;
119 uint64_t sysenter_eip;
120
121 u64 next_rip;
122
123 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
124 u64 host_gs_base;
125
126 u32 *msrpm;
127
128 struct nested_state nested;
129
130 bool nmi_singlestep;
131
132 unsigned int3_injected;
133 unsigned long int3_rip;
134 };
135
136 #define MSR_INVALID 0xffffffffU
137
138 static struct svm_direct_access_msrs {
139 u32 index; /* Index of the MSR */
140 bool always; /* True if intercept is always on */
141 } direct_access_msrs[] = {
142 { .index = MSR_STAR, .always = true },
143 { .index = MSR_IA32_SYSENTER_CS, .always = true },
144 #ifdef CONFIG_X86_64
145 { .index = MSR_GS_BASE, .always = true },
146 { .index = MSR_FS_BASE, .always = true },
147 { .index = MSR_KERNEL_GS_BASE, .always = true },
148 { .index = MSR_LSTAR, .always = true },
149 { .index = MSR_CSTAR, .always = true },
150 { .index = MSR_SYSCALL_MASK, .always = true },
151 #endif
152 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
153 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
154 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
155 { .index = MSR_IA32_LASTINTTOIP, .always = false },
156 { .index = MSR_INVALID, .always = false },
157 };
158
159 /* enable NPT for AMD64 and X86 with PAE */
160 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
161 static bool npt_enabled = true;
162 #else
163 static bool npt_enabled;
164 #endif
165 static int npt = 1;
166
167 module_param(npt, int, S_IRUGO);
168
169 static int nested = 1;
170 module_param(nested, int, S_IRUGO);
171
172 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
173 static void svm_complete_interrupts(struct vcpu_svm *svm);
174
175 static int nested_svm_exit_handled(struct vcpu_svm *svm);
176 static int nested_svm_intercept(struct vcpu_svm *svm);
177 static int nested_svm_vmexit(struct vcpu_svm *svm);
178 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
179 bool has_error_code, u32 error_code);
180
181 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
182 {
183 return container_of(vcpu, struct vcpu_svm, vcpu);
184 }
185
186 static inline bool is_nested(struct vcpu_svm *svm)
187 {
188 return svm->nested.vmcb;
189 }
190
191 static inline void enable_gif(struct vcpu_svm *svm)
192 {
193 svm->vcpu.arch.hflags |= HF_GIF_MASK;
194 }
195
196 static inline void disable_gif(struct vcpu_svm *svm)
197 {
198 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
199 }
200
201 static inline bool gif_set(struct vcpu_svm *svm)
202 {
203 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
204 }
205
206 static unsigned long iopm_base;
207
208 struct kvm_ldttss_desc {
209 u16 limit0;
210 u16 base0;
211 unsigned base1:8, type:5, dpl:2, p:1;
212 unsigned limit1:4, zero0:3, g:1, base2:8;
213 u32 base3;
214 u32 zero1;
215 } __attribute__((packed));
216
217 struct svm_cpu_data {
218 int cpu;
219
220 u64 asid_generation;
221 u32 max_asid;
222 u32 next_asid;
223 struct kvm_ldttss_desc *tss_desc;
224
225 struct page *save_area;
226 };
227
228 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
229 static uint32_t svm_features;
230
231 struct svm_init_data {
232 int cpu;
233 int r;
234 };
235
236 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
237
238 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
239 #define MSRS_RANGE_SIZE 2048
240 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
241
242 static u32 svm_msrpm_offset(u32 msr)
243 {
244 u32 offset;
245 int i;
246
247 for (i = 0; i < NUM_MSR_MAPS; i++) {
248 if (msr < msrpm_ranges[i] ||
249 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
250 continue;
251
252 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
253 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
254
255 /* Now we have the u8 offset - but need the u32 offset */
256 return offset / 4;
257 }
258
259 /* MSR not in any range */
260 return MSR_INVALID;
261 }
262
263 #define MAX_INST_SIZE 15
264
265 static inline u32 svm_has(u32 feat)
266 {
267 return svm_features & feat;
268 }
269
270 static inline void clgi(void)
271 {
272 asm volatile (__ex(SVM_CLGI));
273 }
274
275 static inline void stgi(void)
276 {
277 asm volatile (__ex(SVM_STGI));
278 }
279
280 static inline void invlpga(unsigned long addr, u32 asid)
281 {
282 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
283 }
284
285 static inline void force_new_asid(struct kvm_vcpu *vcpu)
286 {
287 to_svm(vcpu)->asid_generation--;
288 }
289
290 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
291 {
292 force_new_asid(vcpu);
293 }
294
295 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
296 {
297 vcpu->arch.efer = efer;
298 if (!npt_enabled && !(efer & EFER_LMA))
299 efer &= ~EFER_LME;
300
301 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
302 }
303
304 static int is_external_interrupt(u32 info)
305 {
306 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
307 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
308 }
309
310 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
311 {
312 struct vcpu_svm *svm = to_svm(vcpu);
313 u32 ret = 0;
314
315 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
316 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
317 return ret & mask;
318 }
319
320 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
321 {
322 struct vcpu_svm *svm = to_svm(vcpu);
323
324 if (mask == 0)
325 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
326 else
327 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
328
329 }
330
331 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
332 {
333 struct vcpu_svm *svm = to_svm(vcpu);
334
335 if (svm->vmcb->control.next_rip != 0)
336 svm->next_rip = svm->vmcb->control.next_rip;
337
338 if (!svm->next_rip) {
339 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
340 EMULATE_DONE)
341 printk(KERN_DEBUG "%s: NOP\n", __func__);
342 return;
343 }
344 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
345 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
346 __func__, kvm_rip_read(vcpu), svm->next_rip);
347
348 kvm_rip_write(vcpu, svm->next_rip);
349 svm_set_interrupt_shadow(vcpu, 0);
350 }
351
352 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
353 bool has_error_code, u32 error_code,
354 bool reinject)
355 {
356 struct vcpu_svm *svm = to_svm(vcpu);
357
358 /*
359 * If we are within a nested VM we'd better #VMEXIT and let the guest
360 * handle the exception
361 */
362 if (!reinject &&
363 nested_svm_check_exception(svm, nr, has_error_code, error_code))
364 return;
365
366 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
367 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
368
369 /*
370 * For guest debugging where we have to reinject #BP if some
371 * INT3 is guest-owned:
372 * Emulate nRIP by moving RIP forward. Will fail if injection
373 * raises a fault that is not intercepted. Still better than
374 * failing in all cases.
375 */
376 skip_emulated_instruction(&svm->vcpu);
377 rip = kvm_rip_read(&svm->vcpu);
378 svm->int3_rip = rip + svm->vmcb->save.cs.base;
379 svm->int3_injected = rip - old_rip;
380 }
381
382 svm->vmcb->control.event_inj = nr
383 | SVM_EVTINJ_VALID
384 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
385 | SVM_EVTINJ_TYPE_EXEPT;
386 svm->vmcb->control.event_inj_err = error_code;
387 }
388
389 static void svm_init_erratum_383(void)
390 {
391 u32 low, high;
392 int err;
393 u64 val;
394
395 if (!cpu_has_amd_erratum(amd_erratum_383))
396 return;
397
398 /* Use _safe variants to not break nested virtualization */
399 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
400 if (err)
401 return;
402
403 val |= (1ULL << 47);
404
405 low = lower_32_bits(val);
406 high = upper_32_bits(val);
407
408 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
409
410 erratum_383_found = true;
411 }
412
413 static int has_svm(void)
414 {
415 const char *msg;
416
417 if (!cpu_has_svm(&msg)) {
418 printk(KERN_INFO "has_svm: %s\n", msg);
419 return 0;
420 }
421
422 return 1;
423 }
424
425 static void svm_hardware_disable(void *garbage)
426 {
427 cpu_svm_disable();
428 }
429
430 static int svm_hardware_enable(void *garbage)
431 {
432
433 struct svm_cpu_data *sd;
434 uint64_t efer;
435 struct desc_ptr gdt_descr;
436 struct desc_struct *gdt;
437 int me = raw_smp_processor_id();
438
439 rdmsrl(MSR_EFER, efer);
440 if (efer & EFER_SVME)
441 return -EBUSY;
442
443 if (!has_svm()) {
444 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
445 me);
446 return -EINVAL;
447 }
448 sd = per_cpu(svm_data, me);
449
450 if (!sd) {
451 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
452 me);
453 return -EINVAL;
454 }
455
456 sd->asid_generation = 1;
457 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
458 sd->next_asid = sd->max_asid + 1;
459
460 native_store_gdt(&gdt_descr);
461 gdt = (struct desc_struct *)gdt_descr.address;
462 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
463
464 wrmsrl(MSR_EFER, efer | EFER_SVME);
465
466 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
467
468 svm_init_erratum_383();
469
470 return 0;
471 }
472
473 static void svm_cpu_uninit(int cpu)
474 {
475 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
476
477 if (!sd)
478 return;
479
480 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
481 __free_page(sd->save_area);
482 kfree(sd);
483 }
484
485 static int svm_cpu_init(int cpu)
486 {
487 struct svm_cpu_data *sd;
488 int r;
489
490 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
491 if (!sd)
492 return -ENOMEM;
493 sd->cpu = cpu;
494 sd->save_area = alloc_page(GFP_KERNEL);
495 r = -ENOMEM;
496 if (!sd->save_area)
497 goto err_1;
498
499 per_cpu(svm_data, cpu) = sd;
500
501 return 0;
502
503 err_1:
504 kfree(sd);
505 return r;
506
507 }
508
509 static bool valid_msr_intercept(u32 index)
510 {
511 int i;
512
513 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
514 if (direct_access_msrs[i].index == index)
515 return true;
516
517 return false;
518 }
519
520 static void set_msr_interception(u32 *msrpm, unsigned msr,
521 int read, int write)
522 {
523 u8 bit_read, bit_write;
524 unsigned long tmp;
525 u32 offset;
526
527 /*
528 * If this warning triggers extend the direct_access_msrs list at the
529 * beginning of the file
530 */
531 WARN_ON(!valid_msr_intercept(msr));
532
533 offset = svm_msrpm_offset(msr);
534 bit_read = 2 * (msr & 0x0f);
535 bit_write = 2 * (msr & 0x0f) + 1;
536 tmp = msrpm[offset];
537
538 BUG_ON(offset == MSR_INVALID);
539
540 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
541 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
542
543 msrpm[offset] = tmp;
544 }
545
546 static void svm_vcpu_init_msrpm(u32 *msrpm)
547 {
548 int i;
549
550 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
551
552 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
553 if (!direct_access_msrs[i].always)
554 continue;
555
556 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
557 }
558 }
559
560 static void add_msr_offset(u32 offset)
561 {
562 int i;
563
564 for (i = 0; i < MSRPM_OFFSETS; ++i) {
565
566 /* Offset already in list? */
567 if (msrpm_offsets[i] == offset)
568 return;
569
570 /* Slot used by another offset? */
571 if (msrpm_offsets[i] != MSR_INVALID)
572 continue;
573
574 /* Add offset to list */
575 msrpm_offsets[i] = offset;
576
577 return;
578 }
579
580 /*
581 * If this BUG triggers the msrpm_offsets table has an overflow. Just
582 * increase MSRPM_OFFSETS in this case.
583 */
584 BUG();
585 }
586
587 static void init_msrpm_offsets(void)
588 {
589 int i;
590
591 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
592
593 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
594 u32 offset;
595
596 offset = svm_msrpm_offset(direct_access_msrs[i].index);
597 BUG_ON(offset == MSR_INVALID);
598
599 add_msr_offset(offset);
600 }
601 }
602
603 static void svm_enable_lbrv(struct vcpu_svm *svm)
604 {
605 u32 *msrpm = svm->msrpm;
606
607 svm->vmcb->control.lbr_ctl = 1;
608 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
609 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
610 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
611 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
612 }
613
614 static void svm_disable_lbrv(struct vcpu_svm *svm)
615 {
616 u32 *msrpm = svm->msrpm;
617
618 svm->vmcb->control.lbr_ctl = 0;
619 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
620 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
621 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
622 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
623 }
624
625 static __init int svm_hardware_setup(void)
626 {
627 int cpu;
628 struct page *iopm_pages;
629 void *iopm_va;
630 int r;
631
632 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
633
634 if (!iopm_pages)
635 return -ENOMEM;
636
637 iopm_va = page_address(iopm_pages);
638 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
639 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
640
641 init_msrpm_offsets();
642
643 if (boot_cpu_has(X86_FEATURE_NX))
644 kvm_enable_efer_bits(EFER_NX);
645
646 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
647 kvm_enable_efer_bits(EFER_FFXSR);
648
649 if (nested) {
650 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
651 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
652 }
653
654 for_each_possible_cpu(cpu) {
655 r = svm_cpu_init(cpu);
656 if (r)
657 goto err;
658 }
659
660 svm_features = cpuid_edx(SVM_CPUID_FUNC);
661
662 if (!svm_has(SVM_FEATURE_NPT))
663 npt_enabled = false;
664
665 if (npt_enabled && !npt) {
666 printk(KERN_INFO "kvm: Nested Paging disabled\n");
667 npt_enabled = false;
668 }
669
670 if (npt_enabled) {
671 printk(KERN_INFO "kvm: Nested Paging enabled\n");
672 kvm_enable_tdp();
673 } else
674 kvm_disable_tdp();
675
676 return 0;
677
678 err:
679 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
680 iopm_base = 0;
681 return r;
682 }
683
684 static __exit void svm_hardware_unsetup(void)
685 {
686 int cpu;
687
688 for_each_possible_cpu(cpu)
689 svm_cpu_uninit(cpu);
690
691 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
692 iopm_base = 0;
693 }
694
695 static void init_seg(struct vmcb_seg *seg)
696 {
697 seg->selector = 0;
698 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
699 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
700 seg->limit = 0xffff;
701 seg->base = 0;
702 }
703
704 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
705 {
706 seg->selector = 0;
707 seg->attrib = SVM_SELECTOR_P_MASK | type;
708 seg->limit = 0xffff;
709 seg->base = 0;
710 }
711
712 static void init_vmcb(struct vcpu_svm *svm)
713 {
714 struct vmcb_control_area *control = &svm->vmcb->control;
715 struct vmcb_save_area *save = &svm->vmcb->save;
716
717 svm->vcpu.fpu_active = 1;
718
719 control->intercept_cr_read = INTERCEPT_CR0_MASK |
720 INTERCEPT_CR3_MASK |
721 INTERCEPT_CR4_MASK;
722
723 control->intercept_cr_write = INTERCEPT_CR0_MASK |
724 INTERCEPT_CR3_MASK |
725 INTERCEPT_CR4_MASK |
726 INTERCEPT_CR8_MASK;
727
728 control->intercept_dr_read = INTERCEPT_DR0_MASK |
729 INTERCEPT_DR1_MASK |
730 INTERCEPT_DR2_MASK |
731 INTERCEPT_DR3_MASK |
732 INTERCEPT_DR4_MASK |
733 INTERCEPT_DR5_MASK |
734 INTERCEPT_DR6_MASK |
735 INTERCEPT_DR7_MASK;
736
737 control->intercept_dr_write = INTERCEPT_DR0_MASK |
738 INTERCEPT_DR1_MASK |
739 INTERCEPT_DR2_MASK |
740 INTERCEPT_DR3_MASK |
741 INTERCEPT_DR4_MASK |
742 INTERCEPT_DR5_MASK |
743 INTERCEPT_DR6_MASK |
744 INTERCEPT_DR7_MASK;
745
746 control->intercept_exceptions = (1 << PF_VECTOR) |
747 (1 << UD_VECTOR) |
748 (1 << MC_VECTOR);
749
750
751 control->intercept = (1ULL << INTERCEPT_INTR) |
752 (1ULL << INTERCEPT_NMI) |
753 (1ULL << INTERCEPT_SMI) |
754 (1ULL << INTERCEPT_SELECTIVE_CR0) |
755 (1ULL << INTERCEPT_CPUID) |
756 (1ULL << INTERCEPT_INVD) |
757 (1ULL << INTERCEPT_HLT) |
758 (1ULL << INTERCEPT_INVLPG) |
759 (1ULL << INTERCEPT_INVLPGA) |
760 (1ULL << INTERCEPT_IOIO_PROT) |
761 (1ULL << INTERCEPT_MSR_PROT) |
762 (1ULL << INTERCEPT_TASK_SWITCH) |
763 (1ULL << INTERCEPT_SHUTDOWN) |
764 (1ULL << INTERCEPT_VMRUN) |
765 (1ULL << INTERCEPT_VMMCALL) |
766 (1ULL << INTERCEPT_VMLOAD) |
767 (1ULL << INTERCEPT_VMSAVE) |
768 (1ULL << INTERCEPT_STGI) |
769 (1ULL << INTERCEPT_CLGI) |
770 (1ULL << INTERCEPT_SKINIT) |
771 (1ULL << INTERCEPT_WBINVD) |
772 (1ULL << INTERCEPT_MONITOR) |
773 (1ULL << INTERCEPT_MWAIT);
774
775 control->iopm_base_pa = iopm_base;
776 control->msrpm_base_pa = __pa(svm->msrpm);
777 control->int_ctl = V_INTR_MASKING_MASK;
778
779 init_seg(&save->es);
780 init_seg(&save->ss);
781 init_seg(&save->ds);
782 init_seg(&save->fs);
783 init_seg(&save->gs);
784
785 save->cs.selector = 0xf000;
786 /* Executable/Readable Code Segment */
787 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
788 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
789 save->cs.limit = 0xffff;
790 /*
791 * cs.base should really be 0xffff0000, but vmx can't handle that, so
792 * be consistent with it.
793 *
794 * Replace when we have real mode working for vmx.
795 */
796 save->cs.base = 0xf0000;
797
798 save->gdtr.limit = 0xffff;
799 save->idtr.limit = 0xffff;
800
801 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
802 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
803
804 save->efer = EFER_SVME;
805 save->dr6 = 0xffff0ff0;
806 save->dr7 = 0x400;
807 save->rflags = 2;
808 save->rip = 0x0000fff0;
809 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
810
811 /*
812 * This is the guest-visible cr0 value.
813 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
814 */
815 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
816 (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
817
818 save->cr4 = X86_CR4_PAE;
819 /* rdx = ?? */
820
821 if (npt_enabled) {
822 /* Setup VMCB for Nested Paging */
823 control->nested_ctl = 1;
824 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
825 (1ULL << INTERCEPT_INVLPG));
826 control->intercept_exceptions &= ~(1 << PF_VECTOR);
827 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
828 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
829 save->g_pat = 0x0007040600070406ULL;
830 save->cr3 = 0;
831 save->cr4 = 0;
832 }
833 force_new_asid(&svm->vcpu);
834
835 svm->nested.vmcb = 0;
836 svm->vcpu.arch.hflags = 0;
837
838 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
839 control->pause_filter_count = 3000;
840 control->intercept |= (1ULL << INTERCEPT_PAUSE);
841 }
842
843 enable_gif(svm);
844 }
845
846 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
847 {
848 struct vcpu_svm *svm = to_svm(vcpu);
849
850 init_vmcb(svm);
851
852 if (!kvm_vcpu_is_bsp(vcpu)) {
853 kvm_rip_write(vcpu, 0);
854 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
855 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
856 }
857 vcpu->arch.regs_avail = ~0;
858 vcpu->arch.regs_dirty = ~0;
859
860 return 0;
861 }
862
863 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
864 {
865 struct vcpu_svm *svm;
866 struct page *page;
867 struct page *msrpm_pages;
868 struct page *hsave_page;
869 struct page *nested_msrpm_pages;
870 int err;
871
872 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
873 if (!svm) {
874 err = -ENOMEM;
875 goto out;
876 }
877
878 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
879 if (err)
880 goto free_svm;
881
882 err = -ENOMEM;
883 page = alloc_page(GFP_KERNEL);
884 if (!page)
885 goto uninit;
886
887 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
888 if (!msrpm_pages)
889 goto free_page1;
890
891 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
892 if (!nested_msrpm_pages)
893 goto free_page2;
894
895 hsave_page = alloc_page(GFP_KERNEL);
896 if (!hsave_page)
897 goto free_page3;
898
899 svm->nested.hsave = page_address(hsave_page);
900
901 svm->msrpm = page_address(msrpm_pages);
902 svm_vcpu_init_msrpm(svm->msrpm);
903
904 svm->nested.msrpm = page_address(nested_msrpm_pages);
905 svm_vcpu_init_msrpm(svm->nested.msrpm);
906
907 svm->vmcb = page_address(page);
908 clear_page(svm->vmcb);
909 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
910 svm->asid_generation = 0;
911 init_vmcb(svm);
912 svm->vmcb->control.tsc_offset = 0-native_read_tsc();
913
914 err = fx_init(&svm->vcpu);
915 if (err)
916 goto free_page4;
917
918 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
919 if (kvm_vcpu_is_bsp(&svm->vcpu))
920 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
921
922 return &svm->vcpu;
923
924 free_page4:
925 __free_page(hsave_page);
926 free_page3:
927 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
928 free_page2:
929 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
930 free_page1:
931 __free_page(page);
932 uninit:
933 kvm_vcpu_uninit(&svm->vcpu);
934 free_svm:
935 kmem_cache_free(kvm_vcpu_cache, svm);
936 out:
937 return ERR_PTR(err);
938 }
939
940 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
941 {
942 struct vcpu_svm *svm = to_svm(vcpu);
943
944 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
945 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
946 __free_page(virt_to_page(svm->nested.hsave));
947 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
948 kvm_vcpu_uninit(vcpu);
949 kmem_cache_free(kvm_vcpu_cache, svm);
950 }
951
952 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
953 {
954 struct vcpu_svm *svm = to_svm(vcpu);
955 int i;
956
957 if (unlikely(cpu != vcpu->cpu)) {
958 u64 delta;
959
960 if (check_tsc_unstable()) {
961 /*
962 * Make sure that the guest sees a monotonically
963 * increasing TSC.
964 */
965 delta = vcpu->arch.host_tsc - native_read_tsc();
966 svm->vmcb->control.tsc_offset += delta;
967 if (is_nested(svm))
968 svm->nested.hsave->control.tsc_offset += delta;
969 }
970 vcpu->cpu = cpu;
971 kvm_migrate_timers(vcpu);
972 svm->asid_generation = 0;
973 }
974
975 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
976 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
977 }
978
979 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
980 {
981 struct vcpu_svm *svm = to_svm(vcpu);
982 int i;
983
984 ++vcpu->stat.host_state_reload;
985 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
986 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
987
988 vcpu->arch.host_tsc = native_read_tsc();
989 }
990
991 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
992 {
993 return to_svm(vcpu)->vmcb->save.rflags;
994 }
995
996 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
997 {
998 to_svm(vcpu)->vmcb->save.rflags = rflags;
999 }
1000
1001 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1002 {
1003 switch (reg) {
1004 case VCPU_EXREG_PDPTR:
1005 BUG_ON(!npt_enabled);
1006 load_pdptrs(vcpu, vcpu->arch.cr3);
1007 break;
1008 default:
1009 BUG();
1010 }
1011 }
1012
1013 static void svm_set_vintr(struct vcpu_svm *svm)
1014 {
1015 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1016 }
1017
1018 static void svm_clear_vintr(struct vcpu_svm *svm)
1019 {
1020 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1021 }
1022
1023 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1024 {
1025 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1026
1027 switch (seg) {
1028 case VCPU_SREG_CS: return &save->cs;
1029 case VCPU_SREG_DS: return &save->ds;
1030 case VCPU_SREG_ES: return &save->es;
1031 case VCPU_SREG_FS: return &save->fs;
1032 case VCPU_SREG_GS: return &save->gs;
1033 case VCPU_SREG_SS: return &save->ss;
1034 case VCPU_SREG_TR: return &save->tr;
1035 case VCPU_SREG_LDTR: return &save->ldtr;
1036 }
1037 BUG();
1038 return NULL;
1039 }
1040
1041 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1042 {
1043 struct vmcb_seg *s = svm_seg(vcpu, seg);
1044
1045 return s->base;
1046 }
1047
1048 static void svm_get_segment(struct kvm_vcpu *vcpu,
1049 struct kvm_segment *var, int seg)
1050 {
1051 struct vmcb_seg *s = svm_seg(vcpu, seg);
1052
1053 var->base = s->base;
1054 var->limit = s->limit;
1055 var->selector = s->selector;
1056 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1057 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1058 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1059 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1060 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1061 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1062 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1063 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1064
1065 /*
1066 * AMD's VMCB does not have an explicit unusable field, so emulate it
1067 * for cross vendor migration purposes by "not present"
1068 */
1069 var->unusable = !var->present || (var->type == 0);
1070
1071 switch (seg) {
1072 case VCPU_SREG_CS:
1073 /*
1074 * SVM always stores 0 for the 'G' bit in the CS selector in
1075 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1076 * Intel's VMENTRY has a check on the 'G' bit.
1077 */
1078 var->g = s->limit > 0xfffff;
1079 break;
1080 case VCPU_SREG_TR:
1081 var->type |= 0x2;
1082 break;
1083 case VCPU_SREG_DS:
1084 case VCPU_SREG_ES:
1085 case VCPU_SREG_FS:
1086 case VCPU_SREG_GS:
1087 /*
1088 * The accessed bit must always be set in the segment
1089 * descriptor cache, although it can be cleared in the
1090 * descriptor, the cached bit always remains at 1. Since
1091 * Intel has a check on this, set it here to support
1092 * cross-vendor migration.
1093 */
1094 if (!var->unusable)
1095 var->type |= 0x1;
1096 break;
1097 case VCPU_SREG_SS:
1098 /*
1099 * On AMD CPUs sometimes the DB bit in the segment
1100 * descriptor is left as 1, although the whole segment has
1101 * been made unusable. Clear it here to pass an Intel VMX
1102 * entry check when cross vendor migrating.
1103 */
1104 if (var->unusable)
1105 var->db = 0;
1106 break;
1107 }
1108 }
1109
1110 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1111 {
1112 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1113
1114 return save->cpl;
1115 }
1116
1117 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1118 {
1119 struct vcpu_svm *svm = to_svm(vcpu);
1120
1121 dt->size = svm->vmcb->save.idtr.limit;
1122 dt->address = svm->vmcb->save.idtr.base;
1123 }
1124
1125 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1126 {
1127 struct vcpu_svm *svm = to_svm(vcpu);
1128
1129 svm->vmcb->save.idtr.limit = dt->size;
1130 svm->vmcb->save.idtr.base = dt->address ;
1131 }
1132
1133 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1134 {
1135 struct vcpu_svm *svm = to_svm(vcpu);
1136
1137 dt->size = svm->vmcb->save.gdtr.limit;
1138 dt->address = svm->vmcb->save.gdtr.base;
1139 }
1140
1141 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1142 {
1143 struct vcpu_svm *svm = to_svm(vcpu);
1144
1145 svm->vmcb->save.gdtr.limit = dt->size;
1146 svm->vmcb->save.gdtr.base = dt->address ;
1147 }
1148
1149 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1150 {
1151 }
1152
1153 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1154 {
1155 }
1156
1157 static void update_cr0_intercept(struct vcpu_svm *svm)
1158 {
1159 struct vmcb *vmcb = svm->vmcb;
1160 ulong gcr0 = svm->vcpu.arch.cr0;
1161 u64 *hcr0 = &svm->vmcb->save.cr0;
1162
1163 if (!svm->vcpu.fpu_active)
1164 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1165 else
1166 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1167 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1168
1169
1170 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1171 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1172 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1173 if (is_nested(svm)) {
1174 struct vmcb *hsave = svm->nested.hsave;
1175
1176 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1177 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1178 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1179 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1180 }
1181 } else {
1182 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1183 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1184 if (is_nested(svm)) {
1185 struct vmcb *hsave = svm->nested.hsave;
1186
1187 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1188 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1189 }
1190 }
1191 }
1192
1193 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1194 {
1195 struct vcpu_svm *svm = to_svm(vcpu);
1196
1197 if (is_nested(svm)) {
1198 /*
1199 * We are here because we run in nested mode, the host kvm
1200 * intercepts cr0 writes but the l1 hypervisor does not.
1201 * But the L1 hypervisor may intercept selective cr0 writes.
1202 * This needs to be checked here.
1203 */
1204 unsigned long old, new;
1205
1206 /* Remove bits that would trigger a real cr0 write intercept */
1207 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1208 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1209
1210 if (old == new) {
1211 /* cr0 write with ts and mp unchanged */
1212 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1213 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1214 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1215 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1216 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1217 return;
1218 }
1219 }
1220 }
1221
1222 #ifdef CONFIG_X86_64
1223 if (vcpu->arch.efer & EFER_LME) {
1224 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1225 vcpu->arch.efer |= EFER_LMA;
1226 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1227 }
1228
1229 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1230 vcpu->arch.efer &= ~EFER_LMA;
1231 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1232 }
1233 }
1234 #endif
1235 vcpu->arch.cr0 = cr0;
1236
1237 if (!npt_enabled)
1238 cr0 |= X86_CR0_PG | X86_CR0_WP;
1239
1240 if (!vcpu->fpu_active)
1241 cr0 |= X86_CR0_TS;
1242 /*
1243 * re-enable caching here because the QEMU bios
1244 * does not do it - this results in some delay at
1245 * reboot
1246 */
1247 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1248 svm->vmcb->save.cr0 = cr0;
1249 update_cr0_intercept(svm);
1250 }
1251
1252 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1253 {
1254 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1255 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1256
1257 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1258 force_new_asid(vcpu);
1259
1260 vcpu->arch.cr4 = cr4;
1261 if (!npt_enabled)
1262 cr4 |= X86_CR4_PAE;
1263 cr4 |= host_cr4_mce;
1264 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1265 }
1266
1267 static void svm_set_segment(struct kvm_vcpu *vcpu,
1268 struct kvm_segment *var, int seg)
1269 {
1270 struct vcpu_svm *svm = to_svm(vcpu);
1271 struct vmcb_seg *s = svm_seg(vcpu, seg);
1272
1273 s->base = var->base;
1274 s->limit = var->limit;
1275 s->selector = var->selector;
1276 if (var->unusable)
1277 s->attrib = 0;
1278 else {
1279 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1280 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1281 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1282 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1283 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1284 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1285 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1286 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1287 }
1288 if (seg == VCPU_SREG_CS)
1289 svm->vmcb->save.cpl
1290 = (svm->vmcb->save.cs.attrib
1291 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1292
1293 }
1294
1295 static void update_db_intercept(struct kvm_vcpu *vcpu)
1296 {
1297 struct vcpu_svm *svm = to_svm(vcpu);
1298
1299 svm->vmcb->control.intercept_exceptions &=
1300 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1301
1302 if (svm->nmi_singlestep)
1303 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1304
1305 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1306 if (vcpu->guest_debug &
1307 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1308 svm->vmcb->control.intercept_exceptions |=
1309 1 << DB_VECTOR;
1310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1311 svm->vmcb->control.intercept_exceptions |=
1312 1 << BP_VECTOR;
1313 } else
1314 vcpu->guest_debug = 0;
1315 }
1316
1317 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1318 {
1319 struct vcpu_svm *svm = to_svm(vcpu);
1320
1321 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1322 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1323 else
1324 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1325
1326 update_db_intercept(vcpu);
1327 }
1328
1329 static void load_host_msrs(struct kvm_vcpu *vcpu)
1330 {
1331 #ifdef CONFIG_X86_64
1332 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1333 #endif
1334 }
1335
1336 static void save_host_msrs(struct kvm_vcpu *vcpu)
1337 {
1338 #ifdef CONFIG_X86_64
1339 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1340 #endif
1341 }
1342
1343 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1344 {
1345 if (sd->next_asid > sd->max_asid) {
1346 ++sd->asid_generation;
1347 sd->next_asid = 1;
1348 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1349 }
1350
1351 svm->asid_generation = sd->asid_generation;
1352 svm->vmcb->control.asid = sd->next_asid++;
1353 }
1354
1355 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1356 {
1357 struct vcpu_svm *svm = to_svm(vcpu);
1358
1359 svm->vmcb->save.dr7 = value;
1360 }
1361
1362 static int pf_interception(struct vcpu_svm *svm)
1363 {
1364 u64 fault_address;
1365 u32 error_code;
1366
1367 fault_address = svm->vmcb->control.exit_info_2;
1368 error_code = svm->vmcb->control.exit_info_1;
1369
1370 trace_kvm_page_fault(fault_address, error_code);
1371 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1372 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1373 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1374 }
1375
1376 static int db_interception(struct vcpu_svm *svm)
1377 {
1378 struct kvm_run *kvm_run = svm->vcpu.run;
1379
1380 if (!(svm->vcpu.guest_debug &
1381 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1382 !svm->nmi_singlestep) {
1383 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1384 return 1;
1385 }
1386
1387 if (svm->nmi_singlestep) {
1388 svm->nmi_singlestep = false;
1389 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1390 svm->vmcb->save.rflags &=
1391 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1392 update_db_intercept(&svm->vcpu);
1393 }
1394
1395 if (svm->vcpu.guest_debug &
1396 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1397 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1398 kvm_run->debug.arch.pc =
1399 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1400 kvm_run->debug.arch.exception = DB_VECTOR;
1401 return 0;
1402 }
1403
1404 return 1;
1405 }
1406
1407 static int bp_interception(struct vcpu_svm *svm)
1408 {
1409 struct kvm_run *kvm_run = svm->vcpu.run;
1410
1411 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1412 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1413 kvm_run->debug.arch.exception = BP_VECTOR;
1414 return 0;
1415 }
1416
1417 static int ud_interception(struct vcpu_svm *svm)
1418 {
1419 int er;
1420
1421 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1422 if (er != EMULATE_DONE)
1423 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1424 return 1;
1425 }
1426
1427 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1428 {
1429 struct vcpu_svm *svm = to_svm(vcpu);
1430 u32 excp;
1431
1432 if (is_nested(svm)) {
1433 u32 h_excp, n_excp;
1434
1435 h_excp = svm->nested.hsave->control.intercept_exceptions;
1436 n_excp = svm->nested.intercept_exceptions;
1437 h_excp &= ~(1 << NM_VECTOR);
1438 excp = h_excp | n_excp;
1439 } else {
1440 excp = svm->vmcb->control.intercept_exceptions;
1441 excp &= ~(1 << NM_VECTOR);
1442 }
1443
1444 svm->vmcb->control.intercept_exceptions = excp;
1445
1446 svm->vcpu.fpu_active = 1;
1447 update_cr0_intercept(svm);
1448 }
1449
1450 static int nm_interception(struct vcpu_svm *svm)
1451 {
1452 svm_fpu_activate(&svm->vcpu);
1453 return 1;
1454 }
1455
1456 static bool is_erratum_383(void)
1457 {
1458 int err, i;
1459 u64 value;
1460
1461 if (!erratum_383_found)
1462 return false;
1463
1464 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1465 if (err)
1466 return false;
1467
1468 /* Bit 62 may or may not be set for this mce */
1469 value &= ~(1ULL << 62);
1470
1471 if (value != 0xb600000000010015ULL)
1472 return false;
1473
1474 /* Clear MCi_STATUS registers */
1475 for (i = 0; i < 6; ++i)
1476 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1477
1478 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1479 if (!err) {
1480 u32 low, high;
1481
1482 value &= ~(1ULL << 2);
1483 low = lower_32_bits(value);
1484 high = upper_32_bits(value);
1485
1486 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1487 }
1488
1489 /* Flush tlb to evict multi-match entries */
1490 __flush_tlb_all();
1491
1492 return true;
1493 }
1494
1495 static void svm_handle_mce(struct vcpu_svm *svm)
1496 {
1497 if (is_erratum_383()) {
1498 /*
1499 * Erratum 383 triggered. Guest state is corrupt so kill the
1500 * guest.
1501 */
1502 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1503
1504 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1505
1506 return;
1507 }
1508
1509 /*
1510 * On an #MC intercept the MCE handler is not called automatically in
1511 * the host. So do it by hand here.
1512 */
1513 asm volatile (
1514 "int $0x12\n");
1515 /* not sure if we ever come back to this point */
1516
1517 return;
1518 }
1519
1520 static int mc_interception(struct vcpu_svm *svm)
1521 {
1522 return 1;
1523 }
1524
1525 static int shutdown_interception(struct vcpu_svm *svm)
1526 {
1527 struct kvm_run *kvm_run = svm->vcpu.run;
1528
1529 /*
1530 * VMCB is undefined after a SHUTDOWN intercept
1531 * so reinitialize it.
1532 */
1533 clear_page(svm->vmcb);
1534 init_vmcb(svm);
1535
1536 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1537 return 0;
1538 }
1539
1540 static int io_interception(struct vcpu_svm *svm)
1541 {
1542 struct kvm_vcpu *vcpu = &svm->vcpu;
1543 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1544 int size, in, string;
1545 unsigned port;
1546
1547 ++svm->vcpu.stat.io_exits;
1548 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1549 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1550 if (string || in)
1551 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1552
1553 port = io_info >> 16;
1554 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1555 svm->next_rip = svm->vmcb->control.exit_info_2;
1556 skip_emulated_instruction(&svm->vcpu);
1557
1558 return kvm_fast_pio_out(vcpu, size, port);
1559 }
1560
1561 static int nmi_interception(struct vcpu_svm *svm)
1562 {
1563 return 1;
1564 }
1565
1566 static int intr_interception(struct vcpu_svm *svm)
1567 {
1568 ++svm->vcpu.stat.irq_exits;
1569 return 1;
1570 }
1571
1572 static int nop_on_interception(struct vcpu_svm *svm)
1573 {
1574 return 1;
1575 }
1576
1577 static int halt_interception(struct vcpu_svm *svm)
1578 {
1579 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1580 skip_emulated_instruction(&svm->vcpu);
1581 return kvm_emulate_halt(&svm->vcpu);
1582 }
1583
1584 static int vmmcall_interception(struct vcpu_svm *svm)
1585 {
1586 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1587 skip_emulated_instruction(&svm->vcpu);
1588 kvm_emulate_hypercall(&svm->vcpu);
1589 return 1;
1590 }
1591
1592 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1593 {
1594 if (!(svm->vcpu.arch.efer & EFER_SVME)
1595 || !is_paging(&svm->vcpu)) {
1596 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1597 return 1;
1598 }
1599
1600 if (svm->vmcb->save.cpl) {
1601 kvm_inject_gp(&svm->vcpu, 0);
1602 return 1;
1603 }
1604
1605 return 0;
1606 }
1607
1608 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1609 bool has_error_code, u32 error_code)
1610 {
1611 int vmexit;
1612
1613 if (!is_nested(svm))
1614 return 0;
1615
1616 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1617 svm->vmcb->control.exit_code_hi = 0;
1618 svm->vmcb->control.exit_info_1 = error_code;
1619 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1620
1621 vmexit = nested_svm_intercept(svm);
1622 if (vmexit == NESTED_EXIT_DONE)
1623 svm->nested.exit_required = true;
1624
1625 return vmexit;
1626 }
1627
1628 /* This function returns true if it is save to enable the irq window */
1629 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1630 {
1631 if (!is_nested(svm))
1632 return true;
1633
1634 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1635 return true;
1636
1637 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1638 return false;
1639
1640 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1641 svm->vmcb->control.exit_info_1 = 0;
1642 svm->vmcb->control.exit_info_2 = 0;
1643
1644 if (svm->nested.intercept & 1ULL) {
1645 /*
1646 * The #vmexit can't be emulated here directly because this
1647 * code path runs with irqs and preemtion disabled. A
1648 * #vmexit emulation might sleep. Only signal request for
1649 * the #vmexit here.
1650 */
1651 svm->nested.exit_required = true;
1652 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1653 return false;
1654 }
1655
1656 return true;
1657 }
1658
1659 /* This function returns true if it is save to enable the nmi window */
1660 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1661 {
1662 if (!is_nested(svm))
1663 return true;
1664
1665 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1666 return true;
1667
1668 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1669 svm->nested.exit_required = true;
1670
1671 return false;
1672 }
1673
1674 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1675 {
1676 struct page *page;
1677
1678 might_sleep();
1679
1680 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1681 if (is_error_page(page))
1682 goto error;
1683
1684 *_page = page;
1685
1686 return kmap(page);
1687
1688 error:
1689 kvm_release_page_clean(page);
1690 kvm_inject_gp(&svm->vcpu, 0);
1691
1692 return NULL;
1693 }
1694
1695 static void nested_svm_unmap(struct page *page)
1696 {
1697 kunmap(page);
1698 kvm_release_page_dirty(page);
1699 }
1700
1701 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1702 {
1703 unsigned port;
1704 u8 val, bit;
1705 u64 gpa;
1706
1707 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1708 return NESTED_EXIT_HOST;
1709
1710 port = svm->vmcb->control.exit_info_1 >> 16;
1711 gpa = svm->nested.vmcb_iopm + (port / 8);
1712 bit = port % 8;
1713 val = 0;
1714
1715 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1716 val &= (1 << bit);
1717
1718 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1719 }
1720
1721 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1722 {
1723 u32 offset, msr, value;
1724 int write, mask;
1725
1726 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1727 return NESTED_EXIT_HOST;
1728
1729 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1730 offset = svm_msrpm_offset(msr);
1731 write = svm->vmcb->control.exit_info_1 & 1;
1732 mask = 1 << ((2 * (msr & 0xf)) + write);
1733
1734 if (offset == MSR_INVALID)
1735 return NESTED_EXIT_DONE;
1736
1737 /* Offset is in 32 bit units but need in 8 bit units */
1738 offset *= 4;
1739
1740 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1741 return NESTED_EXIT_DONE;
1742
1743 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1744 }
1745
1746 static int nested_svm_exit_special(struct vcpu_svm *svm)
1747 {
1748 u32 exit_code = svm->vmcb->control.exit_code;
1749
1750 switch (exit_code) {
1751 case SVM_EXIT_INTR:
1752 case SVM_EXIT_NMI:
1753 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1754 return NESTED_EXIT_HOST;
1755 case SVM_EXIT_NPF:
1756 /* For now we are always handling NPFs when using them */
1757 if (npt_enabled)
1758 return NESTED_EXIT_HOST;
1759 break;
1760 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1761 /* When we're shadowing, trap PFs */
1762 if (!npt_enabled)
1763 return NESTED_EXIT_HOST;
1764 break;
1765 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1766 nm_interception(svm);
1767 break;
1768 default:
1769 break;
1770 }
1771
1772 return NESTED_EXIT_CONTINUE;
1773 }
1774
1775 /*
1776 * If this function returns true, this #vmexit was already handled
1777 */
1778 static int nested_svm_intercept(struct vcpu_svm *svm)
1779 {
1780 u32 exit_code = svm->vmcb->control.exit_code;
1781 int vmexit = NESTED_EXIT_HOST;
1782
1783 switch (exit_code) {
1784 case SVM_EXIT_MSR:
1785 vmexit = nested_svm_exit_handled_msr(svm);
1786 break;
1787 case SVM_EXIT_IOIO:
1788 vmexit = nested_svm_intercept_ioio(svm);
1789 break;
1790 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1791 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1792 if (svm->nested.intercept_cr_read & cr_bits)
1793 vmexit = NESTED_EXIT_DONE;
1794 break;
1795 }
1796 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1797 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1798 if (svm->nested.intercept_cr_write & cr_bits)
1799 vmexit = NESTED_EXIT_DONE;
1800 break;
1801 }
1802 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1803 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1804 if (svm->nested.intercept_dr_read & dr_bits)
1805 vmexit = NESTED_EXIT_DONE;
1806 break;
1807 }
1808 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1809 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1810 if (svm->nested.intercept_dr_write & dr_bits)
1811 vmexit = NESTED_EXIT_DONE;
1812 break;
1813 }
1814 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1815 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1816 if (svm->nested.intercept_exceptions & excp_bits)
1817 vmexit = NESTED_EXIT_DONE;
1818 break;
1819 }
1820 case SVM_EXIT_ERR: {
1821 vmexit = NESTED_EXIT_DONE;
1822 break;
1823 }
1824 default: {
1825 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1826 if (svm->nested.intercept & exit_bits)
1827 vmexit = NESTED_EXIT_DONE;
1828 }
1829 }
1830
1831 return vmexit;
1832 }
1833
1834 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1835 {
1836 int vmexit;
1837
1838 vmexit = nested_svm_intercept(svm);
1839
1840 if (vmexit == NESTED_EXIT_DONE)
1841 nested_svm_vmexit(svm);
1842
1843 return vmexit;
1844 }
1845
1846 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1847 {
1848 struct vmcb_control_area *dst = &dst_vmcb->control;
1849 struct vmcb_control_area *from = &from_vmcb->control;
1850
1851 dst->intercept_cr_read = from->intercept_cr_read;
1852 dst->intercept_cr_write = from->intercept_cr_write;
1853 dst->intercept_dr_read = from->intercept_dr_read;
1854 dst->intercept_dr_write = from->intercept_dr_write;
1855 dst->intercept_exceptions = from->intercept_exceptions;
1856 dst->intercept = from->intercept;
1857 dst->iopm_base_pa = from->iopm_base_pa;
1858 dst->msrpm_base_pa = from->msrpm_base_pa;
1859 dst->tsc_offset = from->tsc_offset;
1860 dst->asid = from->asid;
1861 dst->tlb_ctl = from->tlb_ctl;
1862 dst->int_ctl = from->int_ctl;
1863 dst->int_vector = from->int_vector;
1864 dst->int_state = from->int_state;
1865 dst->exit_code = from->exit_code;
1866 dst->exit_code_hi = from->exit_code_hi;
1867 dst->exit_info_1 = from->exit_info_1;
1868 dst->exit_info_2 = from->exit_info_2;
1869 dst->exit_int_info = from->exit_int_info;
1870 dst->exit_int_info_err = from->exit_int_info_err;
1871 dst->nested_ctl = from->nested_ctl;
1872 dst->event_inj = from->event_inj;
1873 dst->event_inj_err = from->event_inj_err;
1874 dst->nested_cr3 = from->nested_cr3;
1875 dst->lbr_ctl = from->lbr_ctl;
1876 }
1877
1878 static int nested_svm_vmexit(struct vcpu_svm *svm)
1879 {
1880 struct vmcb *nested_vmcb;
1881 struct vmcb *hsave = svm->nested.hsave;
1882 struct vmcb *vmcb = svm->vmcb;
1883 struct page *page;
1884
1885 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1886 vmcb->control.exit_info_1,
1887 vmcb->control.exit_info_2,
1888 vmcb->control.exit_int_info,
1889 vmcb->control.exit_int_info_err);
1890
1891 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1892 if (!nested_vmcb)
1893 return 1;
1894
1895 /* Exit nested SVM mode */
1896 svm->nested.vmcb = 0;
1897
1898 /* Give the current vmcb to the guest */
1899 disable_gif(svm);
1900
1901 nested_vmcb->save.es = vmcb->save.es;
1902 nested_vmcb->save.cs = vmcb->save.cs;
1903 nested_vmcb->save.ss = vmcb->save.ss;
1904 nested_vmcb->save.ds = vmcb->save.ds;
1905 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1906 nested_vmcb->save.idtr = vmcb->save.idtr;
1907 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1908 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1909 nested_vmcb->save.cr2 = vmcb->save.cr2;
1910 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1911 nested_vmcb->save.rflags = vmcb->save.rflags;
1912 nested_vmcb->save.rip = vmcb->save.rip;
1913 nested_vmcb->save.rsp = vmcb->save.rsp;
1914 nested_vmcb->save.rax = vmcb->save.rax;
1915 nested_vmcb->save.dr7 = vmcb->save.dr7;
1916 nested_vmcb->save.dr6 = vmcb->save.dr6;
1917 nested_vmcb->save.cpl = vmcb->save.cpl;
1918
1919 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1920 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1921 nested_vmcb->control.int_state = vmcb->control.int_state;
1922 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1923 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1924 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1925 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1926 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1927 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1928
1929 /*
1930 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1931 * to make sure that we do not lose injected events. So check event_inj
1932 * here and copy it to exit_int_info if it is valid.
1933 * Exit_int_info and event_inj can't be both valid because the case
1934 * below only happens on a VMRUN instruction intercept which has
1935 * no valid exit_int_info set.
1936 */
1937 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1938 struct vmcb_control_area *nc = &nested_vmcb->control;
1939
1940 nc->exit_int_info = vmcb->control.event_inj;
1941 nc->exit_int_info_err = vmcb->control.event_inj_err;
1942 }
1943
1944 nested_vmcb->control.tlb_ctl = 0;
1945 nested_vmcb->control.event_inj = 0;
1946 nested_vmcb->control.event_inj_err = 0;
1947
1948 /* We always set V_INTR_MASKING and remember the old value in hflags */
1949 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1950 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1951
1952 /* Restore the original control entries */
1953 copy_vmcb_control_area(vmcb, hsave);
1954
1955 kvm_clear_exception_queue(&svm->vcpu);
1956 kvm_clear_interrupt_queue(&svm->vcpu);
1957
1958 /* Restore selected save entries */
1959 svm->vmcb->save.es = hsave->save.es;
1960 svm->vmcb->save.cs = hsave->save.cs;
1961 svm->vmcb->save.ss = hsave->save.ss;
1962 svm->vmcb->save.ds = hsave->save.ds;
1963 svm->vmcb->save.gdtr = hsave->save.gdtr;
1964 svm->vmcb->save.idtr = hsave->save.idtr;
1965 svm->vmcb->save.rflags = hsave->save.rflags;
1966 svm_set_efer(&svm->vcpu, hsave->save.efer);
1967 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1968 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1969 if (npt_enabled) {
1970 svm->vmcb->save.cr3 = hsave->save.cr3;
1971 svm->vcpu.arch.cr3 = hsave->save.cr3;
1972 } else {
1973 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1974 }
1975 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1976 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1977 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1978 svm->vmcb->save.dr7 = 0;
1979 svm->vmcb->save.cpl = 0;
1980 svm->vmcb->control.exit_int_info = 0;
1981
1982 nested_svm_unmap(page);
1983
1984 kvm_mmu_reset_context(&svm->vcpu);
1985 kvm_mmu_load(&svm->vcpu);
1986
1987 return 0;
1988 }
1989
1990 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1991 {
1992 /*
1993 * This function merges the msr permission bitmaps of kvm and the
1994 * nested vmcb. It is omptimized in that it only merges the parts where
1995 * the kvm msr permission bitmap may contain zero bits
1996 */
1997 int i;
1998
1999 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2000 return true;
2001
2002 for (i = 0; i < MSRPM_OFFSETS; i++) {
2003 u32 value, p;
2004 u64 offset;
2005
2006 if (msrpm_offsets[i] == 0xffffffff)
2007 break;
2008
2009 p = msrpm_offsets[i];
2010 offset = svm->nested.vmcb_msrpm + (p * 4);
2011
2012 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2013 return false;
2014
2015 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2016 }
2017
2018 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2019
2020 return true;
2021 }
2022
2023 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2024 {
2025 struct vmcb *nested_vmcb;
2026 struct vmcb *hsave = svm->nested.hsave;
2027 struct vmcb *vmcb = svm->vmcb;
2028 struct page *page;
2029 u64 vmcb_gpa;
2030
2031 vmcb_gpa = svm->vmcb->save.rax;
2032
2033 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2034 if (!nested_vmcb)
2035 return false;
2036
2037 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
2038 nested_vmcb->save.rip,
2039 nested_vmcb->control.int_ctl,
2040 nested_vmcb->control.event_inj,
2041 nested_vmcb->control.nested_ctl);
2042
2043 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2044 nested_vmcb->control.intercept_cr_write,
2045 nested_vmcb->control.intercept_exceptions,
2046 nested_vmcb->control.intercept);
2047
2048 /* Clear internal status */
2049 kvm_clear_exception_queue(&svm->vcpu);
2050 kvm_clear_interrupt_queue(&svm->vcpu);
2051
2052 /*
2053 * Save the old vmcb, so we don't need to pick what we save, but can
2054 * restore everything when a VMEXIT occurs
2055 */
2056 hsave->save.es = vmcb->save.es;
2057 hsave->save.cs = vmcb->save.cs;
2058 hsave->save.ss = vmcb->save.ss;
2059 hsave->save.ds = vmcb->save.ds;
2060 hsave->save.gdtr = vmcb->save.gdtr;
2061 hsave->save.idtr = vmcb->save.idtr;
2062 hsave->save.efer = svm->vcpu.arch.efer;
2063 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2064 hsave->save.cr4 = svm->vcpu.arch.cr4;
2065 hsave->save.rflags = vmcb->save.rflags;
2066 hsave->save.rip = svm->next_rip;
2067 hsave->save.rsp = vmcb->save.rsp;
2068 hsave->save.rax = vmcb->save.rax;
2069 if (npt_enabled)
2070 hsave->save.cr3 = vmcb->save.cr3;
2071 else
2072 hsave->save.cr3 = svm->vcpu.arch.cr3;
2073
2074 copy_vmcb_control_area(hsave, vmcb);
2075
2076 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2077 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2078 else
2079 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2080
2081 /* Load the nested guest state */
2082 svm->vmcb->save.es = nested_vmcb->save.es;
2083 svm->vmcb->save.cs = nested_vmcb->save.cs;
2084 svm->vmcb->save.ss = nested_vmcb->save.ss;
2085 svm->vmcb->save.ds = nested_vmcb->save.ds;
2086 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2087 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2088 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2089 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2090 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2091 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2092 if (npt_enabled) {
2093 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2094 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2095 } else
2096 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2097
2098 /* Guest paging mode is active - reset mmu */
2099 kvm_mmu_reset_context(&svm->vcpu);
2100
2101 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2102 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2103 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2104 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2105
2106 /* In case we don't even reach vcpu_run, the fields are not updated */
2107 svm->vmcb->save.rax = nested_vmcb->save.rax;
2108 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2109 svm->vmcb->save.rip = nested_vmcb->save.rip;
2110 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2111 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2112 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2113
2114 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2115 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2116
2117 /* cache intercepts */
2118 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2119 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2120 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2121 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2122 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2123 svm->nested.intercept = nested_vmcb->control.intercept;
2124
2125 force_new_asid(&svm->vcpu);
2126 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2127 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2128 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2129 else
2130 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2131
2132 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2133 /* We only want the cr8 intercept bits of the guest */
2134 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2135 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2136 }
2137
2138 /* We don't want to see VMMCALLs from a nested guest */
2139 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2140
2141 /*
2142 * We don't want a nested guest to be more powerful than the guest, so
2143 * all intercepts are ORed
2144 */
2145 svm->vmcb->control.intercept_cr_read |=
2146 nested_vmcb->control.intercept_cr_read;
2147 svm->vmcb->control.intercept_cr_write |=
2148 nested_vmcb->control.intercept_cr_write;
2149 svm->vmcb->control.intercept_dr_read |=
2150 nested_vmcb->control.intercept_dr_read;
2151 svm->vmcb->control.intercept_dr_write |=
2152 nested_vmcb->control.intercept_dr_write;
2153 svm->vmcb->control.intercept_exceptions |=
2154 nested_vmcb->control.intercept_exceptions;
2155
2156 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2157
2158 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2159 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2160 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2161 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2162 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2163 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2164
2165 nested_svm_unmap(page);
2166
2167 /* nested_vmcb is our indicator if nested SVM is activated */
2168 svm->nested.vmcb = vmcb_gpa;
2169
2170 enable_gif(svm);
2171
2172 return true;
2173 }
2174
2175 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2176 {
2177 to_vmcb->save.fs = from_vmcb->save.fs;
2178 to_vmcb->save.gs = from_vmcb->save.gs;
2179 to_vmcb->save.tr = from_vmcb->save.tr;
2180 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2181 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2182 to_vmcb->save.star = from_vmcb->save.star;
2183 to_vmcb->save.lstar = from_vmcb->save.lstar;
2184 to_vmcb->save.cstar = from_vmcb->save.cstar;
2185 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2186 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2187 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2188 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2189 }
2190
2191 static int vmload_interception(struct vcpu_svm *svm)
2192 {
2193 struct vmcb *nested_vmcb;
2194 struct page *page;
2195
2196 if (nested_svm_check_permissions(svm))
2197 return 1;
2198
2199 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2200 skip_emulated_instruction(&svm->vcpu);
2201
2202 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2203 if (!nested_vmcb)
2204 return 1;
2205
2206 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2207 nested_svm_unmap(page);
2208
2209 return 1;
2210 }
2211
2212 static int vmsave_interception(struct vcpu_svm *svm)
2213 {
2214 struct vmcb *nested_vmcb;
2215 struct page *page;
2216
2217 if (nested_svm_check_permissions(svm))
2218 return 1;
2219
2220 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2221 skip_emulated_instruction(&svm->vcpu);
2222
2223 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2224 if (!nested_vmcb)
2225 return 1;
2226
2227 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2228 nested_svm_unmap(page);
2229
2230 return 1;
2231 }
2232
2233 static int vmrun_interception(struct vcpu_svm *svm)
2234 {
2235 if (nested_svm_check_permissions(svm))
2236 return 1;
2237
2238 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2239 skip_emulated_instruction(&svm->vcpu);
2240
2241 if (!nested_svm_vmrun(svm))
2242 return 1;
2243
2244 if (!nested_svm_vmrun_msrpm(svm))
2245 goto failed;
2246
2247 return 1;
2248
2249 failed:
2250
2251 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2252 svm->vmcb->control.exit_code_hi = 0;
2253 svm->vmcb->control.exit_info_1 = 0;
2254 svm->vmcb->control.exit_info_2 = 0;
2255
2256 nested_svm_vmexit(svm);
2257
2258 return 1;
2259 }
2260
2261 static int stgi_interception(struct vcpu_svm *svm)
2262 {
2263 if (nested_svm_check_permissions(svm))
2264 return 1;
2265
2266 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2267 skip_emulated_instruction(&svm->vcpu);
2268
2269 enable_gif(svm);
2270
2271 return 1;
2272 }
2273
2274 static int clgi_interception(struct vcpu_svm *svm)
2275 {
2276 if (nested_svm_check_permissions(svm))
2277 return 1;
2278
2279 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2280 skip_emulated_instruction(&svm->vcpu);
2281
2282 disable_gif(svm);
2283
2284 /* After a CLGI no interrupts should come */
2285 svm_clear_vintr(svm);
2286 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2287
2288 return 1;
2289 }
2290
2291 static int invlpga_interception(struct vcpu_svm *svm)
2292 {
2293 struct kvm_vcpu *vcpu = &svm->vcpu;
2294
2295 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2296 vcpu->arch.regs[VCPU_REGS_RAX]);
2297
2298 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2299 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2300
2301 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2302 skip_emulated_instruction(&svm->vcpu);
2303 return 1;
2304 }
2305
2306 static int skinit_interception(struct vcpu_svm *svm)
2307 {
2308 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2309
2310 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2311 return 1;
2312 }
2313
2314 static int invalid_op_interception(struct vcpu_svm *svm)
2315 {
2316 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2317 return 1;
2318 }
2319
2320 static int task_switch_interception(struct vcpu_svm *svm)
2321 {
2322 u16 tss_selector;
2323 int reason;
2324 int int_type = svm->vmcb->control.exit_int_info &
2325 SVM_EXITINTINFO_TYPE_MASK;
2326 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2327 uint32_t type =
2328 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2329 uint32_t idt_v =
2330 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2331 bool has_error_code = false;
2332 u32 error_code = 0;
2333
2334 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2335
2336 if (svm->vmcb->control.exit_info_2 &
2337 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2338 reason = TASK_SWITCH_IRET;
2339 else if (svm->vmcb->control.exit_info_2 &
2340 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2341 reason = TASK_SWITCH_JMP;
2342 else if (idt_v)
2343 reason = TASK_SWITCH_GATE;
2344 else
2345 reason = TASK_SWITCH_CALL;
2346
2347 if (reason == TASK_SWITCH_GATE) {
2348 switch (type) {
2349 case SVM_EXITINTINFO_TYPE_NMI:
2350 svm->vcpu.arch.nmi_injected = false;
2351 break;
2352 case SVM_EXITINTINFO_TYPE_EXEPT:
2353 if (svm->vmcb->control.exit_info_2 &
2354 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2355 has_error_code = true;
2356 error_code =
2357 (u32)svm->vmcb->control.exit_info_2;
2358 }
2359 kvm_clear_exception_queue(&svm->vcpu);
2360 break;
2361 case SVM_EXITINTINFO_TYPE_INTR:
2362 kvm_clear_interrupt_queue(&svm->vcpu);
2363 break;
2364 default:
2365 break;
2366 }
2367 }
2368
2369 if (reason != TASK_SWITCH_GATE ||
2370 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2371 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2372 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2373 skip_emulated_instruction(&svm->vcpu);
2374
2375 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2376 has_error_code, error_code) == EMULATE_FAIL) {
2377 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2378 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2379 svm->vcpu.run->internal.ndata = 0;
2380 return 0;
2381 }
2382 return 1;
2383 }
2384
2385 static int cpuid_interception(struct vcpu_svm *svm)
2386 {
2387 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2388 kvm_emulate_cpuid(&svm->vcpu);
2389 return 1;
2390 }
2391
2392 static int iret_interception(struct vcpu_svm *svm)
2393 {
2394 ++svm->vcpu.stat.nmi_window_exits;
2395 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2396 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2397 return 1;
2398 }
2399
2400 static int invlpg_interception(struct vcpu_svm *svm)
2401 {
2402 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2403 }
2404
2405 static int emulate_on_interception(struct vcpu_svm *svm)
2406 {
2407 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2408 }
2409
2410 static int cr0_write_interception(struct vcpu_svm *svm)
2411 {
2412 struct kvm_vcpu *vcpu = &svm->vcpu;
2413 int r;
2414
2415 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2416
2417 if (svm->nested.vmexit_rip) {
2418 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2419 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2420 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2421 svm->nested.vmexit_rip = 0;
2422 }
2423
2424 return r == EMULATE_DONE;
2425 }
2426
2427 static int cr8_write_interception(struct vcpu_svm *svm)
2428 {
2429 struct kvm_run *kvm_run = svm->vcpu.run;
2430
2431 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2432 /* instruction emulation calls kvm_set_cr8() */
2433 emulate_instruction(&svm->vcpu, 0, 0, 0);
2434 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2435 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2436 return 1;
2437 }
2438 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2439 return 1;
2440 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2441 return 0;
2442 }
2443
2444 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2445 {
2446 struct vcpu_svm *svm = to_svm(vcpu);
2447
2448 switch (ecx) {
2449 case MSR_IA32_TSC: {
2450 u64 tsc_offset;
2451
2452 if (is_nested(svm))
2453 tsc_offset = svm->nested.hsave->control.tsc_offset;
2454 else
2455 tsc_offset = svm->vmcb->control.tsc_offset;
2456
2457 *data = tsc_offset + native_read_tsc();
2458 break;
2459 }
2460 case MSR_STAR:
2461 *data = svm->vmcb->save.star;
2462 break;
2463 #ifdef CONFIG_X86_64
2464 case MSR_LSTAR:
2465 *data = svm->vmcb->save.lstar;
2466 break;
2467 case MSR_CSTAR:
2468 *data = svm->vmcb->save.cstar;
2469 break;
2470 case MSR_KERNEL_GS_BASE:
2471 *data = svm->vmcb->save.kernel_gs_base;
2472 break;
2473 case MSR_SYSCALL_MASK:
2474 *data = svm->vmcb->save.sfmask;
2475 break;
2476 #endif
2477 case MSR_IA32_SYSENTER_CS:
2478 *data = svm->vmcb->save.sysenter_cs;
2479 break;
2480 case MSR_IA32_SYSENTER_EIP:
2481 *data = svm->sysenter_eip;
2482 break;
2483 case MSR_IA32_SYSENTER_ESP:
2484 *data = svm->sysenter_esp;
2485 break;
2486 /*
2487 * Nobody will change the following 5 values in the VMCB so we can
2488 * safely return them on rdmsr. They will always be 0 until LBRV is
2489 * implemented.
2490 */
2491 case MSR_IA32_DEBUGCTLMSR:
2492 *data = svm->vmcb->save.dbgctl;
2493 break;
2494 case MSR_IA32_LASTBRANCHFROMIP:
2495 *data = svm->vmcb->save.br_from;
2496 break;
2497 case MSR_IA32_LASTBRANCHTOIP:
2498 *data = svm->vmcb->save.br_to;
2499 break;
2500 case MSR_IA32_LASTINTFROMIP:
2501 *data = svm->vmcb->save.last_excp_from;
2502 break;
2503 case MSR_IA32_LASTINTTOIP:
2504 *data = svm->vmcb->save.last_excp_to;
2505 break;
2506 case MSR_VM_HSAVE_PA:
2507 *data = svm->nested.hsave_msr;
2508 break;
2509 case MSR_VM_CR:
2510 *data = svm->nested.vm_cr_msr;
2511 break;
2512 case MSR_IA32_UCODE_REV:
2513 *data = 0x01000065;
2514 break;
2515 default:
2516 return kvm_get_msr_common(vcpu, ecx, data);
2517 }
2518 return 0;
2519 }
2520
2521 static int rdmsr_interception(struct vcpu_svm *svm)
2522 {
2523 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2524 u64 data;
2525
2526 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2527 trace_kvm_msr_read_ex(ecx);
2528 kvm_inject_gp(&svm->vcpu, 0);
2529 } else {
2530 trace_kvm_msr_read(ecx, data);
2531
2532 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2533 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2534 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2535 skip_emulated_instruction(&svm->vcpu);
2536 }
2537 return 1;
2538 }
2539
2540 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2541 {
2542 struct vcpu_svm *svm = to_svm(vcpu);
2543 int svm_dis, chg_mask;
2544
2545 if (data & ~SVM_VM_CR_VALID_MASK)
2546 return 1;
2547
2548 chg_mask = SVM_VM_CR_VALID_MASK;
2549
2550 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2551 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2552
2553 svm->nested.vm_cr_msr &= ~chg_mask;
2554 svm->nested.vm_cr_msr |= (data & chg_mask);
2555
2556 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2557
2558 /* check for svm_disable while efer.svme is set */
2559 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2560 return 1;
2561
2562 return 0;
2563 }
2564
2565 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2566 {
2567 struct vcpu_svm *svm = to_svm(vcpu);
2568
2569 switch (ecx) {
2570 case MSR_IA32_TSC: {
2571 u64 tsc_offset = data - native_read_tsc();
2572 u64 g_tsc_offset = 0;
2573
2574 if (is_nested(svm)) {
2575 g_tsc_offset = svm->vmcb->control.tsc_offset -
2576 svm->nested.hsave->control.tsc_offset;
2577 svm->nested.hsave->control.tsc_offset = tsc_offset;
2578 }
2579
2580 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2581
2582 break;
2583 }
2584 case MSR_STAR:
2585 svm->vmcb->save.star = data;
2586 break;
2587 #ifdef CONFIG_X86_64
2588 case MSR_LSTAR:
2589 svm->vmcb->save.lstar = data;
2590 break;
2591 case MSR_CSTAR:
2592 svm->vmcb->save.cstar = data;
2593 break;
2594 case MSR_KERNEL_GS_BASE:
2595 svm->vmcb->save.kernel_gs_base = data;
2596 break;
2597 case MSR_SYSCALL_MASK:
2598 svm->vmcb->save.sfmask = data;
2599 break;
2600 #endif
2601 case MSR_IA32_SYSENTER_CS:
2602 svm->vmcb->save.sysenter_cs = data;
2603 break;
2604 case MSR_IA32_SYSENTER_EIP:
2605 svm->sysenter_eip = data;
2606 svm->vmcb->save.sysenter_eip = data;
2607 break;
2608 case MSR_IA32_SYSENTER_ESP:
2609 svm->sysenter_esp = data;
2610 svm->vmcb->save.sysenter_esp = data;
2611 break;
2612 case MSR_IA32_DEBUGCTLMSR:
2613 if (!svm_has(SVM_FEATURE_LBRV)) {
2614 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2615 __func__, data);
2616 break;
2617 }
2618 if (data & DEBUGCTL_RESERVED_BITS)
2619 return 1;
2620
2621 svm->vmcb->save.dbgctl = data;
2622 if (data & (1ULL<<0))
2623 svm_enable_lbrv(svm);
2624 else
2625 svm_disable_lbrv(svm);
2626 break;
2627 case MSR_VM_HSAVE_PA:
2628 svm->nested.hsave_msr = data;
2629 break;
2630 case MSR_VM_CR:
2631 return svm_set_vm_cr(vcpu, data);
2632 case MSR_VM_IGNNE:
2633 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2634 break;
2635 default:
2636 return kvm_set_msr_common(vcpu, ecx, data);
2637 }
2638 return 0;
2639 }
2640
2641 static int wrmsr_interception(struct vcpu_svm *svm)
2642 {
2643 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2644 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2645 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2646
2647
2648 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2649 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2650 trace_kvm_msr_write_ex(ecx, data);
2651 kvm_inject_gp(&svm->vcpu, 0);
2652 } else {
2653 trace_kvm_msr_write(ecx, data);
2654 skip_emulated_instruction(&svm->vcpu);
2655 }
2656 return 1;
2657 }
2658
2659 static int msr_interception(struct vcpu_svm *svm)
2660 {
2661 if (svm->vmcb->control.exit_info_1)
2662 return wrmsr_interception(svm);
2663 else
2664 return rdmsr_interception(svm);
2665 }
2666
2667 static int interrupt_window_interception(struct vcpu_svm *svm)
2668 {
2669 struct kvm_run *kvm_run = svm->vcpu.run;
2670
2671 svm_clear_vintr(svm);
2672 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2673 /*
2674 * If the user space waits to inject interrupts, exit as soon as
2675 * possible
2676 */
2677 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2678 kvm_run->request_interrupt_window &&
2679 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2680 ++svm->vcpu.stat.irq_window_exits;
2681 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2682 return 0;
2683 }
2684
2685 return 1;
2686 }
2687
2688 static int pause_interception(struct vcpu_svm *svm)
2689 {
2690 kvm_vcpu_on_spin(&(svm->vcpu));
2691 return 1;
2692 }
2693
2694 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2695 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2696 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2697 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2698 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2699 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2700 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2701 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2702 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2703 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2704 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2705 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2706 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2707 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2708 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2709 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2710 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2711 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2712 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2713 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2714 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2715 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2716 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2717 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2718 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2719 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2720 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2721 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2722 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2723 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2724 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2725 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2726 [SVM_EXIT_INTR] = intr_interception,
2727 [SVM_EXIT_NMI] = nmi_interception,
2728 [SVM_EXIT_SMI] = nop_on_interception,
2729 [SVM_EXIT_INIT] = nop_on_interception,
2730 [SVM_EXIT_VINTR] = interrupt_window_interception,
2731 [SVM_EXIT_CPUID] = cpuid_interception,
2732 [SVM_EXIT_IRET] = iret_interception,
2733 [SVM_EXIT_INVD] = emulate_on_interception,
2734 [SVM_EXIT_PAUSE] = pause_interception,
2735 [SVM_EXIT_HLT] = halt_interception,
2736 [SVM_EXIT_INVLPG] = invlpg_interception,
2737 [SVM_EXIT_INVLPGA] = invlpga_interception,
2738 [SVM_EXIT_IOIO] = io_interception,
2739 [SVM_EXIT_MSR] = msr_interception,
2740 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2741 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2742 [SVM_EXIT_VMRUN] = vmrun_interception,
2743 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2744 [SVM_EXIT_VMLOAD] = vmload_interception,
2745 [SVM_EXIT_VMSAVE] = vmsave_interception,
2746 [SVM_EXIT_STGI] = stgi_interception,
2747 [SVM_EXIT_CLGI] = clgi_interception,
2748 [SVM_EXIT_SKINIT] = skinit_interception,
2749 [SVM_EXIT_WBINVD] = emulate_on_interception,
2750 [SVM_EXIT_MONITOR] = invalid_op_interception,
2751 [SVM_EXIT_MWAIT] = invalid_op_interception,
2752 [SVM_EXIT_NPF] = pf_interception,
2753 };
2754
2755 void dump_vmcb(struct kvm_vcpu *vcpu)
2756 {
2757 struct vcpu_svm *svm = to_svm(vcpu);
2758 struct vmcb_control_area *control = &svm->vmcb->control;
2759 struct vmcb_save_area *save = &svm->vmcb->save;
2760
2761 pr_err("VMCB Control Area:\n");
2762 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2763 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2764 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2765 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2766 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2767 pr_err("intercepts: %016llx\n", control->intercept);
2768 pr_err("pause filter count: %d\n", control->pause_filter_count);
2769 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2770 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2771 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2772 pr_err("asid: %d\n", control->asid);
2773 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2774 pr_err("int_ctl: %08x\n", control->int_ctl);
2775 pr_err("int_vector: %08x\n", control->int_vector);
2776 pr_err("int_state: %08x\n", control->int_state);
2777 pr_err("exit_code: %08x\n", control->exit_code);
2778 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2779 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2780 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2781 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2782 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2783 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2784 pr_err("event_inj: %08x\n", control->event_inj);
2785 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2786 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2787 pr_err("next_rip: %016llx\n", control->next_rip);
2788 pr_err("VMCB State Save Area:\n");
2789 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2790 save->es.selector, save->es.attrib,
2791 save->es.limit, save->es.base);
2792 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2793 save->cs.selector, save->cs.attrib,
2794 save->cs.limit, save->cs.base);
2795 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2796 save->ss.selector, save->ss.attrib,
2797 save->ss.limit, save->ss.base);
2798 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2799 save->ds.selector, save->ds.attrib,
2800 save->ds.limit, save->ds.base);
2801 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2802 save->fs.selector, save->fs.attrib,
2803 save->fs.limit, save->fs.base);
2804 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2805 save->gs.selector, save->gs.attrib,
2806 save->gs.limit, save->gs.base);
2807 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2808 save->gdtr.selector, save->gdtr.attrib,
2809 save->gdtr.limit, save->gdtr.base);
2810 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2811 save->ldtr.selector, save->ldtr.attrib,
2812 save->ldtr.limit, save->ldtr.base);
2813 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2814 save->idtr.selector, save->idtr.attrib,
2815 save->idtr.limit, save->idtr.base);
2816 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2817 save->tr.selector, save->tr.attrib,
2818 save->tr.limit, save->tr.base);
2819 pr_err("cpl: %d efer: %016llx\n",
2820 save->cpl, save->efer);
2821 pr_err("cr0: %016llx cr2: %016llx\n",
2822 save->cr0, save->cr2);
2823 pr_err("cr3: %016llx cr4: %016llx\n",
2824 save->cr3, save->cr4);
2825 pr_err("dr6: %016llx dr7: %016llx\n",
2826 save->dr6, save->dr7);
2827 pr_err("rip: %016llx rflags: %016llx\n",
2828 save->rip, save->rflags);
2829 pr_err("rsp: %016llx rax: %016llx\n",
2830 save->rsp, save->rax);
2831 pr_err("star: %016llx lstar: %016llx\n",
2832 save->star, save->lstar);
2833 pr_err("cstar: %016llx sfmask: %016llx\n",
2834 save->cstar, save->sfmask);
2835 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2836 save->kernel_gs_base, save->sysenter_cs);
2837 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2838 save->sysenter_esp, save->sysenter_eip);
2839 pr_err("gpat: %016llx dbgctl: %016llx\n",
2840 save->g_pat, save->dbgctl);
2841 pr_err("br_from: %016llx br_to: %016llx\n",
2842 save->br_from, save->br_to);
2843 pr_err("excp_from: %016llx excp_to: %016llx\n",
2844 save->last_excp_from, save->last_excp_to);
2845
2846 }
2847
2848 static int handle_exit(struct kvm_vcpu *vcpu)
2849 {
2850 struct vcpu_svm *svm = to_svm(vcpu);
2851 struct kvm_run *kvm_run = vcpu->run;
2852 u32 exit_code = svm->vmcb->control.exit_code;
2853
2854 trace_kvm_exit(exit_code, vcpu);
2855
2856 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2857 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2858 if (npt_enabled)
2859 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2860
2861 if (unlikely(svm->nested.exit_required)) {
2862 nested_svm_vmexit(svm);
2863 svm->nested.exit_required = false;
2864
2865 return 1;
2866 }
2867
2868 if (is_nested(svm)) {
2869 int vmexit;
2870
2871 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2872 svm->vmcb->control.exit_info_1,
2873 svm->vmcb->control.exit_info_2,
2874 svm->vmcb->control.exit_int_info,
2875 svm->vmcb->control.exit_int_info_err);
2876
2877 vmexit = nested_svm_exit_special(svm);
2878
2879 if (vmexit == NESTED_EXIT_CONTINUE)
2880 vmexit = nested_svm_exit_handled(svm);
2881
2882 if (vmexit == NESTED_EXIT_DONE)
2883 return 1;
2884 }
2885
2886 svm_complete_interrupts(svm);
2887
2888 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2889 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2890 kvm_run->fail_entry.hardware_entry_failure_reason
2891 = svm->vmcb->control.exit_code;
2892 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2893 dump_vmcb(vcpu);
2894 return 0;
2895 }
2896
2897 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2898 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2899 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2900 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2901 "exit_code 0x%x\n",
2902 __func__, svm->vmcb->control.exit_int_info,
2903 exit_code);
2904
2905 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2906 || !svm_exit_handlers[exit_code]) {
2907 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2908 kvm_run->hw.hardware_exit_reason = exit_code;
2909 return 0;
2910 }
2911
2912 return svm_exit_handlers[exit_code](svm);
2913 }
2914
2915 static void reload_tss(struct kvm_vcpu *vcpu)
2916 {
2917 int cpu = raw_smp_processor_id();
2918
2919 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2920 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2921 load_TR_desc();
2922 }
2923
2924 static void pre_svm_run(struct vcpu_svm *svm)
2925 {
2926 int cpu = raw_smp_processor_id();
2927
2928 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2929
2930 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2931 if (svm->asid_generation != sd->asid_generation)
2932 new_asid(svm, sd);
2933 }
2934
2935 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2936 {
2937 struct vcpu_svm *svm = to_svm(vcpu);
2938
2939 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2940 vcpu->arch.hflags |= HF_NMI_MASK;
2941 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2942 ++vcpu->stat.nmi_injections;
2943 }
2944
2945 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2946 {
2947 struct vmcb_control_area *control;
2948
2949 control = &svm->vmcb->control;
2950 control->int_vector = irq;
2951 control->int_ctl &= ~V_INTR_PRIO_MASK;
2952 control->int_ctl |= V_IRQ_MASK |
2953 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2954 }
2955
2956 static void svm_set_irq(struct kvm_vcpu *vcpu)
2957 {
2958 struct vcpu_svm *svm = to_svm(vcpu);
2959
2960 BUG_ON(!(gif_set(svm)));
2961
2962 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2963 ++vcpu->stat.irq_injections;
2964
2965 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2966 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2967 }
2968
2969 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2970 {
2971 struct vcpu_svm *svm = to_svm(vcpu);
2972
2973 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2974 return;
2975
2976 if (irr == -1)
2977 return;
2978
2979 if (tpr >= irr)
2980 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2981 }
2982
2983 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2984 {
2985 struct vcpu_svm *svm = to_svm(vcpu);
2986 struct vmcb *vmcb = svm->vmcb;
2987 int ret;
2988 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2989 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2990 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2991
2992 return ret;
2993 }
2994
2995 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2996 {
2997 struct vcpu_svm *svm = to_svm(vcpu);
2998
2999 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3000 }
3001
3002 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3003 {
3004 struct vcpu_svm *svm = to_svm(vcpu);
3005
3006 if (masked) {
3007 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3008 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3009 } else {
3010 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3011 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3012 }
3013 }
3014
3015 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3016 {
3017 struct vcpu_svm *svm = to_svm(vcpu);
3018 struct vmcb *vmcb = svm->vmcb;
3019 int ret;
3020
3021 if (!gif_set(svm) ||
3022 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3023 return 0;
3024
3025 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3026
3027 if (is_nested(svm))
3028 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3029
3030 return ret;
3031 }
3032
3033 static void enable_irq_window(struct kvm_vcpu *vcpu)
3034 {
3035 struct vcpu_svm *svm = to_svm(vcpu);
3036
3037 /*
3038 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3039 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3040 * get that intercept, this function will be called again though and
3041 * we'll get the vintr intercept.
3042 */
3043 if (gif_set(svm) && nested_svm_intr(svm)) {
3044 svm_set_vintr(svm);
3045 svm_inject_irq(svm, 0x0);
3046 }
3047 }
3048
3049 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3050 {
3051 struct vcpu_svm *svm = to_svm(vcpu);
3052
3053 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3054 == HF_NMI_MASK)
3055 return; /* IRET will cause a vm exit */
3056
3057 /*
3058 * Something prevents NMI from been injected. Single step over possible
3059 * problem (IRET or exception injection or interrupt shadow)
3060 */
3061 svm->nmi_singlestep = true;
3062 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3063 update_db_intercept(vcpu);
3064 }
3065
3066 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3067 {
3068 return 0;
3069 }
3070
3071 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3072 {
3073 force_new_asid(vcpu);
3074 }
3075
3076 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3077 {
3078 }
3079
3080 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3081 {
3082 struct vcpu_svm *svm = to_svm(vcpu);
3083
3084 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3085 return;
3086
3087 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3088 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3089 kvm_set_cr8(vcpu, cr8);
3090 }
3091 }
3092
3093 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3094 {
3095 struct vcpu_svm *svm = to_svm(vcpu);
3096 u64 cr8;
3097
3098 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3099 return;
3100
3101 cr8 = kvm_get_cr8(vcpu);
3102 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3103 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3104 }
3105
3106 static void svm_complete_interrupts(struct vcpu_svm *svm)
3107 {
3108 u8 vector;
3109 int type;
3110 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3111 unsigned int3_injected = svm->int3_injected;
3112
3113 svm->int3_injected = 0;
3114
3115 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3116 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3117
3118 svm->vcpu.arch.nmi_injected = false;
3119 kvm_clear_exception_queue(&svm->vcpu);
3120 kvm_clear_interrupt_queue(&svm->vcpu);
3121
3122 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3123 return;
3124
3125 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3126 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3127
3128 switch (type) {
3129 case SVM_EXITINTINFO_TYPE_NMI:
3130 svm->vcpu.arch.nmi_injected = true;
3131 break;
3132 case SVM_EXITINTINFO_TYPE_EXEPT:
3133 /*
3134 * In case of software exceptions, do not reinject the vector,
3135 * but re-execute the instruction instead. Rewind RIP first
3136 * if we emulated INT3 before.
3137 */
3138 if (kvm_exception_is_soft(vector)) {
3139 if (vector == BP_VECTOR && int3_injected &&
3140 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3141 kvm_rip_write(&svm->vcpu,
3142 kvm_rip_read(&svm->vcpu) -
3143 int3_injected);
3144 break;
3145 }
3146 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3147 u32 err = svm->vmcb->control.exit_int_info_err;
3148 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3149
3150 } else
3151 kvm_requeue_exception(&svm->vcpu, vector);
3152 break;
3153 case SVM_EXITINTINFO_TYPE_INTR:
3154 kvm_queue_interrupt(&svm->vcpu, vector, false);
3155 break;
3156 default:
3157 break;
3158 }
3159 }
3160
3161 #ifdef CONFIG_X86_64
3162 #define R "r"
3163 #else
3164 #define R "e"
3165 #endif
3166
3167 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3168 {
3169 struct vcpu_svm *svm = to_svm(vcpu);
3170 u16 fs_selector;
3171 u16 gs_selector;
3172 u16 ldt_selector;
3173
3174 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3175 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3176 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3177
3178 /*
3179 * A vmexit emulation is required before the vcpu can be executed
3180 * again.
3181 */
3182 if (unlikely(svm->nested.exit_required))
3183 return;
3184
3185 pre_svm_run(svm);
3186
3187 sync_lapic_to_cr8(vcpu);
3188
3189 save_host_msrs(vcpu);
3190 savesegment(fs, fs_selector);
3191 savesegment(gs, gs_selector);
3192 ldt_selector = kvm_read_ldt();
3193 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3194 /* required for live migration with NPT */
3195 if (npt_enabled)
3196 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3197
3198 clgi();
3199
3200 local_irq_enable();
3201
3202 asm volatile (
3203 "push %%"R"bp; \n\t"
3204 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3205 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3206 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3207 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3208 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3209 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3210 #ifdef CONFIG_X86_64
3211 "mov %c[r8](%[svm]), %%r8 \n\t"
3212 "mov %c[r9](%[svm]), %%r9 \n\t"
3213 "mov %c[r10](%[svm]), %%r10 \n\t"
3214 "mov %c[r11](%[svm]), %%r11 \n\t"
3215 "mov %c[r12](%[svm]), %%r12 \n\t"
3216 "mov %c[r13](%[svm]), %%r13 \n\t"
3217 "mov %c[r14](%[svm]), %%r14 \n\t"
3218 "mov %c[r15](%[svm]), %%r15 \n\t"
3219 #endif
3220
3221 /* Enter guest mode */
3222 "push %%"R"ax \n\t"
3223 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3224 __ex(SVM_VMLOAD) "\n\t"
3225 __ex(SVM_VMRUN) "\n\t"
3226 __ex(SVM_VMSAVE) "\n\t"
3227 "pop %%"R"ax \n\t"
3228
3229 /* Save guest registers, load host registers */
3230 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3231 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3232 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3233 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3234 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3235 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3236 #ifdef CONFIG_X86_64
3237 "mov %%r8, %c[r8](%[svm]) \n\t"
3238 "mov %%r9, %c[r9](%[svm]) \n\t"
3239 "mov %%r10, %c[r10](%[svm]) \n\t"
3240 "mov %%r11, %c[r11](%[svm]) \n\t"
3241 "mov %%r12, %c[r12](%[svm]) \n\t"
3242 "mov %%r13, %c[r13](%[svm]) \n\t"
3243 "mov %%r14, %c[r14](%[svm]) \n\t"
3244 "mov %%r15, %c[r15](%[svm]) \n\t"
3245 #endif
3246 "pop %%"R"bp"
3247 :
3248 : [svm]"a"(svm),
3249 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3250 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3251 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3252 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3253 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3254 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3255 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3256 #ifdef CONFIG_X86_64
3257 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3258 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3259 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3260 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3261 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3262 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3263 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3264 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3265 #endif
3266 : "cc", "memory"
3267 , R"bx", R"cx", R"dx", R"si", R"di"
3268 #ifdef CONFIG_X86_64
3269 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3270 #endif
3271 );
3272
3273 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3274 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3275 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3276 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3277
3278 load_host_msrs(vcpu);
3279 kvm_load_ldt(ldt_selector);
3280 loadsegment(fs, fs_selector);
3281 #ifdef CONFIG_X86_64
3282 load_gs_index(gs_selector);
3283 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3284 #else
3285 loadsegment(gs, gs_selector);
3286 #endif
3287
3288 reload_tss(vcpu);
3289
3290 local_irq_disable();
3291
3292 stgi();
3293
3294 sync_cr8_to_lapic(vcpu);
3295
3296 svm->next_rip = 0;
3297
3298 if (npt_enabled) {
3299 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3300 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3301 }
3302
3303 /*
3304 * We need to handle MC intercepts here before the vcpu has a chance to
3305 * change the physical cpu
3306 */
3307 if (unlikely(svm->vmcb->control.exit_code ==
3308 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3309 svm_handle_mce(svm);
3310 }
3311
3312 #undef R
3313
3314 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3315 {
3316 struct vcpu_svm *svm = to_svm(vcpu);
3317
3318 if (npt_enabled) {
3319 svm->vmcb->control.nested_cr3 = root;
3320 force_new_asid(vcpu);
3321 return;
3322 }
3323
3324 svm->vmcb->save.cr3 = root;
3325 force_new_asid(vcpu);
3326 }
3327
3328 static int is_disabled(void)
3329 {
3330 u64 vm_cr;
3331
3332 rdmsrl(MSR_VM_CR, vm_cr);
3333 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3334 return 1;
3335
3336 return 0;
3337 }
3338
3339 static void
3340 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3341 {
3342 /*
3343 * Patch in the VMMCALL instruction:
3344 */
3345 hypercall[0] = 0x0f;
3346 hypercall[1] = 0x01;
3347 hypercall[2] = 0xd9;
3348 }
3349
3350 static void svm_check_processor_compat(void *rtn)
3351 {
3352 *(int *)rtn = 0;
3353 }
3354
3355 static bool svm_cpu_has_accelerated_tpr(void)
3356 {
3357 return false;
3358 }
3359
3360 static int get_npt_level(void)
3361 {
3362 #ifdef CONFIG_X86_64
3363 return PT64_ROOT_LEVEL;
3364 #else
3365 return PT32E_ROOT_LEVEL;
3366 #endif
3367 }
3368
3369 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3370 {
3371 return 0;
3372 }
3373
3374 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3375 {
3376 }
3377
3378 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3379 {
3380 switch (func) {
3381 case 0x00000001:
3382 /* Mask out xsave bit as long as it is not supported by SVM */
3383 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3384 break;
3385 case 0x80000001:
3386 if (nested)
3387 entry->ecx |= (1 << 2); /* Set SVM bit */
3388 break;
3389 case 0x8000000A:
3390 entry->eax = 1; /* SVM revision 1 */
3391 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3392 ASID emulation to nested SVM */
3393 entry->ecx = 0; /* Reserved */
3394 entry->edx = 0; /* Do not support any additional features */
3395
3396 break;
3397 }
3398 }
3399
3400 static const struct trace_print_flags svm_exit_reasons_str[] = {
3401 { SVM_EXIT_READ_CR0, "read_cr0" },
3402 { SVM_EXIT_READ_CR3, "read_cr3" },
3403 { SVM_EXIT_READ_CR4, "read_cr4" },
3404 { SVM_EXIT_READ_CR8, "read_cr8" },
3405 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3406 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3407 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3408 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3409 { SVM_EXIT_READ_DR0, "read_dr0" },
3410 { SVM_EXIT_READ_DR1, "read_dr1" },
3411 { SVM_EXIT_READ_DR2, "read_dr2" },
3412 { SVM_EXIT_READ_DR3, "read_dr3" },
3413 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3414 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3415 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3416 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3417 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3418 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3419 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3420 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3421 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3422 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3423 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3424 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3425 { SVM_EXIT_INTR, "interrupt" },
3426 { SVM_EXIT_NMI, "nmi" },
3427 { SVM_EXIT_SMI, "smi" },
3428 { SVM_EXIT_INIT, "init" },
3429 { SVM_EXIT_VINTR, "vintr" },
3430 { SVM_EXIT_CPUID, "cpuid" },
3431 { SVM_EXIT_INVD, "invd" },
3432 { SVM_EXIT_HLT, "hlt" },
3433 { SVM_EXIT_INVLPG, "invlpg" },
3434 { SVM_EXIT_INVLPGA, "invlpga" },
3435 { SVM_EXIT_IOIO, "io" },
3436 { SVM_EXIT_MSR, "msr" },
3437 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3438 { SVM_EXIT_SHUTDOWN, "shutdown" },
3439 { SVM_EXIT_VMRUN, "vmrun" },
3440 { SVM_EXIT_VMMCALL, "hypercall" },
3441 { SVM_EXIT_VMLOAD, "vmload" },
3442 { SVM_EXIT_VMSAVE, "vmsave" },
3443 { SVM_EXIT_STGI, "stgi" },
3444 { SVM_EXIT_CLGI, "clgi" },
3445 { SVM_EXIT_SKINIT, "skinit" },
3446 { SVM_EXIT_WBINVD, "wbinvd" },
3447 { SVM_EXIT_MONITOR, "monitor" },
3448 { SVM_EXIT_MWAIT, "mwait" },
3449 { SVM_EXIT_NPF, "npf" },
3450 { -1, NULL }
3451 };
3452
3453 static int svm_get_lpage_level(void)
3454 {
3455 return PT_PDPE_LEVEL;
3456 }
3457
3458 static bool svm_rdtscp_supported(void)
3459 {
3460 return false;
3461 }
3462
3463 static bool svm_has_wbinvd_exit(void)
3464 {
3465 return true;
3466 }
3467
3468 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3469 {
3470 struct vcpu_svm *svm = to_svm(vcpu);
3471
3472 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3473 if (is_nested(svm))
3474 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3475 update_cr0_intercept(svm);
3476 }
3477
3478 static struct kvm_x86_ops svm_x86_ops = {
3479 .cpu_has_kvm_support = has_svm,
3480 .disabled_by_bios = is_disabled,
3481 .hardware_setup = svm_hardware_setup,
3482 .hardware_unsetup = svm_hardware_unsetup,
3483 .check_processor_compatibility = svm_check_processor_compat,
3484 .hardware_enable = svm_hardware_enable,
3485 .hardware_disable = svm_hardware_disable,
3486 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3487
3488 .vcpu_create = svm_create_vcpu,
3489 .vcpu_free = svm_free_vcpu,
3490 .vcpu_reset = svm_vcpu_reset,
3491
3492 .prepare_guest_switch = svm_prepare_guest_switch,
3493 .vcpu_load = svm_vcpu_load,
3494 .vcpu_put = svm_vcpu_put,
3495
3496 .set_guest_debug = svm_guest_debug,
3497 .get_msr = svm_get_msr,
3498 .set_msr = svm_set_msr,
3499 .get_segment_base = svm_get_segment_base,
3500 .get_segment = svm_get_segment,
3501 .set_segment = svm_set_segment,
3502 .get_cpl = svm_get_cpl,
3503 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3504 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3505 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3506 .set_cr0 = svm_set_cr0,
3507 .set_cr3 = svm_set_cr3,
3508 .set_cr4 = svm_set_cr4,
3509 .set_efer = svm_set_efer,
3510 .get_idt = svm_get_idt,
3511 .set_idt = svm_set_idt,
3512 .get_gdt = svm_get_gdt,
3513 .set_gdt = svm_set_gdt,
3514 .set_dr7 = svm_set_dr7,
3515 .cache_reg = svm_cache_reg,
3516 .get_rflags = svm_get_rflags,
3517 .set_rflags = svm_set_rflags,
3518 .fpu_activate = svm_fpu_activate,
3519 .fpu_deactivate = svm_fpu_deactivate,
3520
3521 .tlb_flush = svm_flush_tlb,
3522
3523 .run = svm_vcpu_run,
3524 .handle_exit = handle_exit,
3525 .skip_emulated_instruction = skip_emulated_instruction,
3526 .set_interrupt_shadow = svm_set_interrupt_shadow,
3527 .get_interrupt_shadow = svm_get_interrupt_shadow,
3528 .patch_hypercall = svm_patch_hypercall,
3529 .set_irq = svm_set_irq,
3530 .set_nmi = svm_inject_nmi,
3531 .queue_exception = svm_queue_exception,
3532 .interrupt_allowed = svm_interrupt_allowed,
3533 .nmi_allowed = svm_nmi_allowed,
3534 .get_nmi_mask = svm_get_nmi_mask,
3535 .set_nmi_mask = svm_set_nmi_mask,
3536 .enable_nmi_window = enable_nmi_window,
3537 .enable_irq_window = enable_irq_window,
3538 .update_cr8_intercept = update_cr8_intercept,
3539
3540 .set_tss_addr = svm_set_tss_addr,
3541 .get_tdp_level = get_npt_level,
3542 .get_mt_mask = svm_get_mt_mask,
3543
3544 .exit_reasons_str = svm_exit_reasons_str,
3545 .get_lpage_level = svm_get_lpage_level,
3546
3547 .cpuid_update = svm_cpuid_update,
3548
3549 .rdtscp_supported = svm_rdtscp_supported,
3550
3551 .set_supported_cpuid = svm_set_supported_cpuid,
3552
3553 .has_wbinvd_exit = svm_has_wbinvd_exit,
3554 };
3555
3556 static int __init svm_init(void)
3557 {
3558 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3559 __alignof__(struct vcpu_svm), THIS_MODULE);
3560 }
3561
3562 static void __exit svm_exit(void)
3563 {
3564 kvm_exit();
3565 }
3566
3567 module_init(svm_init)
3568 module_exit(svm_exit)
Tomato firmware and modifications.