?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / sparc / math-emu / math_64.c
blobecc2fc51df0d3058d892ba322f51e8370b4e37e6
1 /*
2 * arch/sparc64/math-emu/math.c
3 *
4 * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 *
7 * Emulation routines originate from soft-fp package, which is part
8 * of glibc and has appropriate copyrights in it.
9 */
10
11 #include <linux/types.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/perf_event.h>
15
16 #include <asm/fpumacro.h>
17 #include <asm/ptrace.h>
18 #include <asm/uaccess.h>
19
20 #include "sfp-util_64.h"
21 #include <math-emu/soft-fp.h>
22 #include <math-emu/single.h>
23 #include <math-emu/double.h>
24 #include <math-emu/quad.h>
25
26 /* QUAD - ftt == 3 */
27 #define FMOVQ 0x003
28 #define FNEGQ 0x007
29 #define FABSQ 0x00b
30 #define FSQRTQ 0x02b
31 #define FADDQ 0x043
32 #define FSUBQ 0x047
33 #define FMULQ 0x04b
34 #define FDIVQ 0x04f
35 #define FDMULQ 0x06e
36 #define FQTOX 0x083
37 #define FXTOQ 0x08c
38 #define FQTOS 0x0c7
39 #define FQTOD 0x0cb
40 #define FITOQ 0x0cc
41 #define FSTOQ 0x0cd
42 #define FDTOQ 0x0ce
43 #define FQTOI 0x0d3
44 /* SUBNORMAL - ftt == 2 */
45 #define FSQRTS 0x029
46 #define FSQRTD 0x02a
47 #define FADDS 0x041
48 #define FADDD 0x042
49 #define FSUBS 0x045
50 #define FSUBD 0x046
51 #define FMULS 0x049
52 #define FMULD 0x04a
53 #define FDIVS 0x04d
54 #define FDIVD 0x04e
55 #define FSMULD 0x069
56 #define FSTOX 0x081
57 #define FDTOX 0x082
58 #define FDTOS 0x0c6
59 #define FSTOD 0x0c9
60 #define FSTOI 0x0d1
61 #define FDTOI 0x0d2
62 #define FXTOS 0x084 /* Only Ultra-III generates this. */
63 #define FXTOD 0x088 /* Only Ultra-III generates this. */
64 #define FITOD 0x0c8 /* Only Ultra-III generates this. */
65 /* FPOP2 */
66 #define FCMPQ 0x053
67 #define FCMPEQ 0x057
68 #define FMOVQ0 0x003
69 #define FMOVQ1 0x043
70 #define FMOVQ2 0x083
71 #define FMOVQ3 0x0c3
72 #define FMOVQI 0x103
73 #define FMOVQX 0x183
74 #define FMOVQZ 0x027
75 #define FMOVQLE 0x047
76 #define FMOVQLZ 0x067
77 #define FMOVQNZ 0x0a7
78 #define FMOVQGZ 0x0c7
79 #define FMOVQGE 0x0e7
80
81 #define FSR_TEM_SHIFT 23UL
82 #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
83 #define FSR_AEXC_SHIFT 5UL
84 #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
85 #define FSR_CEXC_SHIFT 0UL
86 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
87
88 /* All routines returning an exception to raise should detect
89 * such exceptions _before_ rounding to be consistent with
90 * the behavior of the hardware in the implemented cases
91 * (and thus with the recommendations in the V9 architecture
92 * manual).
93 *
94 * We return 0 if a SIGFPE should be sent, 1 otherwise.
95 */
96 static inline int record_exception(struct pt_regs *regs, int eflag)
97 {
98 u64 fsr = current_thread_info()->xfsr[0];
99 int would_trap;
100
101 /* Determine if this exception would have generated a trap. */
102 would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
103
104 /* If trapping, we only want to signal one bit. */
105 if(would_trap != 0) {
106 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
107 if((eflag & (eflag - 1)) != 0) {
108 if(eflag & FP_EX_INVALID)
109 eflag = FP_EX_INVALID;
110 else if(eflag & FP_EX_OVERFLOW)
111 eflag = FP_EX_OVERFLOW;
112 else if(eflag & FP_EX_UNDERFLOW)
113 eflag = FP_EX_UNDERFLOW;
114 else if(eflag & FP_EX_DIVZERO)
115 eflag = FP_EX_DIVZERO;
116 else if(eflag & FP_EX_INEXACT)
117 eflag = FP_EX_INEXACT;
118 }
119 }
120
121 /* Set CEXC, here is the rule:
122 *
123 * In general all FPU ops will set one and only one
124 * bit in the CEXC field, this is always the case
125 * when the IEEE exception trap is enabled in TEM.
126 */
127 fsr &= ~(FSR_CEXC_MASK);
128 fsr |= ((long)eflag << FSR_CEXC_SHIFT);
129
130 /* Set the AEXC field, rule is:
131 *
132 * If a trap would not be generated, the
133 * CEXC just generated is OR'd into the
134 * existing value of AEXC.
135 */
136 if(would_trap == 0)
137 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
138
139 /* If trapping, indicate fault trap type IEEE. */
140 if(would_trap != 0)
141 fsr |= (1UL << 14);
142
143 current_thread_info()->xfsr[0] = fsr;
144
145 /* If we will not trap, advance the program counter over
146 * the instruction being handled.
147 */
148 if(would_trap == 0) {
149 regs->tpc = regs->tnpc;
150 regs->tnpc += 4;
151 }
152
153 return (would_trap ? 0 : 1);
154 }
155
156 typedef union {
157 u32 s;
158 u64 d;
159 u64 q[2];
160 } *argp;
161
162 int do_mathemu(struct pt_regs *regs, struct fpustate *f)
163 {
164 unsigned long pc = regs->tpc;
165 unsigned long tstate = regs->tstate;
166 u32 insn = 0;
167 int type = 0;
168 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
169 whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
170 non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
171 #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
172 int freg;
173 static u64 zero[2] = { 0L, 0L };
174 int flags;
175 FP_DECL_EX;
176 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
177 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
178 FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
179 int IR;
180 long XR, xfsr;
181
182 if (tstate & TSTATE_PRIV)
183 die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
184 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
185 if (test_thread_flag(TIF_32BIT))
186 pc = (u32)pc;
187 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
188 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
189 switch ((insn >> 5) & 0x1ff) {
190 /* QUAD - ftt == 3 */
191 case FMOVQ:
192 case FNEGQ:
193 case FABSQ: TYPE(3,3,0,3,0,0,0); break;
194 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
195 case FADDQ:
196 case FSUBQ:
197 case FMULQ:
198 case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
199 case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
200 case FQTOX: TYPE(3,2,0,3,1,0,0); break;
201 case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
202 case FQTOS: TYPE(3,1,1,3,1,0,0); break;
203 case FQTOD: TYPE(3,2,1,3,1,0,0); break;
204 case FITOQ: TYPE(3,3,1,1,0,0,0); break;
205 case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
206 case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
207 case FQTOI: TYPE(3,1,0,3,1,0,0); break;
208
209 /* We can get either unimplemented or unfinished
210 * for these cases. Pre-Niagara systems generate
211 * unfinished fpop for SUBNORMAL cases, and Niagara
212 * always gives unimplemented fpop for fsqrt{s,d}.
213 */
214 case FSQRTS: {
215 unsigned long x = current_thread_info()->xfsr[0];
216
217 x = (x >> 14) & 0xf;
218 TYPE(x,1,1,1,1,0,0);
219 break;
220 }
221
222 case FSQRTD: {
223 unsigned long x = current_thread_info()->xfsr[0];
224
225 x = (x >> 14) & 0xf;
226 TYPE(x,2,1,2,1,0,0);
227 break;
228 }
229
230 /* SUBNORMAL - ftt == 2 */
231 case FADDD:
232 case FSUBD:
233 case FMULD:
234 case FDIVD: TYPE(2,2,1,2,1,2,1); break;
235 case FADDS:
236 case FSUBS:
237 case FMULS:
238 case FDIVS: TYPE(2,1,1,1,1,1,1); break;
239 case FSMULD: TYPE(2,2,1,1,1,1,1); break;
240 case FSTOX: TYPE(2,2,0,1,1,0,0); break;
241 case FDTOX: TYPE(2,2,0,2,1,0,0); break;
242 case FDTOS: TYPE(2,1,1,2,1,0,0); break;
243 case FSTOD: TYPE(2,2,1,1,1,0,0); break;
244 case FSTOI: TYPE(2,1,0,1,1,0,0); break;
245 case FDTOI: TYPE(2,1,0,2,1,0,0); break;
246
247 /* Only Ultra-III generates these */
248 case FXTOS: TYPE(2,1,1,2,0,0,0); break;
249 case FXTOD: TYPE(2,2,1,2,0,0,0); break;
250 case FITOD: TYPE(2,2,1,1,0,0,0); break;
251 }
252 }
253 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
254 IR = 2;
255 switch ((insn >> 5) & 0x1ff) {
256 case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
257 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
258 /* Now the conditional fmovq support */
259 case FMOVQ0:
260 case FMOVQ1:
261 case FMOVQ2:
262 case FMOVQ3:
263 /* fmovq %fccX, %fY, %fZ */
264 if (!((insn >> 11) & 3))
265 XR = current_thread_info()->xfsr[0] >> 10;
266 else
267 XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
268 XR &= 3;
269 IR = 0;
270 switch ((insn >> 14) & 0x7) {
271 /* case 0: IR = 0; break; */ /* Never */
272 case 1: if (XR) IR = 1; break; /* Not Equal */
273 case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
274 case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
275 case 4: if (XR == 1) IR = 1; break; /* Less */
276 case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
277 case 6: if (XR == 2) IR = 1; break; /* Greater */
278 case 7: if (XR == 3) IR = 1; break; /* Unordered */
279 }
280 if ((insn >> 14) & 8)
281 IR ^= 1;
282 break;
283 case FMOVQI:
284 case FMOVQX:
285 /* fmovq %[ix]cc, %fY, %fZ */
286 XR = regs->tstate >> 32;
287 if ((insn >> 5) & 0x80)
288 XR >>= 4;
289 XR &= 0xf;
290 IR = 0;
291 freg = ((XR >> 2) ^ XR) & 2;
292 switch ((insn >> 14) & 0x7) {
293 /* case 0: IR = 0; break; */ /* Never */
294 case 1: if (XR & 4) IR = 1; break; /* Equal */
295 case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
296 case 3: if (freg) IR = 1; break; /* Less */
297 case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
298 case 5: if (XR & 1) IR = 1; break; /* Carry Set */
299 case 6: if (XR & 8) IR = 1; break; /* Negative */
300 case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
301 }
302 if ((insn >> 14) & 8)
303 IR ^= 1;
304 break;
305 case FMOVQZ:
306 case FMOVQLE:
307 case FMOVQLZ:
308 case FMOVQNZ:
309 case FMOVQGZ:
310 case FMOVQGE:
311 freg = (insn >> 14) & 0x1f;
312 if (!freg)
313 XR = 0;
314 else if (freg < 16)
315 XR = regs->u_regs[freg];
316 else if (test_thread_flag(TIF_32BIT)) {
317 struct reg_window32 __user *win32;
318 flushw_user ();
319 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
320 get_user(XR, &win32->locals[freg - 16]);
321 } else {
322 struct reg_window __user *win;
323 flushw_user ();
324 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
325 get_user(XR, &win->locals[freg - 16]);
326 }
327 IR = 0;
328 switch ((insn >> 10) & 3) {
329 case 1: if (!XR) IR = 1; break; /* Register Zero */
330 case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
331 case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
332 }
333 if ((insn >> 10) & 4)
334 IR ^= 1;
335 break;
336 }
337 if (IR == 0) {
338 /* The fmov test was false. Do a nop instead */
339 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
340 regs->tpc = regs->tnpc;
341 regs->tnpc += 4;
342 return 1;
343 } else if (IR == 1) {
344 /* Change the instruction into plain fmovq */
345 insn = (insn & 0x3e00001f) | 0x81a00060;
346 TYPE(3,3,0,3,0,0,0);
347 }
348 }
349 }
350 if (type) {
351 argp rs1 = NULL, rs2 = NULL, rd = NULL;
352
353 freg = (current_thread_info()->xfsr[0] >> 14) & 0xf;
354 if (freg != (type >> 9))
355 goto err;
356 current_thread_info()->xfsr[0] &= ~0x1c000;
357 freg = ((insn >> 14) & 0x1f);
358 switch (type & 0x3) {
359 case 3: if (freg & 2) {
360 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
361 goto err;
362 }
363 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
364 case 1: rs1 = (argp)&f->regs[freg];
365 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
366 if (!(current_thread_info()->fpsaved[0] & flags))
367 rs1 = (argp)&zero;
368 break;
369 }
370 switch (type & 0x7) {
371 case 7: FP_UNPACK_QP (QA, rs1); break;
372 case 6: FP_UNPACK_DP (DA, rs1); break;
373 case 5: FP_UNPACK_SP (SA, rs1); break;
374 }
375 freg = (insn & 0x1f);
376 switch ((type >> 3) & 0x3) {
377 case 3: if (freg & 2) {
378 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
379 goto err;
380 }
381 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
382 case 1: rs2 = (argp)&f->regs[freg];
383 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
384 if (!(current_thread_info()->fpsaved[0] & flags))
385 rs2 = (argp)&zero;
386 break;
387 }
388 switch ((type >> 3) & 0x7) {
389 case 7: FP_UNPACK_QP (QB, rs2); break;
390 case 6: FP_UNPACK_DP (DB, rs2); break;
391 case 5: FP_UNPACK_SP (SB, rs2); break;
392 }
393 freg = ((insn >> 25) & 0x1f);
394 switch ((type >> 6) & 0x3) {
395 case 3: if (freg & 2) {
396 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
397 goto err;
398 }
399 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
400 case 1: rd = (argp)&f->regs[freg];
401 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
402 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
403 current_thread_info()->fpsaved[0] = FPRS_FEF;
404 current_thread_info()->gsr[0] = 0;
405 }
406 if (!(current_thread_info()->fpsaved[0] & flags)) {
407 if (freg < 32)
408 memset(f->regs, 0, 32*sizeof(u32));
409 else
410 memset(f->regs+32, 0, 32*sizeof(u32));
411 }
412 current_thread_info()->fpsaved[0] |= flags;
413 break;
414 }
415 switch ((insn >> 5) & 0x1ff) {
416 /* + */
417 case FADDS: FP_ADD_S (SR, SA, SB); break;
418 case FADDD: FP_ADD_D (DR, DA, DB); break;
419 case FADDQ: FP_ADD_Q (QR, QA, QB); break;
420 /* - */
421 case FSUBS: FP_SUB_S (SR, SA, SB); break;
422 case FSUBD: FP_SUB_D (DR, DA, DB); break;
423 case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
424 /* * */
425 case FMULS: FP_MUL_S (SR, SA, SB); break;
426 case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
427 FP_CONV (D, S, 1, 1, DB, SB);
428 case FMULD: FP_MUL_D (DR, DA, DB); break;
429 case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
430 FP_CONV (Q, D, 2, 1, QB, DB);
431 case FMULQ: FP_MUL_Q (QR, QA, QB); break;
432 /* / */
433 case FDIVS: FP_DIV_S (SR, SA, SB); break;
434 case FDIVD: FP_DIV_D (DR, DA, DB); break;
435 case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
436 /* sqrt */
437 case FSQRTS: FP_SQRT_S (SR, SB); break;
438 case FSQRTD: FP_SQRT_D (DR, DB); break;
439 case FSQRTQ: FP_SQRT_Q (QR, QB); break;
440 /* mov */
441 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
442 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
443 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
444 /* float to int */
445 case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
446 case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
447 case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
448 case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
449 case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
450 case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
451 /* int to float */
452 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
453 case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
454 /* Only Ultra-III generates these */
455 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
456 case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
457 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
458 /* float to float */
459 case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
460 case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
461 case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
462 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
463 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
464 case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
465 /* comparison */
466 case FCMPQ:
467 case FCMPEQ:
468 FP_CMP_Q(XR, QB, QA, 3);
469 if (XR == 3 &&
470 (((insn >> 5) & 0x1ff) == FCMPEQ ||
471 FP_ISSIGNAN_Q(QA) ||
472 FP_ISSIGNAN_Q(QB)))
473 FP_SET_EXCEPTION (FP_EX_INVALID);
474 }
475 if (!FP_INHIBIT_RESULTS) {
476 switch ((type >> 6) & 0x7) {
477 case 0: xfsr = current_thread_info()->xfsr[0];
478 if (XR == -1) XR = 2;
479 switch (freg & 3) {
480 /* fcc0, 1, 2, 3 */
481 case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
482 case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
483 case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
484 case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
485 }
486 current_thread_info()->xfsr[0] = xfsr;
487 break;
488 case 1: rd->s = IR; break;
489 case 2: rd->d = XR; break;
490 case 5: FP_PACK_SP (rd, SR); break;
491 case 6: FP_PACK_DP (rd, DR); break;
492 case 7: FP_PACK_QP (rd, QR); break;
493 }
494 }
495
496 if(_fex != 0)
497 return record_exception(regs, _fex);
498
499 /* Success and no exceptions detected. */
500 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
501 regs->tpc = regs->tnpc;
502 regs->tnpc += 4;
503 return 1;
504 }
505 err: return 0;
506 }
Tomato firmware and modifications.