release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sparc/include/asm/pgtable_64.h

   1 /*
   2  * pgtable.h: SpitFire page table operations.
   3  *
   4  * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #ifndef _SPARC64_PGTABLE_H
   9 #define _SPARC64_PGTABLE_H
  10
  11 /* This file contains the functions and defines necessary to modify and use
  12  * the SpitFire page tables.
  13  */
  14
  15 #include <asm-generic/pgtable-nopud.h>
  16
  17 #include <linux/compiler.h>
  18 #include <linux/const.h>
  19 #include <asm/types.h>
  20 #include <asm/spitfire.h>
  21 #include <asm/asi.h>
  22 #include <asm/system.h>
  23 #include <asm/page.h>
  24 #include <asm/processor.h>
  25
  26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
  27  * The page copy blockops can use 0x6000000 to 0x8000000.
  28  * The TSB is mapped in the 0x8000000 to 0xa000000 range.
  29  * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
  30  * The vmalloc area spans 0x100000000 to 0x200000000.
  31  * Since modules need to be in the lowest 32-bits of the address space,
  32  * we place them right before the OBP area from 0x10000000 to 0xf0000000.
  33  * There is a single static kernel PMD which maps from 0x0 to address
  34  * 0x400000000.
  35  */
  36 #define TLBTEMP_BASE            _AC(0x0000000006000000,UL)
  37 #define TSBMAP_BASE             _AC(0x0000000008000000,UL)
  38 #define MODULES_VADDR           _AC(0x0000000010000000,UL)
  39 #define MODULES_LEN             _AC(0x00000000e0000000,UL)
  40 #define MODULES_END             _AC(0x00000000f0000000,UL)
  41 #define LOW_OBP_ADDRESS         _AC(0x00000000f0000000,UL)
  42 #define HI_OBP_ADDRESS          _AC(0x0000000100000000,UL)
  43 #define VMALLOC_START           _AC(0x0000000100000000,UL)
  44 #define VMALLOC_END             _AC(0x0000010000000000,UL)
  45 #define VMEMMAP_BASE            _AC(0x0000010000000000,UL)
  46
  47 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
  48
  49 /*
  50  * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
  51  * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
  52  * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
  53  * table is a single page long). The next higher PMD_BITS determine pmd#
  54  * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
  55  * since the pmd entries are 4 bytes, and each pmd page is a single page
  56  * long). Finally, the higher few bits determine pgde#.
  57  */
  58
  59 /* PMD_SHIFT determines the size of the area a second-level page
  60  * table can map
  61  */
  62 #define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-3))
  63 #define PMD_SIZE        (_AC(1,UL) << PMD_SHIFT)
  64 #define PMD_MASK        (~(PMD_SIZE-1))
  65 #define PMD_BITS        (PAGE_SHIFT - 2)
  66
  67 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  68 #define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
  69 #define PGDIR_SIZE      (_AC(1,UL) << PGDIR_SHIFT)
  70 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  71 #define PGDIR_BITS      (PAGE_SHIFT - 2)
  72
  73 #ifndef __ASSEMBLY__
  74
  75 #include <linux/sched.h>
  76
  77 /* Entries per page directory level. */
  78 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-3))
  79 #define PTRS_PER_PMD    (1UL << PMD_BITS)
  80 #define PTRS_PER_PGD    (1UL << PGDIR_BITS)
  81
  82 /* Kernel has a separate 44bit address space. */
  83 #define FIRST_USER_ADDRESS      0
  84
  85 #define pte_ERROR(e)    __builtin_trap()
  86 #define pmd_ERROR(e)    __builtin_trap()
  87 #define pgd_ERROR(e)    __builtin_trap()
  88
  89 #endif /* !(__ASSEMBLY__) */
  90
  91 /* PTE bits which are the same in SUN4U and SUN4V format.  */
  92 #define _PAGE_VALID       _AC(0x8000000000000000,UL) /* Valid TTE            */
  93 #define _PAGE_R           _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
  94
  95 /* SUN4U pte bits... */
  96 #define _PAGE_SZ4MB_4U    _AC(0x6000000000000000,UL) /* 4MB Page             */
  97 #define _PAGE_SZ512K_4U   _AC(0x4000000000000000,UL) /* 512K Page            */
  98 #define _PAGE_SZ64K_4U    _AC(0x2000000000000000,UL) /* 64K Page             */
  99 #define _PAGE_SZ8K_4U     _AC(0x0000000000000000,UL) /* 8K Page              */
 100 #define _PAGE_NFO_4U      _AC(0x1000000000000000,UL) /* No Fault Only        */
 101 #define _PAGE_IE_4U       _AC(0x0800000000000000,UL) /* Invert Endianness    */
 102 #define _PAGE_SOFT2_4U    _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
 103 #define _PAGE_RES1_4U     _AC(0x0002000000000000,UL) /* Reserved             */
 104 #define _PAGE_SZ32MB_4U   _AC(0x0001000000000000,UL) /* (Panther) 32MB page  */
 105 #define _PAGE_SZ256MB_4U  _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
 106 #define _PAGE_SZALL_4U    _AC(0x6001000000000000,UL) /* All pgsz bits        */
 107 #define _PAGE_SN_4U       _AC(0x0000800000000000,UL) /* (Cheetah) Snoop      */
 108 #define _PAGE_RES2_4U     _AC(0x0000780000000000,UL) /* Reserved             */
 109 #define _PAGE_PADDR_4U    _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13]  */
 110 #define _PAGE_SOFT_4U     _AC(0x0000000000001F80,UL) /* Software bits:       */
 111 #define _PAGE_EXEC_4U     _AC(0x0000000000001000,UL) /* Executable SW bit    */
 112 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty)     */
 113 #define _PAGE_FILE_4U     _AC(0x0000000000000800,UL) /* Pagecache page       */
 114 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd)     */
 115 #define _PAGE_READ_4U     _AC(0x0000000000000200,UL) /* Readable SW Bit      */
 116 #define _PAGE_WRITE_4U    _AC(0x0000000000000100,UL) /* Writable SW Bit      */
 117 #define _PAGE_PRESENT_4U  _AC(0x0000000000000080,UL) /* Present              */
 118 #define _PAGE_L_4U        _AC(0x0000000000000040,UL) /* Locked TTE           */
 119 #define _PAGE_CP_4U       _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
 120 #define _PAGE_CV_4U       _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
 121 #define _PAGE_E_4U        _AC(0x0000000000000008,UL) /* side-Effect          */
 122 #define _PAGE_P_4U        _AC(0x0000000000000004,UL) /* Privileged Page      */
 123 #define _PAGE_W_4U        _AC(0x0000000000000002,UL) /* Writable             */
 124
 125 /* SUN4V pte bits... */
 126 #define _PAGE_NFO_4V      _AC(0x4000000000000000,UL) /* No Fault Only        */
 127 #define _PAGE_SOFT2_4V    _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
 128 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty)     */
 129 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd)     */
 130 #define _PAGE_READ_4V     _AC(0x0800000000000000,UL) /* Readable SW Bit      */
 131 #define _PAGE_WRITE_4V    _AC(0x0400000000000000,UL) /* Writable SW Bit      */
 132 #define _PAGE_PADDR_4V    _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13]         */
 133 #define _PAGE_IE_4V       _AC(0x0000000000001000,UL) /* Invert Endianness    */
 134 #define _PAGE_E_4V        _AC(0x0000000000000800,UL) /* side-Effect          */
 135 #define _PAGE_CP_4V       _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
 136 #define _PAGE_CV_4V       _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
 137 #define _PAGE_P_4V        _AC(0x0000000000000100,UL) /* Privileged Page      */
 138 #define _PAGE_EXEC_4V     _AC(0x0000000000000080,UL) /* Executable Page      */
 139 #define _PAGE_W_4V        _AC(0x0000000000000040,UL) /* Writable             */
 140 #define _PAGE_SOFT_4V     _AC(0x0000000000000030,UL) /* Software bits        */
 141 #define _PAGE_FILE_4V     _AC(0x0000000000000020,UL) /* Pagecache page       */
 142 #define _PAGE_PRESENT_4V  _AC(0x0000000000000010,UL) /* Present              */
 143 #define _PAGE_RESV_4V     _AC(0x0000000000000008,UL) /* Reserved             */
 144 #define _PAGE_SZ16GB_4V   _AC(0x0000000000000007,UL) /* 16GB Page            */
 145 #define _PAGE_SZ2GB_4V    _AC(0x0000000000000006,UL) /* 2GB Page             */
 146 #define _PAGE_SZ256MB_4V  _AC(0x0000000000000005,UL) /* 256MB Page           */
 147 #define _PAGE_SZ32MB_4V   _AC(0x0000000000000004,UL) /* 32MB Page            */
 148 #define _PAGE_SZ4MB_4V    _AC(0x0000000000000003,UL) /* 4MB Page             */
 149 #define _PAGE_SZ512K_4V   _AC(0x0000000000000002,UL) /* 512K Page            */
 150 #define _PAGE_SZ64K_4V    _AC(0x0000000000000001,UL) /* 64K Page             */
 151 #define _PAGE_SZ8K_4V     _AC(0x0000000000000000,UL) /* 8K Page              */
 152 #define _PAGE_SZALL_4V    _AC(0x0000000000000007,UL) /* All pgsz bits        */
 153
 154 #if PAGE_SHIFT == 13
 155 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
 156 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
 157 #elif PAGE_SHIFT == 16
 158 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
 159 #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
 160 #else
 161 #error Wrong PAGE_SHIFT specified
 162 #endif
 163
 164 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
 165 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
 166 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
 167 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
 168 #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
 169 #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
 170 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 171 #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
 172 #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
 173 #endif
 174
 175 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
 176 #define __P000  __pgprot(0)
 177 #define __P001  __pgprot(0)
 178 #define __P010  __pgprot(0)
 179 #define __P011  __pgprot(0)
 180 #define __P100  __pgprot(0)
 181 #define __P101  __pgprot(0)
 182 #define __P110  __pgprot(0)
 183 #define __P111  __pgprot(0)
 184
 185 #define __S000  __pgprot(0)
 186 #define __S001  __pgprot(0)
 187 #define __S010  __pgprot(0)
 188 #define __S011  __pgprot(0)
 189 #define __S100  __pgprot(0)
 190 #define __S101  __pgprot(0)
 191 #define __S110  __pgprot(0)
 192 #define __S111  __pgprot(0)
 193
 194 #ifndef __ASSEMBLY__
 195
 196 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
 197
 198 extern unsigned long pte_sz_bits(unsigned long size);
 199
 200 extern pgprot_t PAGE_KERNEL;
 201 extern pgprot_t PAGE_KERNEL_LOCKED;
 202 extern pgprot_t PAGE_COPY;
 203 extern pgprot_t PAGE_SHARED;
 204
 205 extern unsigned long _PAGE_IE;
 206 extern unsigned long _PAGE_E;
 207 extern unsigned long _PAGE_CACHE;
 208
 209 extern unsigned long pg_iobits;
 210 extern unsigned long _PAGE_ALL_SZ_BITS;
 211 extern unsigned long _PAGE_SZBITS;
 212
 213 extern struct page *mem_map_zero;
 214 #define ZERO_PAGE(vaddr)        (mem_map_zero)
 215
 216 /* PFNs are real physical page numbers.  However, mem_map only begins to record
 217  * per-page information starting at pfn_base.  This is to handle systems where
 218  * the first physical page in the machine is at some huge physical address,
 219  * such as 4GB.   This is common on a partitioned E10000, for example.
 220  */
 221 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 222 {
 223         unsigned long paddr = pfn << PAGE_SHIFT;
 224         unsigned long sz_bits;
 225
 226         sz_bits = 0UL;
 227         if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
 228                 __asm__ __volatile__(
 229                 "\n661: sethi           %%uhi(%1), %0\n"
 230                 "       sllx            %0, 32, %0\n"
 231                 "       .section        .sun4v_2insn_patch, \"ax\"\n"
 232                 "       .word           661b\n"
 233                 "       mov             %2, %0\n"
 234                 "       nop\n"
 235                 "       .previous\n"
 236                 : "=r" (sz_bits)
 237                 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
 238         }
 239         return __pte(paddr | sz_bits | pgprot_val(prot));
 240 }
 241 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 242
 243 /* This one can be done with two shifts.  */
 244 static inline unsigned long pte_pfn(pte_t pte)
 245 {
 246         unsigned long ret;
 247
 248         __asm__ __volatile__(
 249         "\n661: sllx            %1, %2, %0\n"
 250         "       srlx            %0, %3, %0\n"
 251         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 252         "       .word           661b\n"
 253         "       sllx            %1, %4, %0\n"
 254         "       srlx            %0, %5, %0\n"
 255         "       .previous\n"
 256         : "=r" (ret)
 257         : "r" (pte_val(pte)),
 258           "i" (21), "i" (21 + PAGE_SHIFT),
 259           "i" (8), "i" (8 + PAGE_SHIFT));
 260
 261         return ret;
 262 }
 263 #define pte_page(x) pfn_to_page(pte_pfn(x))
 264
 265 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
 266 {
 267         unsigned long mask, tmp;
 268
 269         /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
 270          * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
 271          *
 272          * Even if we use negation tricks the result is still a 6
 273          * instruction sequence, so don't try to play fancy and just
 274          * do the most straightforward implementation.
 275          *
 276          * Note: We encode this into 3 sun4v 2-insn patch sequences.
 277          */
 278
 279         __asm__ __volatile__(
 280         "\n661: sethi           %%uhi(%2), %1\n"
 281         "       sethi           %%hi(%2), %0\n"
 282         "\n662: or              %1, %%ulo(%2), %1\n"
 283         "       or              %0, %%lo(%2), %0\n"
 284         "\n663: sllx            %1, 32, %1\n"
 285         "       or              %0, %1, %0\n"
 286         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 287         "       .word           661b\n"
 288         "       sethi           %%uhi(%3), %1\n"
 289         "       sethi           %%hi(%3), %0\n"
 290         "       .word           662b\n"
 291         "       or              %1, %%ulo(%3), %1\n"
 292         "       or              %0, %%lo(%3), %0\n"
 293         "       .word           663b\n"
 294         "       sllx            %1, 32, %1\n"
 295         "       or              %0, %1, %0\n"
 296         "       .previous\n"
 297         : "=r" (mask), "=r" (tmp)
 298         : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
 299                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
 300                _PAGE_SZBITS_4U),
 301           "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
 302                _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
 303                _PAGE_SZBITS_4V));
 304
 305         return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
 306 }
 307
 308 static inline pte_t pgoff_to_pte(unsigned long off)
 309 {
 310         off <<= PAGE_SHIFT;
 311
 312         __asm__ __volatile__(
 313         "\n661: or              %0, %2, %0\n"
 314         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 315         "       .word           661b\n"
 316         "       or              %0, %3, %0\n"
 317         "       .previous\n"
 318         : "=r" (off)
 319         : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 320
 321         return __pte(off);
 322 }
 323
 324 static inline pgprot_t pgprot_noncached(pgprot_t prot)
 325 {
 326         unsigned long val = pgprot_val(prot);
 327
 328         __asm__ __volatile__(
 329         "\n661: andn            %0, %2, %0\n"
 330         "       or              %0, %3, %0\n"
 331         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 332         "       .word           661b\n"
 333         "       andn            %0, %4, %0\n"
 334         "       or              %0, %5, %0\n"
 335         "       .previous\n"
 336         : "=r" (val)
 337         : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
 338                      "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
 339
 340         return __pgprot(val);
 341 }
 342 /* Various pieces of code check for platform support by ifdef testing
 343  * on "pgprot_noncached".  That's broken and should be fixed, but for
 344  * now...
 345  */
 346 #define pgprot_noncached pgprot_noncached
 347
 348 #ifdef CONFIG_HUGETLB_PAGE
 349 static inline pte_t pte_mkhuge(pte_t pte)
 350 {
 351         unsigned long mask;
 352
 353         __asm__ __volatile__(
 354         "\n661: sethi           %%uhi(%1), %0\n"
 355         "       sllx            %0, 32, %0\n"
 356         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 357         "       .word           661b\n"
 358         "       mov             %2, %0\n"
 359         "       nop\n"
 360         "       .previous\n"
 361         : "=r" (mask)
 362         : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
 363
 364         return __pte(pte_val(pte) | mask);
 365 }
 366 #endif
 367
 368 static inline pte_t pte_mkdirty(pte_t pte)
 369 {
 370         unsigned long val = pte_val(pte), tmp;
 371
 372         __asm__ __volatile__(
 373         "\n661: or              %0, %3, %0\n"
 374         "       nop\n"
 375         "\n662: nop\n"
 376         "       nop\n"
 377         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 378         "       .word           661b\n"
 379         "       sethi           %%uhi(%4), %1\n"
 380         "       sllx            %1, 32, %1\n"
 381         "       .word           662b\n"
 382         "       or              %1, %%lo(%4), %1\n"
 383         "       or              %0, %1, %0\n"
 384         "       .previous\n"
 385         : "=r" (val), "=r" (tmp)
 386         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 387           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 388
 389         return __pte(val);
 390 }
 391
 392 static inline pte_t pte_mkclean(pte_t pte)
 393 {
 394         unsigned long val = pte_val(pte), tmp;
 395
 396         __asm__ __volatile__(
 397         "\n661: andn            %0, %3, %0\n"
 398         "       nop\n"
 399         "\n662: nop\n"
 400         "       nop\n"
 401         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 402         "       .word           661b\n"
 403         "       sethi           %%uhi(%4), %1\n"
 404         "       sllx            %1, 32, %1\n"
 405         "       .word           662b\n"
 406         "       or              %1, %%lo(%4), %1\n"
 407         "       andn            %0, %1, %0\n"
 408         "       .previous\n"
 409         : "=r" (val), "=r" (tmp)
 410         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 411           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 412
 413         return __pte(val);
 414 }
 415
 416 static inline pte_t pte_mkwrite(pte_t pte)
 417 {
 418         unsigned long val = pte_val(pte), mask;
 419
 420         __asm__ __volatile__(
 421         "\n661: mov             %1, %0\n"
 422         "       nop\n"
 423         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 424         "       .word           661b\n"
 425         "       sethi           %%uhi(%2), %0\n"
 426         "       sllx            %0, 32, %0\n"
 427         "       .previous\n"
 428         : "=r" (mask)
 429         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 430
 431         return __pte(val | mask);
 432 }
 433
 434 static inline pte_t pte_wrprotect(pte_t pte)
 435 {
 436         unsigned long val = pte_val(pte), tmp;
 437
 438         __asm__ __volatile__(
 439         "\n661: andn            %0, %3, %0\n"
 440         "       nop\n"
 441         "\n662: nop\n"
 442         "       nop\n"
 443         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 444         "       .word           661b\n"
 445         "       sethi           %%uhi(%4), %1\n"
 446         "       sllx            %1, 32, %1\n"
 447         "       .word           662b\n"
 448         "       or              %1, %%lo(%4), %1\n"
 449         "       andn            %0, %1, %0\n"
 450         "       .previous\n"
 451         : "=r" (val), "=r" (tmp)
 452         : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
 453           "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
 454
 455         return __pte(val);
 456 }
 457
 458 static inline pte_t pte_mkold(pte_t pte)
 459 {
 460         unsigned long mask;
 461
 462         __asm__ __volatile__(
 463         "\n661: mov             %1, %0\n"
 464         "       nop\n"
 465         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 466         "       .word           661b\n"
 467         "       sethi           %%uhi(%2), %0\n"
 468         "       sllx            %0, 32, %0\n"
 469         "       .previous\n"
 470         : "=r" (mask)
 471         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 472
 473         mask |= _PAGE_R;
 474
 475         return __pte(pte_val(pte) & ~mask);
 476 }
 477
 478 static inline pte_t pte_mkyoung(pte_t pte)
 479 {
 480         unsigned long mask;
 481
 482         __asm__ __volatile__(
 483         "\n661: mov             %1, %0\n"
 484         "       nop\n"
 485         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 486         "       .word           661b\n"
 487         "       sethi           %%uhi(%2), %0\n"
 488         "       sllx            %0, 32, %0\n"
 489         "       .previous\n"
 490         : "=r" (mask)
 491         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 492
 493         mask |= _PAGE_R;
 494
 495         return __pte(pte_val(pte) | mask);
 496 }
 497
 498 static inline pte_t pte_mkspecial(pte_t pte)
 499 {
 500         return pte;
 501 }
 502
 503 static inline unsigned long pte_young(pte_t pte)
 504 {
 505         unsigned long mask;
 506
 507         __asm__ __volatile__(
 508         "\n661: mov             %1, %0\n"
 509         "       nop\n"
 510         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 511         "       .word           661b\n"
 512         "       sethi           %%uhi(%2), %0\n"
 513         "       sllx            %0, 32, %0\n"
 514         "       .previous\n"
 515         : "=r" (mask)
 516         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 517
 518         return (pte_val(pte) & mask);
 519 }
 520
 521 static inline unsigned long pte_dirty(pte_t pte)
 522 {
 523         unsigned long mask;
 524
 525         __asm__ __volatile__(
 526         "\n661: mov             %1, %0\n"
 527         "       nop\n"
 528         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 529         "       .word           661b\n"
 530         "       sethi           %%uhi(%2), %0\n"
 531         "       sllx            %0, 32, %0\n"
 532         "       .previous\n"
 533         : "=r" (mask)
 534         : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
 535
 536         return (pte_val(pte) & mask);
 537 }
 538
 539 static inline unsigned long pte_write(pte_t pte)
 540 {
 541         unsigned long mask;
 542
 543         __asm__ __volatile__(
 544         "\n661: mov             %1, %0\n"
 545         "       nop\n"
 546         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 547         "       .word           661b\n"
 548         "       sethi           %%uhi(%2), %0\n"
 549         "       sllx            %0, 32, %0\n"
 550         "       .previous\n"
 551         : "=r" (mask)
 552         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 553
 554         return (pte_val(pte) & mask);
 555 }
 556
 557 static inline unsigned long pte_exec(pte_t pte)
 558 {
 559         unsigned long mask;
 560
 561         __asm__ __volatile__(
 562         "\n661: sethi           %%hi(%1), %0\n"
 563         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 564         "       .word           661b\n"
 565         "       mov             %2, %0\n"
 566         "       .previous\n"
 567         : "=r" (mask)
 568         : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
 569
 570         return (pte_val(pte) & mask);
 571 }
 572
 573 static inline unsigned long pte_file(pte_t pte)
 574 {
 575         unsigned long val = pte_val(pte);
 576
 577         __asm__ __volatile__(
 578         "\n661: and             %0, %2, %0\n"
 579         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 580         "       .word           661b\n"
 581         "       and             %0, %3, %0\n"
 582         "       .previous\n"
 583         : "=r" (val)
 584         : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 585
 586         return val;
 587 }
 588
 589 static inline unsigned long pte_present(pte_t pte)
 590 {
 591         unsigned long val = pte_val(pte);
 592
 593         __asm__ __volatile__(
 594         "\n661: and             %0, %2, %0\n"
 595         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 596         "       .word           661b\n"
 597         "       and             %0, %3, %0\n"
 598         "       .previous\n"
 599         : "=r" (val)
 600         : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
 601
 602         return val;
 603 }
 604
 605 static inline int pte_special(pte_t pte)
 606 {
 607         return 0;
 608 }
 609
 610 #define pmd_set(pmdp, ptep)     \
 611         (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
 612 #define pud_set(pudp, pmdp)     \
 613         (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
 614 #define __pmd_page(pmd)         \
 615         ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
 616 #define pmd_page(pmd)                   virt_to_page((void *)__pmd_page(pmd))
 617 #define pud_page_vaddr(pud)             \
 618         ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
 619 #define pud_page(pud)                   virt_to_page((void *)pud_page_vaddr(pud))
 620 #define pmd_none(pmd)                   (!pmd_val(pmd))
 621 #define pmd_bad(pmd)                    (0)
 622 #define pmd_present(pmd)                (pmd_val(pmd) != 0U)
 623 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0U)
 624 #define pud_none(pud)                   (!pud_val(pud))
 625 #define pud_bad(pud)                    (0)
 626 #define pud_present(pud)                (pud_val(pud) != 0U)
 627 #define pud_clear(pudp)                 (pud_val(*(pudp)) = 0U)
 628
 629 /* Same in both SUN4V and SUN4U.  */
 630 #define pte_none(pte)                   (!pte_val(pte))
 631
 632 /* to find an entry in a page-table-directory. */
 633 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 634 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 635
 636 /* to find an entry in a kernel page-table-directory */
 637 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 638
 639 /* Find an entry in the second-level page table.. */
 640 #define pmd_offset(pudp, address)       \
 641         ((pmd_t *) pud_page_vaddr(*(pudp)) + \
 642          (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
 643
 644 /* Find an entry in the third-level page table.. */
 645 #define pte_index(dir, address) \
 646         ((pte_t *) __pmd_page(*(dir)) + \
 647          ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 648 #define pte_offset_kernel               pte_index
 649 #define pte_offset_map                  pte_index
 650 #define pte_offset_map_nested           pte_index
 651 #define pte_unmap(pte)                  do { } while (0)
 652 #define pte_unmap_nested(pte)           do { } while (0)
 653
 654 /* Actual page table PTE updates.  */
 655 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
 656
 657 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
 658 {
 659         pte_t orig = *ptep;
 660
 661         *ptep = pte;
 662
 663         /* It is more efficient to let flush_tlb_kernel_range()
 664          * handle init_mm tlb flushes.
 665          *
 666          * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
 667          *             and SUN4V pte layout, so this inline test is fine.
 668          */
 669         if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
 670                 tlb_batch_add(mm, addr, ptep, orig);
 671 }
 672
 673 #define pte_clear(mm,addr,ptep)         \
 674         set_pte_at((mm), (addr), (ptep), __pte(0UL))
 675
 676 #ifdef DCACHE_ALIASING_POSSIBLE
 677 #define __HAVE_ARCH_MOVE_PTE
 678 #define move_pte(pte, prot, old_addr, new_addr)                         \
 679 ({                                                                      \
 680         pte_t newpte = (pte);                                           \
 681         if (tlb_type != hypervisor && pte_present(pte)) {               \
 682                 unsigned long this_pfn = pte_pfn(pte);                  \
 683                                                                         \
 684                 if (pfn_valid(this_pfn) &&                              \
 685                     (((old_addr) ^ (new_addr)) & (1 << 13)))            \
 686                         flush_dcache_page_all(current->mm,              \
 687                                               pfn_to_page(this_pfn));   \
 688         }                                                               \
 689         newpte;                                                         \
 690 })
 691 #endif
 692
 693 extern pgd_t swapper_pg_dir[2048];
 694 extern pmd_t swapper_low_pmd_dir[2048];
 695
 696 extern void paging_init(void);
 697 extern unsigned long find_ecache_flush_span(unsigned long size);
 698
 699 /* These do nothing with the way I have things setup. */
 700 #define mmu_lockarea(vaddr, len)                (vaddr)
 701 #define mmu_unlockarea(vaddr, len)              do { } while(0)
 702
 703 struct vm_area_struct;
 704 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 705
 706 /* Encode and de-code a swap entry */
 707 #define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
 708 #define __swp_offset(entry)     ((entry).val >> (PAGE_SHIFT + 8UL))
 709 #define __swp_entry(type, offset)       \
 710         ( (swp_entry_t) \
 711           { \
 712                 (((long)(type) << PAGE_SHIFT) | \
 713                  ((long)(offset) << (PAGE_SHIFT + 8UL))) \
 714           } )
 715 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 716 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 717
 718 /* File offset in PTE support. */
 719 extern unsigned long pte_file(pte_t);
 720 #define pte_to_pgoff(pte)       (pte_val(pte) >> PAGE_SHIFT)
 721 extern pte_t pgoff_to_pte(unsigned long);
 722 #define PTE_FILE_MAX_BITS       (64UL - PAGE_SHIFT - 1UL)
 723
 724 extern unsigned long sparc64_valid_addr_bitmap[];
 725
 726 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 727 static inline bool kern_addr_valid(unsigned long addr)
 728 {
 729         unsigned long paddr = __pa(addr);
 730
 731         if ((paddr >> 41UL) != 0UL)
 732                 return false;
 733         return test_bit(paddr >> 22, sparc64_valid_addr_bitmap);
 734 }
 735
 736 extern int page_in_phys_avail(unsigned long paddr);
 737
 738 extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
 739                                unsigned long pfn,
 740                                unsigned long size, pgprot_t prot);
 741
 742 /*
 743  * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 744  * its high 4 bits.  These macros/functions put it there or get it from there.
 745  */
 746 #define MK_IOSPACE_PFN(space, pfn)      (pfn | (space << (BITS_PER_LONG - 4)))
 747 #define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
 748 #define GET_PFN(pfn)                    (pfn & 0x0fffffffffffffffUL)
 749
 750 #include <asm-generic/pgtable.h>
 751
 752 /* We provide our own get_unmapped_area to cope with VA holes and
 753  * SHM area cache aliasing for userland.
 754  */
 755 #define HAVE_ARCH_UNMAPPED_AREA
 756 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 757
 758 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
 759  * the largest alignment possible such that larget PTEs can be used.
 760  */
 761 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
 762                                           unsigned long, unsigned long,
 763                                           unsigned long);
 764 #define HAVE_ARCH_FB_UNMAPPED_AREA
 765
 766 extern void pgtable_cache_init(void);
 767 extern void sun4v_register_fault_status(void);
 768 extern void sun4v_ktsb_register(void);
 769 extern void __init cheetah_ecache_flush_init(void);
 770 extern void sun4v_patch_tlb_handlers(void);
 771
 772 extern unsigned long cmdline_memory_size;
 773
 774 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
 775
 776 #endif /* !(__ASSEMBLY__) */
 777
 778 #endif /* !(_SPARC64_PGTABLE_H) */