release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/module.h>
  20 #include <linux/kallsyms.h>
  21 #include <linux/io.h>
  22 #include <linux/bug.h>
  23 #include <linux/debug_locks.h>
  24 #include <linux/kdebug.h>
  25 #include <linux/kexec.h>
  26 #include <linux/limits.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/uaccess.h>
  29 #include <asm/system.h>
  30 #include <asm/alignment.h>
  31 #include <asm/fpu.h>
  32 #include <asm/kprobes.h>
  33
  34 #ifdef CONFIG_CPU_SH2
  35 # define TRAP_RESERVED_INST     4
  36 # define TRAP_ILLEGAL_SLOT_INST 6
  37 # define TRAP_ADDRESS_ERROR     9
  38 # ifdef CONFIG_CPU_SH2A
  39 #  define TRAP_UBC              12
  40 #  define TRAP_FPU_ERROR        13
  41 #  define TRAP_DIVZERO_ERROR    17
  42 #  define TRAP_DIVOVF_ERROR     18
  43 # endif
  44 #else
  45 #define TRAP_RESERVED_INST      12
  46 #define TRAP_ILLEGAL_SLOT_INST  13
  47 #endif
  48
  49 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  50 {
  51         unsigned long p;
  52         int i;
  53
  54         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  55
  56         for (p = bottom & ~31; p < top; ) {
  57                 printk("%04lx: ", p & 0xffff);
  58
  59                 for (i = 0; i < 8; i++, p += 4) {
  60                         unsigned int val;
  61
  62                         if (p < bottom || p >= top)
  63                                 printk("         ");
  64                         else {
  65                                 if (__get_user(val, (unsigned int __user *)p)) {
  66                                         printk("\n");
  67                                         return;
  68                                 }
  69                                 printk("%08x ", val);
  70                         }
  71                 }
  72                 printk("\n");
  73         }
  74 }
  75
  76 static DEFINE_SPINLOCK(die_lock);
  77
  78 void die(const char * str, struct pt_regs * regs, long err)
  79 {
  80         static int die_counter;
  81
  82         oops_enter();
  83
  84         spin_lock_irq(&die_lock);
  85         console_verbose();
  86         bust_spinlocks(1);
  87
  88         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  89         sysfs_printk_last_file();
  90         print_modules();
  91         show_regs(regs);
  92
  93         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  94                         task_pid_nr(current), task_stack_page(current) + 1);
  95
  96         if (!user_mode(regs) || in_interrupt())
  97                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  98                          (unsigned long)task_stack_page(current));
  99
 100         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
 101
 102         bust_spinlocks(0);
 103         add_taint(TAINT_DIE);
 104         spin_unlock_irq(&die_lock);
 105         oops_exit();
 106
 107         if (kexec_should_crash(current))
 108                 crash_kexec(regs);
 109
 110         if (in_interrupt())
 111                 panic("Fatal exception in interrupt");
 112
 113         if (panic_on_oops)
 114                 panic("Fatal exception");
 115
 116         do_exit(SIGSEGV);
 117 }
 118
 119 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 120                                  long err)
 121 {
 122         if (!user_mode(regs))
 123                 die(str, regs, err);
 124 }
 125
 126 /*
 127  * try and fix up kernelspace address errors
 128  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 129  * - kernel/userspace interfaces cause a jump to an appropriate handler
 130  * - other kernel errors are bad
 131  */
 132 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 133 {
 134         if (!user_mode(regs)) {
 135                 const struct exception_table_entry *fixup;
 136                 fixup = search_exception_tables(regs->pc);
 137                 if (fixup) {
 138                         regs->pc = fixup->fixup;
 139                         return;
 140                 }
 141
 142                 die(str, regs, err);
 143         }
 144 }
 145
 146 static inline void sign_extend(unsigned int count, unsigned char *dst)
 147 {
 148 #ifdef __LITTLE_ENDIAN__
 149         if ((count == 1) && dst[0] & 0x80) {
 150                 dst[1] = 0xff;
 151                 dst[2] = 0xff;
 152                 dst[3] = 0xff;
 153         }
 154         if ((count == 2) && dst[1] & 0x80) {
 155                 dst[2] = 0xff;
 156                 dst[3] = 0xff;
 157         }
 158 #else
 159         if ((count == 1) && dst[3] & 0x80) {
 160                 dst[2] = 0xff;
 161                 dst[1] = 0xff;
 162                 dst[0] = 0xff;
 163         }
 164         if ((count == 2) && dst[2] & 0x80) {
 165                 dst[1] = 0xff;
 166                 dst[0] = 0xff;
 167         }
 168 #endif
 169 }
 170
 171 static struct mem_access user_mem_access = {
 172         copy_from_user,
 173         copy_to_user,
 174 };
 175
 176 /*
 177  * handle an instruction that does an unaligned memory access by emulating the
 178  * desired behaviour
 179  * - note that PC _may not_ point to the faulting instruction
 180  *   (if that instruction is in a branch delay slot)
 181  * - return 0 if emulation okay, -EFAULT on existential error
 182  */
 183 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 184                                 struct mem_access *ma)
 185 {
 186         int ret, index, count;
 187         unsigned long *rm, *rn;
 188         unsigned char *src, *dst;
 189         unsigned char __user *srcu, *dstu;
 190
 191         index = (instruction>>8)&15;    /* 0x0F00 */
 192         rn = &regs->regs[index];
 193
 194         index = (instruction>>4)&15;    /* 0x00F0 */
 195         rm = &regs->regs[index];
 196
 197         count = 1<<(instruction&3);
 198
 199         switch (count) {
 200         case 1: inc_unaligned_byte_access(); break;
 201         case 2: inc_unaligned_word_access(); break;
 202         case 4: inc_unaligned_dword_access(); break;
 203         case 8: inc_unaligned_multi_access(); break;
 204         }
 205
 206         ret = -EFAULT;
 207         switch (instruction>>12) {
 208         case 0: /* mov.[bwl] to/from memory via r0+rn */
 209                 if (instruction & 8) {
 210                         /* from memory */
 211                         srcu = (unsigned char __user *)*rm;
 212                         srcu += regs->regs[0];
 213                         dst = (unsigned char *)rn;
 214                         *(unsigned long *)dst = 0;
 215
 216 #if !defined(__LITTLE_ENDIAN__)
 217                         dst += 4-count;
 218 #endif
 219                         if (ma->from(dst, srcu, count))
 220                                 goto fetch_fault;
 221
 222                         sign_extend(count, dst);
 223                 } else {
 224                         /* to memory */
 225                         src = (unsigned char *)rm;
 226 #if !defined(__LITTLE_ENDIAN__)
 227                         src += 4-count;
 228 #endif
 229                         dstu = (unsigned char __user *)*rn;
 230                         dstu += regs->regs[0];
 231
 232                         if (ma->to(dstu, src, count))
 233                                 goto fetch_fault;
 234                 }
 235                 ret = 0;
 236                 break;
 237
 238         case 1: /* mov.l Rm,@(disp,Rn) */
 239                 src = (unsigned char*) rm;
 240                 dstu = (unsigned char __user *)*rn;
 241                 dstu += (instruction&0x000F)<<2;
 242
 243                 if (ma->to(dstu, src, 4))
 244                         goto fetch_fault;
 245                 ret = 0;
 246                 break;
 247
 248         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 249                 if (instruction & 4)
 250                         *rn -= count;
 251                 src = (unsigned char*) rm;
 252                 dstu = (unsigned char __user *)*rn;
 253 #if !defined(__LITTLE_ENDIAN__)
 254                 src += 4-count;
 255 #endif
 256                 if (ma->to(dstu, src, count))
 257                         goto fetch_fault;
 258                 ret = 0;
 259                 break;
 260
 261         case 5: /* mov.l @(disp,Rm),Rn */
 262                 srcu = (unsigned char __user *)*rm;
 263                 srcu += (instruction & 0x000F) << 2;
 264                 dst = (unsigned char *)rn;
 265                 *(unsigned long *)dst = 0;
 266
 267                 if (ma->from(dst, srcu, 4))
 268                         goto fetch_fault;
 269                 ret = 0;
 270                 break;
 271
 272         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 273                 srcu = (unsigned char __user *)*rm;
 274                 if (instruction & 4)
 275                         *rm += count;
 276                 dst = (unsigned char*) rn;
 277                 *(unsigned long*)dst = 0;
 278
 279 #if !defined(__LITTLE_ENDIAN__)
 280                 dst += 4-count;
 281 #endif
 282                 if (ma->from(dst, srcu, count))
 283                         goto fetch_fault;
 284                 sign_extend(count, dst);
 285                 ret = 0;
 286                 break;
 287
 288         case 8:
 289                 switch ((instruction&0xFF00)>>8) {
 290                 case 0x81: /* mov.w R0,@(disp,Rn) */
 291                         src = (unsigned char *) &regs->regs[0];
 292 #if !defined(__LITTLE_ENDIAN__)
 293                         src += 2;
 294 #endif
 295                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 296                         dstu += (instruction & 0x000F) << 1;
 297
 298                         if (ma->to(dstu, src, 2))
 299                                 goto fetch_fault;
 300                         ret = 0;
 301                         break;
 302
 303                 case 0x85: /* mov.w @(disp,Rm),R0 */
 304                         srcu = (unsigned char __user *)*rm;
 305                         srcu += (instruction & 0x000F) << 1;
 306                         dst = (unsigned char *) &regs->regs[0];
 307                         *(unsigned long *)dst = 0;
 308
 309 #if !defined(__LITTLE_ENDIAN__)
 310                         dst += 2;
 311 #endif
 312                         if (ma->from(dst, srcu, 2))
 313                                 goto fetch_fault;
 314                         sign_extend(2, dst);
 315                         ret = 0;
 316                         break;
 317                 }
 318                 break;
 319         }
 320         return ret;
 321
 322  fetch_fault:
 323         /* Argh. Address not only misaligned but also non-existent.
 324          * Raise an EFAULT and see if it's trapped
 325          */
 326         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 327         return -EFAULT;
 328 }
 329
 330 /*
 331  * emulate the instruction in the delay slot
 332  * - fetches the instruction from PC+2
 333  */
 334 static inline int handle_delayslot(struct pt_regs *regs,
 335                                    insn_size_t old_instruction,
 336                                    struct mem_access *ma)
 337 {
 338         insn_size_t instruction;
 339         void __user *addr = (void __user *)(regs->pc +
 340                 instruction_size(old_instruction));
 341
 342         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 343                 /* the instruction-fetch faulted */
 344                 if (user_mode(regs))
 345                         return -EFAULT;
 346
 347                 /* kernel */
 348                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 349                     regs, 0);
 350         }
 351
 352         return handle_unaligned_ins(instruction, regs, ma);
 353 }
 354
 355 /*
 356  * handle an instruction that does an unaligned memory access
 357  * - have to be careful of branch delay-slot instructions that fault
 358  *  SH3:
 359  *   - if the branch would be taken PC points to the branch
 360  *   - if the branch would not be taken, PC points to delay-slot
 361  *  SH4:
 362  *   - PC always points to delayed branch
 363  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 364  */
 365
 366 /* Macros to determine offset from current PC for branch instructions */
 367 /* Explicit type coercion is used to force sign extension where needed */
 368 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 369 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 370
 371 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 372                             struct mem_access *ma, int expected)
 373 {
 374         u_int rm;
 375         int ret, index;
 376
 377         if (instruction_size(instruction) != 2)
 378                 return -EINVAL;
 379
 380         index = (instruction>>8)&15;    /* 0x0F00 */
 381         rm = regs->regs[index];
 382
 383         /* shout about fixups */
 384         if (!expected)
 385                 unaligned_fixups_notify(current, instruction, regs);
 386
 387         ret = -EFAULT;
 388         switch (instruction&0xF000) {
 389         case 0x0000:
 390                 if (instruction==0x000B) {
 391                         /* rts */
 392                         ret = handle_delayslot(regs, instruction, ma);
 393                         if (ret==0)
 394                                 regs->pc = regs->pr;
 395                 }
 396                 else if ((instruction&0x00FF)==0x0023) {
 397                         /* braf @Rm */
 398                         ret = handle_delayslot(regs, instruction, ma);
 399                         if (ret==0)
 400                                 regs->pc += rm + 4;
 401                 }
 402                 else if ((instruction&0x00FF)==0x0003) {
 403                         /* bsrf @Rm */
 404                         ret = handle_delayslot(regs, instruction, ma);
 405                         if (ret==0) {
 406                                 regs->pr = regs->pc + 4;
 407                                 regs->pc += rm + 4;
 408                         }
 409                 }
 410                 else {
 411                         /* mov.[bwl] to/from memory via r0+rn */
 412                         goto simple;
 413                 }
 414                 break;
 415
 416         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 417                 goto simple;
 418
 419         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 420                 goto simple;
 421
 422         case 0x4000:
 423                 if ((instruction&0x00FF)==0x002B) {
 424                         /* jmp @Rm */
 425                         ret = handle_delayslot(regs, instruction, ma);
 426                         if (ret==0)
 427                                 regs->pc = rm;
 428                 }
 429                 else if ((instruction&0x00FF)==0x000B) {
 430                         /* jsr @Rm */
 431                         ret = handle_delayslot(regs, instruction, ma);
 432                         if (ret==0) {
 433                                 regs->pr = regs->pc + 4;
 434                                 regs->pc = rm;
 435                         }
 436                 }
 437                 else {
 438                         /* mov.[bwl] to/from memory via r0+rn */
 439                         goto simple;
 440                 }
 441                 break;
 442
 443         case 0x5000: /* mov.l @(disp,Rm),Rn */
 444                 goto simple;
 445
 446         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 447                 goto simple;
 448
 449         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 450                 switch (instruction&0x0F00) {
 451                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 452                         goto simple;
 453                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 454                         goto simple;
 455                 case 0x0B00: /* bf   lab - no delayslot*/
 456                         break;
 457                 case 0x0F00: /* bf/s lab */
 458                         ret = handle_delayslot(regs, instruction, ma);
 459                         if (ret==0) {
 460 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 461                                 if ((regs->sr & 0x00000001) != 0)
 462                                         regs->pc += 4; /* next after slot */
 463                                 else
 464 #endif
 465                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 466                         }
 467                         break;
 468                 case 0x0900: /* bt   lab - no delayslot */
 469                         break;
 470                 case 0x0D00: /* bt/s lab */
 471                         ret = handle_delayslot(regs, instruction, ma);
 472                         if (ret==0) {
 473 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 474                                 if ((regs->sr & 0x00000001) == 0)
 475                                         regs->pc += 4; /* next after slot */
 476                                 else
 477 #endif
 478                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 479                         }
 480                         break;
 481                 }
 482                 break;
 483
 484         case 0xA000: /* bra label */
 485                 ret = handle_delayslot(regs, instruction, ma);
 486                 if (ret==0)
 487                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 488                 break;
 489
 490         case 0xB000: /* bsr label */
 491                 ret = handle_delayslot(regs, instruction, ma);
 492                 if (ret==0) {
 493                         regs->pr = regs->pc + 4;
 494                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 495                 }
 496                 break;
 497         }
 498         return ret;
 499
 500         /* handle non-delay-slot instruction */
 501  simple:
 502         ret = handle_unaligned_ins(instruction, regs, ma);
 503         if (ret==0)
 504                 regs->pc += instruction_size(instruction);
 505         return ret;
 506 }
 507
 508 /*
 509  * Handle various address error exceptions:
 510  *  - instruction address error:
 511  *       misaligned PC
 512  *       PC >= 0x80000000 in user mode
 513  *  - data address error (read and write)
 514  *       misaligned data access
 515  *       access to >= 0x80000000 is user mode
 516  * Unfortuntaly we can't distinguish between instruction address error
 517  * and data address errors caused by read accesses.
 518  */
 519 asmlinkage void do_address_error(struct pt_regs *regs,
 520                                  unsigned long writeaccess,
 521                                  unsigned long address)
 522 {
 523         unsigned long error_code = 0;
 524         mm_segment_t oldfs;
 525         siginfo_t info;
 526         insn_size_t instruction;
 527         int tmp;
 528
 529         /* Intentional ifdef */
 530 #ifdef CONFIG_CPU_HAS_SR_RB
 531         error_code = lookup_exception_vector();
 532 #endif
 533
 534         oldfs = get_fs();
 535
 536         if (user_mode(regs)) {
 537                 int si_code = BUS_ADRERR;
 538                 unsigned int user_action;
 539
 540                 local_irq_enable();
 541                 inc_unaligned_user_access();
 542
 543                 set_fs(USER_DS);
 544                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
 545                                    sizeof(instruction))) {
 546                         set_fs(oldfs);
 547                         goto uspace_segv;
 548                 }
 549                 set_fs(oldfs);
 550
 551                 /* shout about userspace fixups */
 552                 unaligned_fixups_notify(current, instruction, regs);
 553
 554                 user_action = unaligned_user_action();
 555                 if (user_action & UM_FIXUP)
 556                         goto fixup;
 557                 if (user_action & UM_SIGNAL)
 558                         goto uspace_segv;
 559                 else {
 560                         /* ignore */
 561                         regs->pc += instruction_size(instruction);
 562                         return;
 563                 }
 564
 565 fixup:
 566                 /* bad PC is not something we can fix */
 567                 if (regs->pc & 1) {
 568                         si_code = BUS_ADRALN;
 569                         goto uspace_segv;
 570                 }
 571
 572                 set_fs(USER_DS);
 573                 tmp = handle_unaligned_access(instruction, regs,
 574                                               &user_mem_access, 0);
 575                 set_fs(oldfs);
 576
 577                 if (tmp == 0)
 578                         return; /* sorted */
 579 uspace_segv:
 580                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 581                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 582                        regs->pr);
 583
 584                 info.si_signo = SIGBUS;
 585                 info.si_errno = 0;
 586                 info.si_code = si_code;
 587                 info.si_addr = (void __user *)address;
 588                 force_sig_info(SIGBUS, &info, current);
 589         } else {
 590                 inc_unaligned_kernel_access();
 591
 592                 if (regs->pc & 1)
 593                         die("unaligned program counter", regs, error_code);
 594
 595                 set_fs(KERNEL_DS);
 596                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 597                                    sizeof(instruction))) {
 598                         /* Argh. Fault on the instruction itself.
 599                            This should never happen non-SMP
 600                         */
 601                         set_fs(oldfs);
 602                         die("insn faulting in do_address_error", regs, 0);
 603                 }
 604
 605                 unaligned_fixups_notify(current, instruction, regs);
 606
 607                 handle_unaligned_access(instruction, regs,
 608                                         &user_mem_access, 0);
 609                 set_fs(oldfs);
 610         }
 611 }
 612
 613 #ifdef CONFIG_SH_DSP
 614 /*
 615  *      SH-DSP support gerg@snapgear.com.
 616  */
 617 int is_dsp_inst(struct pt_regs *regs)
 618 {
 619         unsigned short inst = 0;
 620
 621         /*
 622          * Safe guard if DSP mode is already enabled or we're lacking
 623          * the DSP altogether.
 624          */
 625         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 626                 return 0;
 627
 628         get_user(inst, ((unsigned short *) regs->pc));
 629
 630         inst &= 0xf000;
 631
 632         /* Check for any type of DSP or support instruction */
 633         if ((inst == 0xf000) || (inst == 0x4000))
 634                 return 1;
 635
 636         return 0;
 637 }
 638 #else
 639 #define is_dsp_inst(regs)       (0)
 640 #endif /* CONFIG_SH_DSP */
 641
 642 #ifdef CONFIG_CPU_SH2A
 643 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 644                                 unsigned long r6, unsigned long r7,
 645                                 struct pt_regs __regs)
 646 {
 647         siginfo_t info;
 648
 649         switch (r4) {
 650         case TRAP_DIVZERO_ERROR:
 651                 info.si_code = FPE_INTDIV;
 652                 break;
 653         case TRAP_DIVOVF_ERROR:
 654                 info.si_code = FPE_INTOVF;
 655                 break;
 656         }
 657
 658         force_sig_info(SIGFPE, &info, current);
 659 }
 660 #endif
 661
 662 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 663                                 unsigned long r6, unsigned long r7,
 664                                 struct pt_regs __regs)
 665 {
 666         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 667         unsigned long error_code;
 668         struct task_struct *tsk = current;
 669
 670 #ifdef CONFIG_SH_FPU_EMU
 671         unsigned short inst = 0;
 672         int err;
 673
 674         get_user(inst, (unsigned short*)regs->pc);
 675
 676         err = do_fpu_inst(inst, regs);
 677         if (!err) {
 678                 regs->pc += instruction_size(inst);
 679                 return;
 680         }
 681         /* not a FPU inst. */
 682 #endif
 683
 684 #ifdef CONFIG_SH_DSP
 685         /* Check if it's a DSP instruction */
 686         if (is_dsp_inst(regs)) {
 687                 /* Enable DSP mode, and restart instruction. */
 688                 regs->sr |= SR_DSP;
 689                 /* Save DSP mode */
 690                 tsk->thread.dsp_status.status |= SR_DSP;
 691                 return;
 692         }
 693 #endif
 694
 695         error_code = lookup_exception_vector();
 696
 697         local_irq_enable();
 698         force_sig(SIGILL, tsk);
 699         die_if_no_fixup("reserved instruction", regs, error_code);
 700 }
 701
 702 #ifdef CONFIG_SH_FPU_EMU
 703 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 704 {
 705         /*
 706          * bfs: 8fxx: PC+=d*2+4;
 707          * bts: 8dxx: PC+=d*2+4;
 708          * bra: axxx: PC+=D*2+4;
 709          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 710          * braf:0x23: PC+=Rn*2+4;
 711          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 712          * jmp: 4x2b: PC=Rn;
 713          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 714          * rts: 000b: PC=PR;
 715          */
 716         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 717             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 718             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 719                 regs->pr = regs->pc + 4;
 720
 721         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 722                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 723                 return 0;
 724         }
 725
 726         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 727                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 728                 return 0;
 729         }
 730
 731         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 732                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 733                 return 0;
 734         }
 735
 736         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 737                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 738                 return 0;
 739         }
 740
 741         if ((inst & 0xffff) == 0x000b) {        /* rts */
 742                 regs->pc = regs->pr;
 743                 return 0;
 744         }
 745
 746         return 1;
 747 }
 748 #endif
 749
 750 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 751                                 unsigned long r6, unsigned long r7,
 752                                 struct pt_regs __regs)
 753 {
 754         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 755         unsigned long inst;
 756         struct task_struct *tsk = current;
 757
 758         if (kprobe_handle_illslot(regs->pc) == 0)
 759                 return;
 760
 761 #ifdef CONFIG_SH_FPU_EMU
 762         get_user(inst, (unsigned short *)regs->pc + 1);
 763         if (!do_fpu_inst(inst, regs)) {
 764                 get_user(inst, (unsigned short *)regs->pc);
 765                 if (!emulate_branch(inst, regs))
 766                         return;
 767                 /* fault in branch.*/
 768         }
 769         /* not a FPU inst. */
 770 #endif
 771
 772         inst = lookup_exception_vector();
 773
 774         local_irq_enable();
 775         force_sig(SIGILL, tsk);
 776         die_if_no_fixup("illegal slot instruction", regs, inst);
 777 }
 778
 779 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 780                                    unsigned long r6, unsigned long r7,
 781                                    struct pt_regs __regs)
 782 {
 783         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 784         long ex;
 785
 786         ex = lookup_exception_vector();
 787         die_if_kernel("exception", regs, ex);
 788 }
 789
 790 void __cpuinit per_cpu_trap_init(void)
 791 {
 792         extern void *vbr_base;
 793
 794         /* NOTE: The VBR value should be at P1
 795            (or P2, virtural "fixed" address space).
 796            It's definitely should not in physical address.  */
 797
 798         asm volatile("ldc       %0, vbr"
 799                      : /* no output */
 800                      : "r" (&vbr_base)
 801                      : "memory");
 802 }
 803
 804 void *set_exception_table_vec(unsigned int vec, void *handler)
 805 {
 806         extern void *exception_handling_table[];
 807         void *old_handler;
 808
 809         old_handler = exception_handling_table[vec];
 810         exception_handling_table[vec] = handler;
 811         return old_handler;
 812 }
 813
 814 void __init trap_init(void)
 815 {
 816         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 817         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 818
 819 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || defined(CONFIG_SH_FPU_EMU)
 820         /*
 821          * For SH-4 lacking an FPU, treat floating point instructions as
 822          * reserved. They'll be handled in the math-emu case, or faulted on
 823          * otherwise.
 824          */
 825         set_exception_table_evt(0x800, do_reserved_inst);
 826         set_exception_table_evt(0x820, do_illegal_slot_inst);
 827 #elif defined(CONFIG_SH_FPU)
 828         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 829         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 830 #endif
 831
 832 #ifdef CONFIG_CPU_SH2
 833         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 834 #endif
 835 #ifdef CONFIG_CPU_SH2A
 836         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 837         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 838 #ifdef CONFIG_SH_FPU
 839         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 840 #endif
 841 #endif
 842
 843 #ifdef TRAP_UBC
 844         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 845 #endif
 846 }
 847
 848 void show_stack(struct task_struct *tsk, unsigned long *sp)
 849 {
 850         unsigned long stack;
 851
 852         if (!tsk)
 853                 tsk = current;
 854         if (tsk == current)
 855                 sp = (unsigned long *)current_stack_pointer;
 856         else
 857                 sp = (unsigned long *)tsk->thread.sp;
 858
 859         stack = (unsigned long)sp;
 860         dump_mem("Stack: ", stack, THREAD_SIZE +
 861                  (unsigned long)task_stack_page(tsk));
 862         show_trace(tsk, sp, NULL);
 863 }
 864
 865 void dump_stack(void)
 866 {
 867         show_stack(NULL, NULL);
 868 }
 869 EXPORT_SYMBOL(dump_stack);