release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/drivers/pci/pcie-sh7786.h

   1 /*
   2  * SH7786 PCI-Express controller definitions.
   3  *
   4  * Copyright (C) 2008, 2009 Renesas Technology Corp.
   5  * All rights reserved.
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #ifndef __PCI_SH7786_H
  12 #define __PCI_SH7786_H
  13
  14 /* PCIe bus-0(x4) on SH7786 */                  // Rev1.171
  15 #define SH4A_PCIE_SPW_BASE      0xFE000000      /* spw config address for controller 0 */
  16 #define SH4A_PCIE_SPW_BASE1     0xFE200000      /* spw config address for controller 1 (Rev1.14)*/
  17 #define SH4A_PCIE_SPW_BASE2     0xFCC00000      /* spw config address for controller 2 (Rev1.171)*/
  18 #define SH4A_PCIE_SPW_BASE_LEN  0x00080000
  19
  20 #define SH4A_PCI_CNFG_BASE      0xFE040000      /* pci config address for controller 0 */
  21 #define SH4A_PCI_CNFG_BASE1     0xFE240000      /* pci config address for controller 1 (Rev1.14)*/
  22 #define SH4A_PCI_CNFG_BASE2     0xFCC40000      /* pci config address for controller 2 (Rev1.171)*/
  23 #define SH4A_PCI_CNFG_BASE_LEN  0x00040000
  24
  25 #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0      /* offset to pci config_address */
  26 #define SH4A_PCIPIO_DATA_OFFSET 0x00000220      /* offset to pci config_data */
  27
  28 /*
  29  * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K),
  30  * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
  31  */
  32
  33 /* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
  34 #define SH4A_PCIBMSTR_TRANSLATION       0x20000000
  35
  36 /*      SPVCR0          */
  37 #define SH4A_PCIEVCR0           (0x000000)      /* R - 0x0000 0000 32 */
  38 #define         BITS_TOP_MB     (24)
  39 #define         MASK_TOP_MB     (0xff<<BITS_TOP_MB)
  40 #define         BITS_BOT_MB     (16)
  41 #define         MASK_BOT_MB     (0xff<<BITS_BOT_MB)
  42 #define         BITS_VC_ID      (0)
  43 #define         MASK_VC_ID      (0xffff<<BITS_VC_ID)
  44
  45 /*      SPVCR1          */
  46 #define SH4A_PCIEVCR1           (0x000004)      /* R - 0x0000 0000 32*/
  47 #define         BITS_BADOPC     (5)             /* 5 BADOPC 0 R/W */
  48 #define         MASK_BADOPC     (1<<BITS_BADOPC)
  49 #define         BITS_BADDEST    (4)             /*4 BADDEST 0 R/W  */
  50 #define         MASK_BADDEST    (1<<BITS_BADDEST)
  51 #define         BITS_UNSOLRESP  (3)             /* 3 UNSOLRESP 0 R/W  */
  52 #define         MASK_UNSOLRESP  (1<<BITS_UNSOLRESP)
  53 #define         BITS_ERRSNT     (1)             /* 1 ERRSNT 0 */
  54 #define         MASK_ERRSNT     (1<<BITS_ERRSNT)
  55 #define         BITS_ERRRCV     (0)             /* 0 ERRRCV 0 */
  56 #define         MASK_ERRRCV     (1<<BITS_ERRRCV)
  57
  58 /*      PCIEECR         */
  59 #define SH4A_PCIEECR            (0x000008)      /* R/W - 0x0000 0000 32 */
  60 #define         BITS_ENBL       (0)     /* 0 ENBL 0 R/W */
  61 #define         MASK_ENBL       (1<<BITS_ENBL)
  62
  63 /*      PCIEPAR         */
  64 #define SH4A_PCIEPAR            (0x000010)      /* R/W - 0x0000 0000 32 */
  65 #define         BITS_BN         (24)
  66 #define         MASK_BN         (0xff<<BITS_BN)
  67 #define         BITS_DN         (19)
  68 #define         MASK_DN         (0x1f<<BITS_DN)
  69 #define         BITS_FN         (16)
  70 #define         MASK_FN         (0x7<<BITS_FN)
  71 #define         BITS_EREGNO     (8)
  72 #define         MASK_EREGNO     (0xff<<BITS_EREGNO)
  73 #define         BITS_REGNO      (2)
  74 #define         MASK_REGNO      (0x3f<<BITS_REGNO)
  75
  76 /*      PCIEPCTLR       */
  77 #define SH4A_PCIEPCTLR          (0x000018)      /* R/W - 0x0000 0000 32 */
  78 #define         BITS_CCIE       (31)    /*  31 CCIE */
  79 #define         MASK_CCIE       (1<<BITS_CCIE)
  80 #define         BITS_TYPE       (8)
  81 #define         MASK_TYPE       (1<<BITS_TYPE)
  82 #define         BITS_C_VC       (0)
  83 #define         MASK_C_VC       (1<<BITS_C_VC)
  84
  85 /*      PCIEPDR         */
  86 #define SH4A_PCIEPDR            (0x000020)      /* R/W - 0x0000 0000 32 */
  87 #define         BITS_PDR        (0)
  88 #define         MASK_PDR        (0xffffffff<<BITS_PDR)
  89
  90 /*      PCIEMSGALR      */
  91 #define SH4A_PCIEMSGALR         (0x000030)      /* R/W - 0x0000 0000 32 */
  92 #define         BITS_MSGADRL    (0)
  93 #define         MASK_MSGADRL    (0xffffffff<<BITS_MSGADRL)
  94
  95 /*      PCIEMSGAHR      */
  96 #define SH4A_PCIEMSGAHR         (0x000034)      /* R/W - 0x0000 0000 32 */
  97 #define         BITS_MSGADRH    (0)
  98 #define         MASK_MSGADRH    (0xffffffff<<BITS_MSGADRH)
  99
 100 /*      PCIEMSGCTLR     */
 101 #define SH4A_PCIEMSGCTLR        (0x000038)      /* R/W - 0x0000 0000 32 */
 102 #define         BITS_MSGIE      (31)
 103 #define         MASK_MSGIE      (1<<BITS_MSGIE)
 104 #define         BITS_MROUTE     (16)
 105 #define         MASK_MROUTE     (0x7<<BITS_MROUTE)
 106 #define         BITS_MCODE      (8)
 107 #define         MASK_MCODE      (0xff<<BITS_MCODE)
 108 #define         BITS_M_VC       (0)
 109 #define         MASK_M_VC       (1<<BITS_M_VC)
 110
 111 /*      PCIEMSG         */
 112 #define SH4A_PCIEMSG            (0x000040)      /* W - - 32     */
 113 #define         BITS_MDATA      (0)
 114 #define         MASK_MDATA      (0xffffffff<<BITS_MDATA)
 115
 116 /*      PCIEPHYCTLR     */
 117 #define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
 118 #define         BITS_CKE        (0)
 119 #define         MASK_CKE        (1<<BITS_CKE)
 120
 121 /*      PCIERMSGIER     */
 122 #define SH4A_PCIERMSGIER        (0x004040)      /* R/W - 0x0000 0000 32 */
 123
 124 /*      PCIEPHYADRR     */
 125 #define SH4A_PCIEPHYADRR        (0x010004)      /* R/W - 0x0000 0000 32 */
 126 #define         BITS_ACK        (24)                    // Rev1.171
 127 #define         MASK_ACK        (1<<BITS_ACK)           // Rev1.171
 128 #define         BITS_CMD        (16)                    // Rev1.171
 129 #define         MASK_CMD        (0x03<<BITS_CMD)        // Rev1.171
 130 #define         BITS_LANE       (8)
 131 #define         MASK_LANE       (0x0f<<BITS_LANE)
 132 #define         BITS_ADR        (0)
 133 #define         MASK_ADR        (0xff<<BITS_ADR)
 134
 135 /*      PCIEPHYDINR     */                                                      // Rev1.171 start.
 136 #define SH4A_PCIEPHYDINR        (0x010008)      /* R/W - 0x0000 0000 32 */
 137
 138 /*      PCIEPHYDOUTR    */
 139 #define SH4A_PCIEPHYDOUTR       (0x01000C)      /* R/W - 0x0000 0000 32 */
 140
 141 /*      PCIEPHYSR       */
 142 #define SH4A_PCIEPHYSR          (0x010010)      /* R/W - 0x0000 0000 32 */      // Rev1.171 end.
 143
 144 /*      PCIEPHYDATAR    */
 145 #define SH4A_PCIEPHYDATAR       (0x00008)
 146 #define         BITS_DATA       (0)
 147 #define         MASK_DATA       (0xffffffff<<BITS_DATA)
 148
 149 /*      PCIETCTLR       */
 150 #define SH4A_PCIETCTLR          (0x020000)      /* R/W R/W 0x0000 0000 32 */
 151 #define         BITS_CFINT      (0)
 152 #define         MASK_CFINT      (1<<BITS_CFINT)
 153
 154 /*      PCIETSTR        */
 155 #define SH4A_PCIETSTR           (0x020004)      /* R/W R/W 0x0000 0000 32  */
 156
 157 /*      PCIEINTR        */
 158 #define SH4A_PCIEINTR           (0x020008)      /* R/W R/W 0x0000 0000 32  */
 159 #define         BITS_INT_RX_ERP                 (31)
 160 #define         MASK_INT_RX_ERP                 (1<<BITS_INT_RX_ERP)
 161 #define         BITS_INT_RX_VCX_Posted          (30)
 162 #define         MASK_INT_RX_VCX_Posted          (1<<BITS_INT_RX_VCX_Posted)
 163 #define         BITS_INT_RX_VCX_NonPosted       (29)
 164 #define         MASK_INT_RX_VCX_NonPosted       (1<<BITS_INT_RX_VCX_NonPosted)
 165 #define         BITS_INT_RX_VCX_CPL             (28)
 166 #define         MASK_INT_RX_VCX_CPL             (1<<BITS_INT_RX_VCX_CPL)
 167 #define         BITS_INT_TX_VCX_Posted          (26)
 168 #define         MASK_INT_TX_VCX_Posted          (1<<BITS_INT_TX_VCX_Posted)
 169 #define         BITS_INT_TX_VCX_NonPosted       (25)
 170 #define         MASK_INT_TX_VCX_NonPosted       (1<<BITS_INT_TX_VCX_NonPosted)
 171 #define         BITS_INT_TX_VCX_CPL             (24)
 172 #define         MASK_INT_TX_VCX_CPL             (1<<BITS_INT_TX_VCX_CPL)
 173 #define         BITS_INT_RX_VC0_Posted          (22)
 174 #define         MASK_INT_RX_VC0_Posted          (1<<BITS_INT_RX_VC0_Posted)
 175 #define         BITS_INT_RX_VC0_NonPosted       (21)
 176 #define         MASK_INT_RX_VC0_NonPosted       (1<<BITS_INT_RX_VC0_NonPosted)
 177 #define         BITS_INT_RX_VC0_CPL             (20)
 178 #define         MASK_INT_RX_VC0_CPL             (1<<BITS_INT_RX_VC0_CPL)
 179 #define         BITS_INT_TX_VC0_Posted          (18)
 180 #define         MASK_INT_TX_VC0_Posted          (1<<BITS_INT_TX_VC0_Posted)
 181 #define         BITS_INT_TX_VC0_NonPosted       (17)
 182 #define         MASK_INT_TX_VC0_NonPosted       (1<<BITS_INT_TX_VC0_NonPosted)
 183 #define         BITS_INT_TX_VC0_CPL             (16)
 184 #define         MASK_INT_TX_VC0_CPL             (1<<BITS_INT_TX_VC0_CPL)
 185 #define         BITS_INT_RX_CTRL                (15)
 186 #define         MASK_INT_RX_CTRL                (1<<BITS_INT_RX_CTRL)
 187 #define         BITS_INT_TX_CTRL                (14)
 188 #define         MASK_INT_TX_CTRL                (1<<BITS_INT_TX_CTRL)
 189 #define         BITS_INTTL                      (11)
 190 #define         MASK_INTTL                      (1<<BITS_INTTL)
 191 #define         BITS_INTDL                      (10)
 192 #define         MASK_INTDL                      (1<<BITS_INTDL)
 193 #define         BITS_INTMAC                     (9)
 194 #define         MASK_INTMAC                     (1<<BITS_INTMAC)
 195 #define         BITS_INTPM                      (8)
 196 #define         MASK_INTPM                      (1<<BITS_INTPM)
 197
 198 /*      PCIEINTER       */
 199 #define SH4A_PCIEINTER          (0x02000C)      /* R/W R/W 0x0000 0000 32 */
 200 #define         BITS_INT_RX_ERP                 (31)
 201 #define         MASK_INT_RX_ERP                 (1<<BITS_INT_RX_ERP)
 202 #define         BITS_INT_RX_VCX_Posted          (30)
 203 #define         MASK_INT_RX_VCX_Posted          (1<<BITS_INT_RX_VCX_Posted)
 204 #define         BITS_INT_RX_VCX_NonPosted       (29)
 205 #define         MASK_INT_RX_VCX_NonPosted       (1<<BITS_INT_RX_VCX_NonPosted)
 206 #define         BITS_INT_RX_VCX_CPL             (28)
 207 #define         MASK_INT_RX_VCX_CPL             (1<<BITS_INT_RX_VCX_CPL)
 208 #define         BITS_INT_TX_VCX_Posted          (26)
 209 #define         MASK_INT_TX_VCX_Posted          (1<<BITS_INT_TX_VCX_Posted)
 210 #define         BITS_INT_TX_VCX_NonPosted       (25)
 211 #define         MASK_INT_TX_VCX_NonPosted       (1<<BITS_INT_TX_VCX_NonPosted)
 212 #define         BITS_INT_TX_VCX_CPL             (24)
 213 #define         MASK_INT_TX_VCX_CPL             (1<<BITS_INT_TX_VCX_CPL)
 214 #define         BITS_INT_RX_VC0_Posted          (22)
 215 #define         MASK_INT_RX_VC0_Posted          (1<<BITS_INT_RX_VC0_Posted)
 216 #define         BITS_INT_RX_VC0_NonPosted       (21)
 217 #define         MASK_INT_RX_VC0_NonPosted       (1<<BITS_INT_RX_VC0_NonPosted)
 218 #define         BITS_INT_RX_VC0_CPL             (20)
 219 #define         MASK_INT_RX_VC0_CPL             (1<<BITS_INT_RX_VC0_CPL)
 220 #define         BITS_INT_TX_VC0_Posted          (18)
 221 #define         MASK_INT_TX_VC0_Posted          (1<<BITS_INT_TX_VC0_Posted)
 222 #define         BITS_INT_TX_VC0_NonPosted       (17)
 223 #define         MASK_INT_TX_VC0_NonPosted       (1<<BITS_INT_TX_VC0_NonPosted)
 224 #define         BITS_INT_TX_VC0_CPL             (16)
 225 #define         MASK_INT_TX_VC0_CPL             (1<<BITS_INT_TX_VC0_CPL)
 226 #define         BITS_INT_RX_CTRL                (15)
 227 #define         MASK_INT_RX_CTRL                (1<<BITS_INT_RX_CTRL)
 228 #define         BITS_INT_TX_CTRL                (14)
 229 #define         MASK_INT_TX_CTRL                (1<<BITS_INT_TX_CTRL)
 230 #define         BITS_INTTL                      (11)
 231 #define         MASK_INTTL                      (1<<BITS_INTTL)
 232 #define         BITS_INTDL                      (10)
 233 #define         MASK_INTDL                      (1<<BITS_INTDL)
 234 #define         BITS_INTMAC                     (9)
 235 #define         MASK_INTMAC                     (1<<BITS_INTMAC)
 236 #define         BITS_INTPM                      (8)
 237 #define         MASK_INTPM                      (1<<BITS_INTPM)
 238
 239 /*      PCIEAIR  */
 240 #define SH4A_PCIEAIR            (SH4A_PCIE_BASE + 0x020010)
 241
 242 /*       PCIECIR         */
 243 #define SH4A_PCIECIR            (SH4A_PCIE_BASE)
 244
 245 /*       PCIEERRFR       */                                                             // Rev1.18
 246 #define SH4A_PCIEERRFR          (0x020020)      // Rev1.18
 247                                                                                         // Rev1.18
 248 /*      PCIELAR0        */
 249 #define SH4A_PCIELAR0           (0x020200)      /* R/W R/W 0x0000 0000 32 */
 250 #define         BITS_LARn       (20)
 251 #define         MASK_LARn       (0xfff<<BITS_LARn)
 252
 253 #define SH4A_PCIE_020204        (0x020204)      /* R/W R/W 0x0000 0000 32 */
 254
 255 /*      PCIELAMR0       */
 256 #define SH4A_PCIELAMR0          (0x020208)      /* R/W R/W 0x0000 0000 32 */
 257 #define         BITS_LAMRn      (20)
 258 #define         MASK_LAMRn      (0x1ff<<BITS_LAMRn)
 259 #define         BITS_LAREn      (0)
 260 #define         MASK_LAREn      (0x1<<BITS_LAREn)
 261
 262 /*      PCIECSCR0       */
 263 #define SH4A_PCIECSCR0          (0x020210)      /* R/W R/W 0x0000 0000 32 */
 264 #define         BITS_RANGE      (2)
 265 #define         MASK_RANGE      (0x7<<BITS_RANGE)
 266 #define         BITS_SNPMD      (0)
 267 #define         MASK_SNPMD      (0x3<<BITS_SNPMD)
 268
 269 /*      PCIECSAR0       */
 270 #define SH4A_PCIECSAR0          (0x020214)      /* R/W R/W 0x0000 0000 32 */
 271 #define         BITS_CSADR      (0)
 272 #define         MASK_CSADR      (0xffffffff<<BITS_CSADR)
 273
 274 /*      PCIESTCTLR0     */
 275 #define SH4A_PCIESTCTLR0        (0x020218)      /* R/W R/W 0x0000 0000 32 */
 276 #define         BITS_SHPRI      (8)
 277 #define         MASK_SHPRI      (0x0f<<BITS_SHPRI)
 278
 279 #define SH4A_PCIE_020224        (0x020224)      /* R/W R/W 0x0000 0000 32 */
 280
 281 #define SH4A_PCIELAR1           (0x020220)      /* R/W R/W 0x0000 0000 32 */
 282 #define SH4A_PCIELAMR1          (0x020228)      /* R/W R/W 0x0000 0000 32 */
 283 #define SH4A_PCIECSCR1          (0x020230)      /* R/W R/W 0x0000 0000 32 */
 284 #define SH4A_PCIECSAR1          (0x020234)      /* R/W R/W 0x0000 0000 32 */
 285 #define SH4A_PCIESTCTLR1        (0x020238)      /* R/W R/W 0x0000 0000 32 */
 286
 287 #define SH4A_PCIELAR2           (0x020240)      /* R/W R/W 0x0000 0000 32 */
 288 #define SH4A_PCIE_020244        (0x020244)      /* R/W R/W 0x0000 0000 32 */
 289 #define SH4A_PCIELAMR2          (0x020248)      /* R/W R/W 0x0000 0000 32 */
 290 #define SH4A_PCIECSCR2          (0x020250)      /* R/W R/W 0x0000 0000 32 */
 291 #define SH4A_PCIECSAR2          (0x020254)      /* R/W R/W 0x0000 0000 32 */
 292 #define SH4A_PCIESTCTLR2        (0x020258)      /* R/W R/W 0x0000 0000 32 */
 293
 294 #define SH4A_PCIELAR3           (0x020260)      /* R/W R/W 0x0000 0000 32 */
 295 #define SH4A_PCIE_020264        (0x020264)      /* R/W R/W 0x0000 0000 32 */
 296 #define SH4A_PCIELAMR3          (0x020268)      /* R/W R/W 0x0000 0000 32 */
 297 #define SH4A_PCIECSCR3          (0x020270)      /* R/W R/W 0x0000 0000 32 */
 298 #define SH4A_PCIECSAR3          (0x020274)      /* R/W R/W 0x0000 0000 32 */
 299 #define SH4A_PCIESTCTLR3        (0x020278)      /* R/W R/W 0x0000 0000 32 */
 300
 301 #define SH4A_PCIELAR4           (0x020280)      /* R/W R/W 0x0000 0000 32 */
 302 #define SH4A_PCIE_020284        (0x020284)      /* R/W R/W 0x0000 0000 32 */
 303 #define SH4A_PCIELAMR4          (0x020288)      /* R/W R/W 0x0000 0000 32 */
 304 #define SH4A_PCIECSCR4          (0x020290)      /* R/W R/W 0x0000 0000 32 */
 305 #define SH4A_PCIECSAR4          (0x020294)      /* R/W R/W 0x0000 0000 32 */
 306 #define SH4A_PCIESTCTLR4        (0x020298)      /* R/W R/W 0x0000 0000 32 */
 307
 308 #define SH4A_PCIELAR5           (0x0202A0)      /* R/W R/W 0x0000 0000 32 */
 309 #define SH4A_PCIE_0202A4        (0x0202A4)      /* R/W R/W 0x0000 0000 32 */
 310 #define SH4A_PCIELAMR5          (0x0202A8)      /* R/W R/W 0x0000 0000 32 */
 311 #define SH4A_PCIECSCR5          (0x0202B0)      /* R/W R/W 0x0000 0000 32 */
 312 #define SH4A_PCIECSAR5          (0x0202B4)      /* R/W R/W 0x0000 0000 32 */
 313 #define SH4A_PCIESTCTLR5        (0x0202B8)      /* R/W R/W 0x0000 0000 32 */
 314
 315 /*      PCIEPARL        */
 316 #define SH4A_PCIEPARL(x)        (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 317 #define         BITS_PAL        (18)
 318 #define         MASK_PAL        (0x3fff<<BITS_PAL)
 319
 320 /*      PCIEPARH        */
 321 #define SH4A_PCIEPARH(x)        (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 322 #define         BITS_PAH        (0)
 323 #define         MASK_PAH        (0xffffffff<<BITS_PAH)
 324
 325 /*      PCIEPAMR         */
 326 #define SH4A_PCIEPAMR(x)        (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 327 #define         BITS_PAM        (18)
 328 #define         MASK_PAM        (0x3fff<<BITS_PAM)
 329
 330 /*      PCIEPTCTLR      */
 331 #define SH4A_PCIEPTCTLR(x)      (0x02040C + ((x) * 0x20))
 332 #define         BITS_PARE       (31)
 333 #define         MASK_PARE       (0x1<<BITS_PARE)
 334 #define         BITS_TC         (20)
 335 #define         MASK_TC         (0x7<<BITS_TC)
 336 #define         BITS_T_VC       (16)
 337 #define         MASK_T_VC       (0x1<<BITS_T_VC)
 338 #define         BITS_LOCK       (12)
 339 #define         MASK_LOCK       (0x1<<BITS_LOCK)
 340 #define         BITS_SPC        (8)
 341 #define         MASK_SPC        (0x1<<BITS_SPC)
 342
 343 #define SH4A_PCIEDMAOR          (0x021000)      /* R/W R/W 0x0000 0000 32 */
 344 #define SH4A_PCIEDMSAR0         (0x021100)      /* R/W R/W 0x0000 0000 32 */
 345 #define SH4A_PCIEDMSAHR0        (0x021104)      /* R/W R/W 0x0000 0000 32 */
 346 #define SH4A_PCIEDMDAR0         (0x021108)      /* R/W R/W 0x0000 0000 32 */
 347 #define SH4A_PCIEDMDAHR0        (0x02110C)      /* R/W R/W 0x0000 0000 32 */
 348 #define SH4A_PCIEDMBCNTR0       (0x021110)      /* R/W R/W 0x0000 0000 32 */
 349 #define SH4A_PCIEDMSBCNTR0      (0x021114)      /* R/W R/W 0x0000 0000 32 */
 350 #define SH4A_PCIEDMSTRR0        (0x021118)      /* R/W R/W 0x0000 0000 32 */
 351 #define SH4A_PCIEDMCCAR0        (0x02111C)      /* R/W R/W 0x0000 0000 32 */
 352 #define SH4A_PCIEDMCCR0         (0x021120)      /* R/W R/W 0x0000 0000 32 */
 353 #define SH4A_PCIEDMCC2R0        (0x021124)      /* R/W R/W 0x0000 0000 - */
 354 #define SH4A_PCIEDMCCCR0        (0x021128)      /* R/W R/W 0x0000 0000 32 */
 355 #define SH4A_PCIEDMSAR1         (0x021140)      /* R/W R/W 0x0000 0000 32 */
 356 #define SH4A_PCIEDMSAHR1        (0x021144)      /* R/W R/W 0x0000 0000 32 */
 357 #define SH4A_PCIEDMDAR1         (0x021148)      /* R/W R/W 0x0000 0000 32 */
 358 #define SH4A_PCIEDMDAHR1        (0x02114C)      /* R/W R/W 0x0000 0000 32 */
 359 #define SH4A_PCIEDMBCNTR1       (0x021150)      /* R/W R/W 0x0000 0000 32 */
 360 #define SH4A_PCIEDMSBCNTR1      (0x021154)      /* R/W R/W 0x0000 0000 32 */
 361 #define SH4A_PCIEDMSTRR1        (0x021158)      /* R/W R/W 0x0000 0000 32 */
 362 #define SH4A_PCIEDMCCAR1        (0x02115C)      /* R/W R/W 0x0000 0000 32 */
 363 #define SH4A_PCIEDMCCR1         (0x021160)      /* R/W R/W 0x0000 0000 32 */
 364 #define SH4A_PCIEDMCC2R1        (0x021164)      /* R/W R/W 0x0000 0000 - */
 365 #define SH4A_PCIEDMCCCR1        (0x021168)      /* R/W R/W 0x0000 0000 32 */
 366 #define SH4A_PCIEDMSAR2         (0x021180)      /* R/W R/W 0x0000 0000 32 */
 367 #define SH4A_PCIEDMSAHR2        (0x021184)      /* R/W R/W 0x0000 0000 32 */
 368 #define SH4A_PCIEDMDAR2         (0x021188)      /* R/W R/W 0x0000 0000 32 */
 369 #define SH4A_PCIEDMDAHR2        (0x02118C)      /* R/W R/W 0x0000 0000 32 */
 370 #define SH4A_PCIEDMBCNTR2       (0x021190)      /* R/W R/W 0x0000 0000 32 */
 371 #define SH4A_PCIEDMSBCNTR2      (0x021194)      /* R/W R/W 0x0000 0000 32 */
 372 #define SH4A_PCIEDMSTRR2        (0x021198)      /* R/W R/W 0x0000 0000 32 */
 373 #define SH4A_PCIEDMCCAR2        (0x02119C)      /* R/W R/W 0x0000 0000 32 */
 374 #define SH4A_PCIEDMCCR2         (0x0211A0)      /* R/W R/W 0x0000 0000 32 */
 375 #define SH4A_PCIEDMCC2R2        (0x0211A4)      /* R/W R/W 0x0000 0000 -  */
 376 #define SH4A_PCIEDMCCCR2        (0x0211A8)      /* R/W R/W 0x0000 0000 32 */
 377 #define SH4A_PCIEDMSAR3         (0x0211C0)      /* R/W R/W 0x0000 0000 32 */
 378 #define SH4A_PCIEDMSAHR3        (0x0211C4)      /* R/W R/W 0x0000 0000 32 */
 379 #define SH4A_PCIEDMDAR3         (0x0211C8)      /* R/W R/W 0x0000 0000 32 */
 380 #define SH4A_PCIEDMDAHR3        (0x0211CC)      /* R/W R/W 0x0000 0000 32 */
 381 #define SH4A_PCIEDMBCNTR3       (0x0211D0)      /* R/W R/W 0x0000 0000 32 */
 382 #define SH4A_PCIEDMSBCNTR3      (0x0211D4)      /* R/W R/W 0x0000 0000 32 */
 383 #define SH4A_PCIEDMSTRR3        (0x0211D8)      /* R/W R/W 0x0000 0000 32 */
 384 #define SH4A_PCIEDMCCAR3        (0x0211DC)      /* R/W R/W 0x0000 0000 32 */
 385 #define SH4A_PCIEDMCCR3         (0x0211E0)      /* R/W R/W 0x0000 0000 32 */
 386 #define SH4A_PCIEDMCC2R3        (0x0211E4)      /* R/W R/W 0x0000 0000 -  */
 387 #define SH4A_PCIEDMCCCR3        (0x0211E8)      /* R/W R/W 0x0000 0000 32 */
 388 #define SH4A_PCIEPCICONF0       (0x040000)      /* R R - 8/16/32 */
 389 #define SH4A_PCIEPCICONF1       (0x040004)      /* R/W R/W 0x0008 0000 8/16/32 */
 390 #define SH4A_PCIEPCICONF2       (0x040008)      /* R/W R/W 0xFF00 0000 8/16/32 */
 391 #define SH4A_PCIEPCICONF3       (0x04000C)      /* R/W R/W 0x0000 0000 8/16/32 */
 392 #define SH4A_PCIEPCICONF4       (0x040010)      /* - R/W - 8/16/32 */
 393 #define SH4A_PCIEPCICONF5       (0x040014)      /* - R/W - 8/16/32 */
 394 #define SH4A_PCIEPCICONF6       (0x040018)      /* - R/W - 8/16/32 */
 395 #define SH4A_PCIEPCICONF7       (0x04001C)      /* - R/W - 8/16/32 */
 396 #define SH4A_PCIEPCICONF8       (0x040020)      /* - R/W - 8/16/32 */
 397 #define SH4A_PCIEPCICONF9       (0x040024)      /* - R/W - 8/16/32 */
 398 #define SH4A_PCIEPCICONF10      (0x040028)      /* R/W R/W 0x0000 0000 8/16/32 */
 399 #define SH4A_PCIEPCICONF11      (0x04002C)      /* R/W R/W 0x0000 0000 8/16/32 */
 400 #define SH4A_PCIEPCICONF12      (0x040030)      /* R/W R/W 0x0000 0000 8/16/32 */
 401 #define SH4A_PCIEPCICONF13      (0x040034)      /* R/W R/W 0x0000 0040 8/16/32 */
 402 #define SH4A_PCIEPCICONF14      (0x040038)      /* R/W R/W 0x0000 0000 8/16/32 */
 403 #define SH4A_PCIEPCICONF15      (0x04003C)      /* R/W R/W 0x0000 00FF 8/16/32 */
 404 #define SH4A_PCIEPMCAP0         (0x040040)      /* R/W R 0x0003 5001 8/16/32 */
 405 #define SH4A_PCIEPMCAP1         (0x040044)      /* R/W R/W 0x0000 0000 8/16/32 */
 406 #define SH4A_PCIEMSICAP0        (0x040050)      /* R/W R/W 0x0180 7005 8/16/32 */
 407 #define SH4A_PCIEMSICAP1        (0x040054)      /* R/W R/W 0x0000 0000 8/16/32 */
 408 #define SH4A_PCIEMSICAP2        (0x040058)      /* R/W R/W 0x0000 0000 8/16/32 */
 409 #define SH4A_PCIEMSICAP3        (0x04005C)      /* R/W R/W 0x0000 0000 8/16/32 */
 410 #define SH4A_PCIEMSICAP4        (0x040060)      /* R/W R/W 0x0000 0000 8/16/32 */
 411 #define SH4A_PCIEMSICAP5        (0x040064)      /* R/W R/W 0x0000 0000 8/16/32 */
 412 #define SH4A_PCIEEXPCAP0        (0x040070)      /* R/W R/W 0x0001 0010 8/16/32 */
 413 #define SH4A_PCIEEXPCAP1        (0x040074)      /* R/W R 0x0000 0005 8/16/32 */
 414 #define SH4A_PCIEEXPCAP2        (0x040078)      /* R/W R/W 0x0000 0801 8/16/32 */
 415 #define SH4A_PCIEEXPCAP3        (0x04007C)      /* R/W R 0x0003 F421 8/16/32 */
 416 #define SH4A_PCIEEXPCAP4        (0x040080)      /* R/W R/W 0x0041 0000 8/16/32 */
 417 #define SH4A_PCIEEXPCAP5        (0x040084)      /* R/W R/W 0x0000 0000 8/16/32 */
 418 #define SH4A_PCIEEXPCAP6        (0x040088)      /* R/W R/W 0x0000 03C0 8/16/32 */
 419 #define SH4A_PCIEEXPCAP7        (0x04008C)      /* R/W R/W 0x0000 0000 8/16/32 */
 420 #define SH4A_PCIEEXPCAP8        (0x040090)      /* R/W R/W 0x0000 0000 8/16/32 */
 421 #define SH4A_PCIEVCCAP0         (0x040100)      /* R/W R 0x1B01 0002 8/16/32 */
 422 #define SH4A_PCIEVCCAP1         (0x040104)      /* R R 0x0000 0001 8/16/32 */
 423 #define SH4A_PCIEVCCAP2         (0x040108)      /* R R 0x0000 0000 8/16/32 */
 424 #define SH4A_PCIEVCCAP3         (0x04010C)      /* R R/W 0x0000 0000 8/16/32 */
 425 #define SH4A_PCIEVCCAP4         (0x040110)      /* R/W R/W 0x0000 0000 8/16/32 */
 426 #define SH4A_PCIEVCCAP5         (0x040114)      /* R/W R/W 0x8000 00FF 8/16/32 */
 427 #define SH4A_PCIEVCCAP6         (0x040118)      /* R/W R 0x0002 0000 8/16/32 */
 428 #define SH4A_PCIEVCCAP7         (0x04011C)      /* R/W R/W 0x0000 0000 8/16/32 */
 429 #define SH4A_PCIEVCCAP8         (0x040120)      /* R/W R/W 0x0000 0000 8/16/32 */
 430 #define SH4A_PCIEVCCAP9         (0x040124)      /* R/W R 0x0002 0000 8/16/32 */
 431 #define SH4A_PCIENUMCAP0        (0x0001B0)      /* RW R 0x0001 0003 8/16/32 */
 432 #define SH4A_PCIENUMCAP1        (0x0001B4)      /* R R 0x0000 0000 8/16/32 */
 433 #define SH4A_PCIENUMCAP2        (0x0001B8)      /* R R 0x0000 0000 8/16/32 */
 434 #define SH4A_PCIEIDSETR0        (0x041000)      /* R/W R 0x0000 FFFF 16/32 */
 435 #define SH4A_PCIEIDSETR1        (0x041004)      /* R/W R 0xFF00 0000 16/32 */
 436 #define SH4A_PCIEBAR0SETR       (0x041008)      /* R/W R 0x0000 0000 16/32 */
 437 #define SH4A_PCIEBAR1SETR       (0x04100C)      /* R/W R 0x0000 0000 16/32 */
 438 #define SH4A_PCIEBAR2SETR       (0x041010)      /* R/W R 0x0000 0000 16/32 */
 439 #define SH4A_PCIEBAR3SETR       (0x041014)      /* R/W R 0x0000 0000 16/32 */
 440 #define SH4A_PCIEBAR4SETR       (0x041018)      /* R/W R 0x0000 0000 16/32 */
 441 #define SH4A_PCIEBAR5SETR       (0x04101C)      /* R/W R 0x0000 0000 16/32 */
 442 #define SH4A_PCIECISSETR        (0x041020)      /* R/W R 0x0000 0000 16/32 */
 443 #define SH4A_PCIEIDSETR2        (0x041024)      /* R/W R 0x0000 0000 16/32 */
 444 #define SH4A_PCIEEROMSETR       (0x041028)      /* R/W R 0x0000 0000 16/32 */
 445 #define SH4A_PCIEDSERSETR0      (0x04102C)      /* R/W R 0x0000 0000 16/32 */
 446 #define SH4A_PCIEDSERSETR1      (0x041030)      /* R/W R 0x0000 0000 16/32 */
 447 #define SH4A_PCIECTLR           (0x041040)      /* R/W R 0x0000 0000 16/32 */
 448 #define SH4A_PCIETLSR           (0x041044)      /* R/W1C R 0x0000 0000 16/32 */
 449 #define SH4A_PCIETLCTLR         (0x041048)      /* R/W R 0x0000 0000 16/32 */
 450 #define SH4A_PCIEDLSR           (0x04104C)      /* R/W1C R 0x4003 0000 16/32 */
 451 #define SH4A_PCIEDLCTLR         (0x041050)      /* R R 0x0000 0000 16/32 */
 452 #define SH4A_PCIEMACSR          (0x041054)      /* R/W1C R 0x0041 0000 16/32 */
 453 #define SH4A_PCIEMACCTLR        (0x041058)      /* R/W R 0x0000 0000 16/32 */
 454 #define         PCIEMACCTLR_SCR_DIS     (1 << 27)       /* scramble disable */
 455 #define SH4A_PCIEPMSTR          (0x04105C)      /* R/W1C R 0x0000 0000 16/32 */
 456 #define SH4A_PCIEPMCTLR         (0x041060)      /* R/W R 0x0000 0000 16/32 */
 457 #define SH4A_PCIETLINTENR       (0x041064)      /* R/W R 0x0000 0000 16/32 */
 458 #define SH4A_PCIEDLINTENR       (0x041068)      /* R/W R 0x0000 0000 16/32 */
 459 #define         PCIEDLINTENR_DLL_ACT_ENABLE     (1 << 31) /* DL active irq */
 460 #define SH4A_PCIEMACINTENR      (0x04106C)      /* R/W R 0x0000 0000 16/32 */
 461 #define SH4A_PCIEPMINTENR       (0x041070)      /* R/W R 0x0000 0000 16/32 */
 462 #define SH4A_PCIETXDCTLR        (0x044000)      /* R/W - H'00000000_00000000 32/64 */
 463 #define SH4A_PCIETXCTLR         (0x044020)      /* R/W - H'00000000_00000000 32/64 */
 464 #define SH4A_PCIETXSR           (0x044028)      /* R - H'00000000_00000000 32/64 */
 465 #define SH4A_PCIETXVC0DCTLR     (0x044100)      /* R/W - H'00000000_00000000 32/64 */
 466 #define SH4A_PCIETXVC0SR        (0x044108)      /* R/W - H'00888000_00000000 32/64 */
 467 #define SH4A_PCIEVC0PDTXR       (0x044110)      /* W - H'00000000_00000000 32/64 */
 468 #define SH4A_PCIEVC0PHTXR       (0x044118)      /* W - H'00000000_00000000 32/64 */
 469 #define SH4A_PCIEVC0NPDTXR      (0x044120)      /* W - H'00000000_00000000 32/64 */
 470 #define SH4A_PCIEVC0NPHTXR      (0x044128)      /* W - H'00000000_00000000 32/64 */
 471 #define SH4A_PCIEVC0CDTXR       (0x044130)      /* W - H'00000000_00000000 32/64 */
 472 #define SH4A_PCIEVC0CHTXR       (0x044138)      /* W - H'00000000_00000000 32/64 */
 473 #define SH4A_PCIETXVCXDCTLR     (0x044200)      /* R/W - H'00000000_00000000 32/64 */
 474 #define SH4A_PCIETXVCXSR        (0x044208)      /* R/W - H'00000000_00000000 32/64 */
 475 #define SH4A_PCIEVCXPDTXR       (0x044210)      /* W - H'00000000_00000000 32/64 */
 476 #define SH4A_PCIEVCXPHTXR       (0x044218)      /* W - H'00000000_00000000 32/64 */
 477 #define SH4A_PCIEVCXNPDTXR      (0x044220)      /* W - H'00000000_00000000 32/64 */
 478 #define SH4A_PCIEVCXNPHTXR      (0x044228)      /* W - H'00000000_00000000 32/64 */
 479 #define SH4A_PCIEVCXCDTXR       (0x044230)      /* W - H'00000000_00000000 32/64 */
 480 #define SH4A_PCIEVCXCHTXR       (0x044238)      /* W - H'00000000_00000000 32/64 */
 481 #define SH4A_PCIERDCTLR         (0x046000)      /* RW - H'00000000_00000000 32/64 */
 482 #define SH4A_PCIEERPCTLR        (0x046008)      /* RW - H'00000000_00000000 32/64 */
 483 #define SH4A_PCIEERPHR          (0x046010)      /* R - H'00000000_00000000 32/64 */
 484 #define SH4A_PCIEERPERR         (0x046018)      /* R - H'00000000_00000000 32/64 */
 485 #define SH4A_PCIERXVC0DCTLR     (0x046100)      /* RW - H'00000000_00000000 32/64 */
 486 #define SH4A_PCIERXVC0SR        (0x046108)      /* RW - H'00000000_00000000 32/64 */
 487 #define SH4A_PCIEVC0PDRXR       (0x046140)      /* R - H'00000000_00000000 32/64 */
 488 #define SH4A_PCIEVC0PHRXR       (0x046148)      /* R - H'00000000_00000000 32/64 */
 489 #define SH4A_PCIEVC0PERR        (0x046150)      /* R - H'00000000_00000000 32/64 */
 490 #define SH4A_PCIEVC0NPDRXR      (0x046158)      /* R - H'00000000_00000000 32/64 */
 491 #define SH4A_PCIEVC0NPHRXR      (0x046160)      /* R - H'00000000_00000000 32/64 */
 492 #define SH4A_PCIEVC0NPERR       (0x046168)      /* R - H'00000000_00000000 32/64 */
 493 #define SH4A_PCIEVC0CDRXR       (0x046170)      /* R - H'00000000_00000000 32/64 */
 494 #define SH4A_PCIEVC0CHRXR       (0x046178)      /* R - H'00000000_00000000 32/64 */
 495 #define SH4A_PCIEVC0CERR        (0x046180)      /* R - H'00000000_00000000 32/64 */
 496 #define SH4A_PCIERXVCXDCTLR     (0x046200)      /* RW - H'00000000_00000000 32/64 */
 497 #define SH4A_PCIERXVCXSR        (0x046208)      /* RW - H'00000000_00000000 32/64 */
 498 #define SH4A_PCIEVCXPDRXR       (0x046240)      /* R - H'00000000_00000000 32/64 */
 499 #define SH4A_PCIEVCXPHRXR       (0x046248)      /* R H'00000000_00000000 32/64 */
 500 #define SH4A_PCIEVCXPERR        (0x046250)      /* R H'00000000_00000000 32/64 */
 501 #define SH4A_PCIEVCXNPDRXR      (0x046258)      /* R H'00000000_00000000 32/64 */
 502 #define SH4A_PCIEVCXNPHRXR      (0x046260)      /* R H'00000000_00000000 32/64 */
 503 #define SH4A_PCIEVCXNPERR       (0x046268)      /* R H'00000000_00000000 32/64 */
 504 #define SH4A_PCIEVCXCDRXR       (0x046270)      /* R H'00000000_00000000 32/64 */
 505 #define SH4A_PCIEVCXCHRXR       (0x046278)      /* R H'00000000_00000000 32/64 */
 506 #define SH4A_PCIEVCXCERR        (0x046280)      /* R H'00000000_00000000 32/64 */
 507
 508 #define SH4A_PCI_SSI_BASE       0xFFE00000      /* spw config address   */
 509 #define SH4A_PCI_SSI_BASE_LEN   0x00100000      /* 1MB                  */
 510
 511 #define SH4A_SSICR0             (0x000000)
 512 #define SH4A_SSICR1             (0x010000)
 513 #define SH4A_SSICR2             (0x020000)
 514 #define SH4A_SSICR3             (0x030000)
 515
 516 #define PCI_REG(x)              ((x) + 0x40000)
 517
 518 static inline void
 519 pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
 520 {
 521         __raw_writel(val, chan->reg_base + reg);
 522 }
 523
 524 static inline unsigned long
 525 pci_read_reg(struct pci_channel *chan, unsigned long reg)
 526 {
 527         return __raw_readl(chan->reg_base + reg);
 528 }
 529
 530 #endif /* __PCI_SH7786_H */