release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/drivers/dma/dma-sh.c

   1 /*
   2  * arch/sh/drivers/dma/dma-sh.c
   3  *
   4  * SuperH On-chip DMAC Support
   5  *
   6  * Copyright (C) 2000 Takashi YOSHII
   7  * Copyright (C) 2003, 2004 Paul Mundt
   8  * Copyright (C) 2005 Andriy Skulysh
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <mach-dreamcast/mach/dma.h>
  18 #include <asm/dma.h>
  19 #include <asm/io.h>
  20 #include <asm/dma-sh.h>
  21
  22 #if defined(DMAE1_IRQ)
  23 #define NR_DMAE         2
  24 #else
  25 #define NR_DMAE         1
  26 #endif
  27
  28 static const char *dmae_name[] = {
  29         "DMAC Address Error0", "DMAC Address Error1"
  30 };
  31
  32 static inline unsigned int get_dmte_irq(unsigned int chan)
  33 {
  34         unsigned int irq = 0;
  35         if (chan < ARRAY_SIZE(dmte_irq_map))
  36                 irq = dmte_irq_map[chan];
  37
  38 #if defined(CONFIG_SH_DMA_IRQ_MULTI)
  39         if (irq > DMTE6_IRQ)
  40                 return DMTE6_IRQ;
  41         return DMTE0_IRQ;
  42 #else
  43         return irq;
  44 #endif
  45 }
  46
  47 /*
  48  * We determine the correct shift size based off of the CHCR transmit size
  49  * for the given channel. Since we know that it will take:
  50  *
  51  *      info->count >> ts_shift[transmit_size]
  52  *
  53  * iterations to complete the transfer.
  54  */
  55 static unsigned int ts_shift[] = TS_SHIFT;
  56 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  57 {
  58         u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
  59         int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
  60                 ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
  61
  62         return ts_shift[cnt];
  63 }
  64
  65 /*
  66  * The transfer end interrupt must read the chcr register to end the
  67  * hardware interrupt active condition.
  68  * Besides that it needs to waken any waiting process, which should handle
  69  * setting up the next transfer.
  70  */
  71 static irqreturn_t dma_tei(int irq, void *dev_id)
  72 {
  73         struct dma_channel *chan = dev_id;
  74         u32 chcr;
  75
  76         chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
  77
  78         if (!(chcr & CHCR_TE))
  79                 return IRQ_NONE;
  80
  81         chcr &= ~(CHCR_IE | CHCR_DE);
  82         __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
  83
  84         wake_up(&chan->wait_queue);
  85
  86         return IRQ_HANDLED;
  87 }
  88
  89 static int sh_dmac_request_dma(struct dma_channel *chan)
  90 {
  91         if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
  92                 return 0;
  93
  94         return request_irq(get_dmte_irq(chan->chan), dma_tei,
  95 #if defined(CONFIG_SH_DMA_IRQ_MULTI)
  96                                 IRQF_SHARED,
  97 #else
  98                                 IRQF_DISABLED,
  99 #endif
 100                                 chan->dev_id, chan);
 101 }
 102
 103 static void sh_dmac_free_dma(struct dma_channel *chan)
 104 {
 105         free_irq(get_dmte_irq(chan->chan), chan);
 106 }
 107
 108 static int
 109 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
 110 {
 111         if (!chcr)
 112                 chcr = RS_DUAL | CHCR_IE;
 113
 114         if (chcr & CHCR_IE) {
 115                 chcr &= ~CHCR_IE;
 116                 chan->flags |= DMA_TEI_CAPABLE;
 117         } else {
 118                 chan->flags &= ~DMA_TEI_CAPABLE;
 119         }
 120
 121         __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 122
 123         chan->flags |= DMA_CONFIGURED;
 124         return 0;
 125 }
 126
 127 static void sh_dmac_enable_dma(struct dma_channel *chan)
 128 {
 129         int irq;
 130         u32 chcr;
 131
 132         chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
 133         chcr |= CHCR_DE;
 134
 135         if (chan->flags & DMA_TEI_CAPABLE)
 136                 chcr |= CHCR_IE;
 137
 138         __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 139
 140         if (chan->flags & DMA_TEI_CAPABLE) {
 141                 irq = get_dmte_irq(chan->chan);
 142                 enable_irq(irq);
 143         }
 144 }
 145
 146 static void sh_dmac_disable_dma(struct dma_channel *chan)
 147 {
 148         int irq;
 149         u32 chcr;
 150
 151         if (chan->flags & DMA_TEI_CAPABLE) {
 152                 irq = get_dmte_irq(chan->chan);
 153                 disable_irq(irq);
 154         }
 155
 156         chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
 157         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 158         __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 159 }
 160
 161 static int sh_dmac_xfer_dma(struct dma_channel *chan)
 162 {
 163         /*
 164          * If we haven't pre-configured the channel with special flags, use
 165          * the defaults.
 166          */
 167         if (unlikely(!(chan->flags & DMA_CONFIGURED)))
 168                 sh_dmac_configure_channel(chan, 0);
 169
 170         sh_dmac_disable_dma(chan);
 171
 172         /*
 173          * Single-address mode usage note!
 174          *
 175          * It's important that we don't accidentally write any value to SAR/DAR
 176          * (this includes 0) that hasn't been directly specified by the user if
 177          * we're in single-address mode.
 178          *
 179          * In this case, only one address can be defined, anything else will
 180          * result in a DMA address error interrupt (at least on the SH-4),
 181          * which will subsequently halt the transfer.
 182          *
 183          * Channel 2 on the Dreamcast is a special case, as this is used for
 184          * cascading to the PVR2 DMAC. In this case, we still need to write
 185          * SAR and DAR, regardless of value, in order for cascading to work.
 186          */
 187         if (chan->sar || (mach_is_dreamcast() &&
 188                           chan->chan == PVR2_CASCADE_CHAN))
 189                 __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
 190         if (chan->dar || (mach_is_dreamcast() &&
 191                           chan->chan == PVR2_CASCADE_CHAN))
 192                 __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
 193
 194         __raw_writel(chan->count >> calc_xmit_shift(chan),
 195                 (dma_base_addr[chan->chan] + TCR));
 196
 197         sh_dmac_enable_dma(chan);
 198
 199         return 0;
 200 }
 201
 202 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 203 {
 204         if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
 205                 return 0;
 206
 207         return __raw_readl(dma_base_addr[chan->chan] + TCR)
 208                  << calc_xmit_shift(chan);
 209 }
 210
 211 static inline int dmaor_reset(int no)
 212 {
 213         unsigned long dmaor = dmaor_read_reg(no);
 214
 215         /* Try to clear the error flags first, incase they are set */
 216         dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
 217         dmaor_write_reg(no, dmaor);
 218
 219         dmaor |= DMAOR_INIT;
 220         dmaor_write_reg(no, dmaor);
 221
 222         /* See if we got an error again */
 223         if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
 224                 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
 225                 return -EINVAL;
 226         }
 227
 228         return 0;
 229 }
 230
 231 #if defined(CONFIG_CPU_SH4)
 232 static irqreturn_t dma_err(int irq, void *dummy)
 233 {
 234 #if defined(CONFIG_SH_DMA_IRQ_MULTI)
 235         int cnt = 0;
 236         switch (irq) {
 237 #if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
 238         case DMTE6_IRQ:
 239                 cnt++;
 240 #endif
 241         case DMTE0_IRQ:
 242                 if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
 243                         disable_irq(irq);
 244                         /* DMA multi and error IRQ */
 245                         return IRQ_HANDLED;
 246                 }
 247         default:
 248                 return IRQ_NONE;
 249         }
 250 #else
 251         dmaor_reset(0);
 252 #if defined(CONFIG_CPU_SUBTYPE_SH7723)  || defined(CONFIG_CPU_SUBTYPE_SH7780)   || \
 253         defined(CONFIG_CPU_SUBTYPE_SH7785)
 254         dmaor_reset(1);
 255 #endif
 256         disable_irq(irq);
 257
 258         return IRQ_HANDLED;
 259 #endif
 260 }
 261 #endif
 262
 263 static struct dma_ops sh_dmac_ops = {
 264         .request        = sh_dmac_request_dma,
 265         .free           = sh_dmac_free_dma,
 266         .get_residue    = sh_dmac_get_dma_residue,
 267         .xfer           = sh_dmac_xfer_dma,
 268         .configure      = sh_dmac_configure_channel,
 269 };
 270
 271 static struct dma_info sh_dmac_info = {
 272         .name           = "sh_dmac",
 273         .nr_channels    = CONFIG_NR_ONCHIP_DMA_CHANNELS,
 274         .ops            = &sh_dmac_ops,
 275         .flags          = DMAC_CHANNELS_TEI_CAPABLE,
 276 };
 277
 278 #ifdef CONFIG_CPU_SH4
 279 static unsigned int get_dma_error_irq(int n)
 280 {
 281 #if defined(CONFIG_SH_DMA_IRQ_MULTI)
 282         return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
 283 #else
 284         return (n == 0) ? DMAE0_IRQ :
 285 #if defined(DMAE1_IRQ)
 286                                 DMAE1_IRQ;
 287 #else
 288                                 -1;
 289 #endif
 290 #endif
 291 }
 292 #endif
 293
 294 static int __init sh_dmac_init(void)
 295 {
 296         struct dma_info *info = &sh_dmac_info;
 297         int i;
 298
 299 #ifdef CONFIG_CPU_SH4
 300         int n;
 301
 302         for (n = 0; n < NR_DMAE; n++) {
 303                 i = request_irq(get_dma_error_irq(n), dma_err,
 304 #if defined(CONFIG_SH_DMA_IRQ_MULTI)
 305                                 IRQF_SHARED,
 306 #else
 307                                 IRQF_DISABLED,
 308 #endif
 309                                 dmae_name[n], (void *)dmae_name[n]);
 310                 if (unlikely(i < 0)) {
 311                         printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
 312                         return i;
 313                 }
 314         }
 315 #endif /* CONFIG_CPU_SH4 */
 316
 317         /*
 318          * Initialize DMAOR, and clean up any error flags that may have
 319          * been set.
 320          */
 321         i = dmaor_reset(0);
 322         if (unlikely(i != 0))
 323                 return i;
 324 #if defined(CONFIG_CPU_SUBTYPE_SH7723)  || defined(CONFIG_CPU_SUBTYPE_SH7780)   || \
 325         defined(CONFIG_CPU_SUBTYPE_SH7785)
 326         i = dmaor_reset(1);
 327         if (unlikely(i != 0))
 328                 return i;
 329 #endif
 330
 331         return register_dmac(info);
 332 }
 333
 334 static void __exit sh_dmac_exit(void)
 335 {
 336 #ifdef CONFIG_CPU_SH4
 337         int n;
 338
 339         for (n = 0; n < NR_DMAE; n++) {
 340                 free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
 341         }
 342 #endif /* CONFIG_CPU_SH4 */
 343         unregister_dmac(&sh_dmac_info);
 344 }
 345
 346 subsys_initcall(sh_dmac_init);
 347 module_exit(sh_dmac_exit);
 348
 349 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
 350 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
 351 MODULE_LICENSE("GPL");