release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/platforms/52xx/media5200.c

   1 /*
   2  * Support for 'media5200-platform' compatible boards.
   3  *
   4  * Copyright (C) 2008 Secret Lab Technologies Ltd.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Description:
  12  * This code implements support for the Freescape Media5200 platform
  13  * (built around the MPC5200 SoC).
  14  *
  15  * Notable characteristic of the Media5200 is the presence of an FPGA
  16  * that has all external IRQ lines routed through it.  This file implements
  17  * a cascaded interrupt controller driver which attaches itself to the
  18  * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
  19  * is initialized.
  20  *
  21  */
  22
  23 #undef DEBUG
  24
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <asm/time.h>
  29 #include <asm/prom.h>
  30 #include <asm/machdep.h>
  31 #include <asm/mpc52xx.h>
  32
  33 static struct of_device_id mpc5200_gpio_ids[] __initdata = {
  34         { .compatible = "fsl,mpc5200-gpio", },
  35         { .compatible = "mpc5200-gpio", },
  36         {}
  37 };
  38
  39 /* FPGA register set */
  40 #define MEDIA5200_IRQ_ENABLE (0x40c)
  41 #define MEDIA5200_IRQ_STATUS (0x410)
  42 #define MEDIA5200_NUM_IRQS   (6)
  43 #define MEDIA5200_IRQ_SHIFT  (32 - MEDIA5200_NUM_IRQS)
  44
  45 struct media5200_irq {
  46         void __iomem *regs;
  47         spinlock_t lock;
  48         struct irq_host *irqhost;
  49 };
  50 struct media5200_irq media5200_irq;
  51
  52 static void media5200_irq_unmask(unsigned int virq)
  53 {
  54         unsigned long flags;
  55         u32 val;
  56
  57         spin_lock_irqsave(&media5200_irq.lock, flags);
  58         val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  59         val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
  60         out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  61         spin_unlock_irqrestore(&media5200_irq.lock, flags);
  62 }
  63
  64 static void media5200_irq_mask(unsigned int virq)
  65 {
  66         unsigned long flags;
  67         u32 val;
  68
  69         spin_lock_irqsave(&media5200_irq.lock, flags);
  70         val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  71         val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
  72         out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  73         spin_unlock_irqrestore(&media5200_irq.lock, flags);
  74 }
  75
  76 static struct irq_chip media5200_irq_chip = {
  77         .name = "Media5200 FPGA",
  78         .unmask = media5200_irq_unmask,
  79         .mask = media5200_irq_mask,
  80         .mask_ack = media5200_irq_mask,
  81 };
  82
  83 void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
  84 {
  85         int sub_virq, val;
  86         u32 status, enable;
  87
  88         /* Mask off the cascaded IRQ */
  89         raw_spin_lock(&desc->lock);
  90         desc->chip->mask(virq);
  91         raw_spin_unlock(&desc->lock);
  92
  93         /* Ask the FPGA for IRQ status.  If 'val' is 0, then no irqs
  94          * are pending.  'ffs()' is 1 based */
  95         status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  96         enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
  97         val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
  98         if (val) {
  99                 sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
 100                 /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
 101                  *          __func__, virq, status, enable, val - 1, sub_virq);
 102                  */
 103                 generic_handle_irq(sub_virq);
 104         }
 105
 106         /* Processing done; can reenable the cascade now */
 107         raw_spin_lock(&desc->lock);
 108         desc->chip->ack(virq);
 109         if (!(desc->status & IRQ_DISABLED))
 110                 desc->chip->unmask(virq);
 111         raw_spin_unlock(&desc->lock);
 112 }
 113
 114 static int media5200_irq_map(struct irq_host *h, unsigned int virq,
 115                              irq_hw_number_t hw)
 116 {
 117         struct irq_desc *desc = irq_to_desc(virq);
 118
 119         pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
 120         set_irq_chip_data(virq, &media5200_irq);
 121         set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
 122         set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
 123         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 124         desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
 125
 126         return 0;
 127 }
 128
 129 static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
 130                                  const u32 *intspec, unsigned int intsize,
 131                                  irq_hw_number_t *out_hwirq,
 132                                  unsigned int *out_flags)
 133 {
 134         if (intsize != 2)
 135                 return -1;
 136
 137         pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
 138         *out_hwirq = intspec[1];
 139         *out_flags = IRQ_TYPE_NONE;
 140         return 0;
 141 }
 142
 143 static struct irq_host_ops media5200_irq_ops = {
 144         .map = media5200_irq_map,
 145         .xlate = media5200_irq_xlate,
 146 };
 147
 148 /*
 149  * Setup Media5200 IRQ mapping
 150  */
 151 static void __init media5200_init_irq(void)
 152 {
 153         struct device_node *fpga_np;
 154         int cascade_virq;
 155
 156         /* First setup the regular MPC5200 interrupt controller */
 157         mpc52xx_init_irq();
 158
 159         /* Now find the FPGA IRQ */
 160         fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
 161         if (!fpga_np)
 162                 goto out;
 163         pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
 164
 165         media5200_irq.regs = of_iomap(fpga_np, 0);
 166         if (!media5200_irq.regs)
 167                 goto out;
 168         pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
 169
 170         cascade_virq = irq_of_parse_and_map(fpga_np, 0);
 171         if (!cascade_virq)
 172                 goto out;
 173         pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
 174
 175         /* Disable all FPGA IRQs */
 176         out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
 177
 178         spin_lock_init(&media5200_irq.lock);
 179
 180         media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
 181                                                MEDIA5200_NUM_IRQS,
 182                                                &media5200_irq_ops, -1);
 183         if (!media5200_irq.irqhost)
 184                 goto out;
 185         pr_debug("%s: allocated irqhost\n", __func__);
 186
 187         media5200_irq.irqhost->host_data = &media5200_irq;
 188
 189         set_irq_data(cascade_virq, &media5200_irq);
 190         set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
 191
 192         return;
 193
 194  out:
 195         pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
 196 }
 197
 198 /*
 199  * Setup the architecture
 200  */
 201 static void __init media5200_setup_arch(void)
 202 {
 203
 204         struct device_node *np;
 205         struct mpc52xx_gpio __iomem *gpio;
 206         u32 port_config;
 207
 208         if (ppc_md.progress)
 209                 ppc_md.progress("media5200_setup_arch()", 0);
 210
 211         /* Map important registers from the internal memory map */
 212         mpc52xx_map_common_devices();
 213
 214         /* Some mpc5200 & mpc5200b related configuration */
 215         mpc5200_setup_xlb_arbiter();
 216
 217         mpc52xx_setup_pci();
 218
 219         np = of_find_matching_node(NULL, mpc5200_gpio_ids);
 220         gpio = of_iomap(np, 0);
 221         of_node_put(np);
 222         if (!gpio) {
 223                 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
 224                        __func__);
 225                 return;
 226         }
 227
 228         /* Set port config */
 229         port_config = in_be32(&gpio->port_config);
 230
 231         port_config &= ~0x03000000;     /* ATA CS is on csb_4/5         */
 232         port_config |=  0x01000000;
 233
 234         out_be32(&gpio->port_config, port_config);
 235
 236         /* Unmap zone */
 237         iounmap(gpio);
 238
 239 }
 240
 241 /* list of the supported boards */
 242 static char *board[] __initdata = {
 243         "fsl,media5200",
 244         NULL
 245 };
 246
 247 /*
 248  * Called very early, MMU is off, device-tree isn't unflattened
 249  */
 250 static int __init media5200_probe(void)
 251 {
 252         unsigned long node = of_get_flat_dt_root();
 253         int i = 0;
 254
 255         while (board[i]) {
 256                 if (of_flat_dt_is_compatible(node, board[i]))
 257                         break;
 258                 i++;
 259         }
 260
 261         return (board[i] != NULL);
 262 }
 263
 264 define_machine(media5200_platform) {
 265         .name           = "media5200-platform",
 266         .probe          = media5200_probe,
 267         .setup_arch     = media5200_setup_arch,
 268         .init           = mpc52xx_declare_of_platform_devices,
 269         .init_IRQ       = media5200_init_irq,
 270         .get_irq        = mpc52xx_get_irq,
 271         .restart        = mpc52xx_restart,
 272         .calibrate_decr = generic_calibrate_decr,
 273 };