2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/of_address.h>
26 #include <linux/list.h>
27 #include <linux/syscalls.h>
28 #include <linux/irq.h>
29 #include <linux/vmalloc.h>
30 #include <linux/slab.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
42 static DEFINE_SPINLOCK(hose_spinlock
);
45 static int global_phb_number
; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base
;
50 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
51 unsigned int ppc_pci_flags
= 0;
54 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
56 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
58 pci_dma_ops
= dma_ops
;
61 struct dma_map_ops
*get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops
);
67 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
69 struct pci_controller
*phb
;
71 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
74 spin_lock(&hose_spinlock
);
75 phb
->global_number
= global_phb_number
++;
76 list_add_tail(&phb
->list_node
, &hose_list
);
77 spin_unlock(&hose_spinlock
);
79 phb
->is_dynamic
= mem_init_done
;
82 int nid
= of_node_to_nid(dev
);
84 if (nid
< 0 || !node_online(nid
))
87 PHB_SET_NODE(phb
, nid
);
93 void pcibios_free_controller(struct pci_controller
*phb
)
95 spin_lock(&hose_spinlock
);
96 list_del(&phb
->list_node
);
97 spin_unlock(&hose_spinlock
);
103 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
106 return hose
->pci_io_size
;
108 return hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
112 int pcibios_vaddr_is_ioport(void __iomem
*address
)
115 struct pci_controller
*hose
;
116 resource_size_t size
;
118 spin_lock(&hose_spinlock
);
119 list_for_each_entry(hose
, &hose_list
, list_node
) {
120 size
= pcibios_io_size(hose
);
121 if (address
>= hose
->io_base_virt
&&
122 address
< (hose
->io_base_virt
+ size
)) {
127 spin_unlock(&hose_spinlock
);
131 unsigned long pci_address_to_pio(phys_addr_t address
)
133 struct pci_controller
*hose
;
134 resource_size_t size
;
135 unsigned long ret
= ~0;
137 spin_lock(&hose_spinlock
);
138 list_for_each_entry(hose
, &hose_list
, list_node
) {
139 size
= pcibios_io_size(hose
);
140 if (address
>= hose
->io_base_phys
&&
141 address
< (hose
->io_base_phys
+ size
)) {
143 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
144 ret
= base
+ (address
- hose
->io_base_phys
);
148 spin_unlock(&hose_spinlock
);
152 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
155 * Return the domain number for this bus.
157 int pci_domain_nr(struct pci_bus
*bus
)
159 struct pci_controller
*hose
= pci_bus_to_host(bus
);
161 return hose
->global_number
;
163 EXPORT_SYMBOL(pci_domain_nr
);
165 /* This routine is meant to be used early during boot, when the
166 * PCI bus numbers have not yet been assigned, and you need to
167 * issue PCI config cycles to an OF device.
168 * It could also be used to "fix" RTAS config cycles if you want
169 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
172 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
175 struct pci_controller
*hose
, *tmp
;
176 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
177 if (hose
->dn
== node
)
184 static ssize_t
pci_show_devspec(struct device
*dev
,
185 struct device_attribute
*attr
, char *buf
)
187 struct pci_dev
*pdev
;
188 struct device_node
*np
;
190 pdev
= to_pci_dev (dev
);
191 np
= pci_device_to_OF_node(pdev
);
192 if (np
== NULL
|| np
->full_name
== NULL
)
194 return sprintf(buf
, "%s", np
->full_name
);
196 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
198 /* Add sysfs properties */
199 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
201 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
204 char __devinit
*pcibios_setup(char *str
)
210 * Reads the interrupt pin to determine if interrupt is use by card.
211 * If the interrupt is used, then gets the interrupt line from the
212 * openfirmware and sets it in the pci_dev and pci_config line.
214 int pci_read_irq_line(struct pci_dev
*pci_dev
)
219 /* The current device-tree that iSeries generates from the HV
220 * PCI informations doesn't contain proper interrupt routing,
221 * and all the fallback would do is print out crap, so we
222 * don't attempt to resolve the interrupts here at all, some
223 * iSeries specific fixup does it.
225 * In the long run, we will hopefully fix the generated device-tree
228 #ifdef CONFIG_PPC_ISERIES
229 if (firmware_has_feature(FW_FEATURE_ISERIES
))
233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
236 memset(&oirq
, 0xff, sizeof(oirq
));
238 /* Try to get a mapping from the device-tree */
239 if (of_irq_map_pci(pci_dev
, &oirq
)) {
242 /* If that fails, lets fallback to what is in the config
243 * space and map that through the default controller. We
244 * also set the type to level low since that's what PCI
245 * interrupts are. If your platform does differently, then
246 * either provide a proper interrupt tree or don't use this
249 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
253 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
254 line
== 0xff || line
== 0) {
257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
260 virq
= irq_create_mapping(NULL
, line
);
262 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
265 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
266 oirq
.controller
? oirq
.controller
->full_name
:
269 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
273 pr_debug(" Failed to map !\n");
277 pr_debug(" Mapped to linux irq %d\n", virq
);
283 EXPORT_SYMBOL(pci_read_irq_line
);
286 * Platform support for /proc/bus/pci/X/Y mmap()s,
287 * modelled on the sparc64 implementation by Dave Miller.
291 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
292 resource_size_t
*offset
,
293 enum pci_mmap_state mmap_state
)
295 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
296 unsigned long io_offset
= 0;
300 return NULL
; /* should never happen */
302 /* If memory, add on the PCI bridge address offset */
303 if (mmap_state
== pci_mmap_mem
) {
304 res_bit
= IORESOURCE_MEM
;
306 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
307 *offset
+= io_offset
;
308 res_bit
= IORESOURCE_IO
;
312 * Check that the offset requested corresponds to one of the
313 * resources of the device.
315 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
316 struct resource
*rp
= &dev
->resource
[i
];
317 int flags
= rp
->flags
;
319 /* treat ROM as memory (should be already) */
320 if (i
== PCI_ROM_RESOURCE
)
321 flags
|= IORESOURCE_MEM
;
323 /* Active and same type? */
324 if ((flags
& res_bit
) == 0)
327 /* In the range of this resource? */
328 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
331 /* found it! construct the final physical address */
332 if (mmap_state
== pci_mmap_io
)
333 *offset
+= hose
->io_base_phys
- io_offset
;
341 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
344 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
346 enum pci_mmap_state mmap_state
,
349 unsigned long prot
= pgprot_val(protection
);
351 if (mmap_state
!= pci_mmap_mem
)
353 else if (write_combine
== 0) {
354 if (rp
->flags
& IORESOURCE_PREFETCH
)
359 return pgprot_noncached_wc(prot
);
361 return pgprot_noncached(prot
);
365 * This one is used by /dev/mem and fbdev who have no clue about the
366 * PCI device, it tries to find the PCI device first and calls the
369 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
374 struct pci_dev
*pdev
= NULL
;
375 struct resource
*found
= NULL
;
376 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
379 if (page_is_ram(pfn
))
382 prot
= pgprot_noncached(prot
);
383 for_each_pci_dev(pdev
) {
384 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
385 struct resource
*rp
= &pdev
->resource
[i
];
386 int flags
= rp
->flags
;
388 /* Active and same type? */
389 if ((flags
& IORESOURCE_MEM
) == 0)
391 /* In the range of this resource? */
392 if (offset
< (rp
->start
& PAGE_MASK
) ||
402 if (found
->flags
& IORESOURCE_PREFETCH
)
403 prot
= pgprot_noncached_wc(prot
);
407 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
408 (unsigned long long)offset
, pgprot_val(prot
));
415 * Perform the actual remap of the pages for a PCI device mapping, as
416 * appropriate for this architecture. The region in the process to map
417 * is described by vm_start and vm_end members of VMA, the base physical
418 * address is found in vm_pgoff.
419 * The pci device structure is provided so that architectures may make mapping
420 * decisions on a per-device or per-bus basis.
422 * Returns a negative error code on failure, zero on success.
424 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
425 enum pci_mmap_state mmap_state
, int write_combine
)
427 resource_size_t offset
=
428 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
432 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
436 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
437 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
439 mmap_state
, write_combine
);
441 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
442 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
447 /* This provides legacy IO read access on a bus */
448 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
450 unsigned long offset
;
451 struct pci_controller
*hose
= pci_bus_to_host(bus
);
452 struct resource
*rp
= &hose
->io_resource
;
455 /* Check if port can be supported by that bus. We only check
456 * the ranges of the PHB though, not the bus itself as the rules
457 * for forwarding legacy cycles down bridges are not our problem
458 * here. So if the host bridge supports it, we do it.
460 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
463 if (!(rp
->flags
& IORESOURCE_IO
))
465 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
467 addr
= hose
->io_base_virt
+ port
;
471 *((u8
*)val
) = in_8(addr
);
476 *((u16
*)val
) = in_le16(addr
);
481 *((u32
*)val
) = in_le32(addr
);
487 /* This provides legacy IO write access on a bus */
488 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
490 unsigned long offset
;
491 struct pci_controller
*hose
= pci_bus_to_host(bus
);
492 struct resource
*rp
= &hose
->io_resource
;
495 /* Check if port can be supported by that bus. We only check
496 * the ranges of the PHB though, not the bus itself as the rules
497 * for forwarding legacy cycles down bridges are not our problem
498 * here. So if the host bridge supports it, we do it.
500 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
503 if (!(rp
->flags
& IORESOURCE_IO
))
505 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
507 addr
= hose
->io_base_virt
+ port
;
509 /* WARNING: The generic code is idiotic. It gets passed a pointer
510 * to what can be a 1, 2 or 4 byte quantity and always reads that
511 * as a u32, which means that we have to correct the location of
512 * the data read within those 32 bits for size 1 and 2
516 out_8(addr
, val
>> 24);
521 out_le16(addr
, val
>> 16);
532 /* This provides legacy IO or memory mmap access on a bus */
533 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
534 struct vm_area_struct
*vma
,
535 enum pci_mmap_state mmap_state
)
537 struct pci_controller
*hose
= pci_bus_to_host(bus
);
538 resource_size_t offset
=
539 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
540 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
543 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
544 pci_domain_nr(bus
), bus
->number
,
545 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
546 (unsigned long long)offset
,
547 (unsigned long long)(offset
+ size
- 1));
549 if (mmap_state
== pci_mmap_mem
) {
552 * Because X is lame and can fail starting if it gets an error trying
553 * to mmap legacy_mem (instead of just moving on without legacy memory
554 * access) we fake it here by giving it anonymous memory, effectively
555 * behaving just like /dev/zero
557 if ((offset
+ size
) > hose
->isa_mem_size
) {
559 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
560 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
561 if (vma
->vm_flags
& VM_SHARED
)
562 return shmem_zero_setup(vma
);
565 offset
+= hose
->isa_mem_phys
;
567 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
568 unsigned long roffset
= offset
+ io_offset
;
569 rp
= &hose
->io_resource
;
570 if (!(rp
->flags
& IORESOURCE_IO
))
572 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
574 offset
+= hose
->io_base_phys
;
576 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
578 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
579 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
580 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
581 vma
->vm_end
- vma
->vm_start
,
585 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
586 const struct resource
*rsrc
,
587 resource_size_t
*start
, resource_size_t
*end
)
589 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
590 resource_size_t offset
= 0;
595 if (rsrc
->flags
& IORESOURCE_IO
)
596 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
598 /* We pass a fully fixed up address to userland for MMIO instead of
599 * a BAR value because X is lame and expects to be able to use that
600 * to pass to /dev/mem !
602 * That means that we'll have potentially 64 bits values where some
603 * userland apps only expect 32 (like X itself since it thinks only
604 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
607 * Hopefully, the sysfs insterface is immune to that gunk. Once X
608 * has been fixed (and the fix spread enough), we can re-enable the
609 * 2 lines below and pass down a BAR value to userland. In that case
610 * we'll also have to re-enable the matching code in
611 * __pci_mmap_make_offset().
616 *start
= rsrc
->start
- offset
;
617 *end
= rsrc
->end
- offset
;
621 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
622 * @hose: newly allocated pci_controller to be setup
623 * @dev: device node of the host bridge
624 * @primary: set if primary bus (32 bits only, soon to be deprecated)
626 * This function will parse the "ranges" property of a PCI host bridge device
627 * node and setup the resource mapping of a pci controller based on its
630 * Life would be boring if it wasn't for a few issues that we have to deal
633 * - We can only cope with one IO space range and up to 3 Memory space
634 * ranges. However, some machines (thanks Apple !) tend to split their
635 * space into lots of small contiguous ranges. So we have to coalesce.
637 * - We can only cope with all memory ranges having the same offset
638 * between CPU addresses and PCI addresses. Unfortunately, some bridges
639 * are setup for a large 1:1 mapping along with a small "window" which
640 * maps PCI address 0 to some arbitrary high address of the CPU space in
641 * order to give access to the ISA memory hole.
642 * The way out of here that I've chosen for now is to always set the
643 * offset based on the first resource found, then override it if we
644 * have a different offset and the previous was set by an ISA hole.
646 * - Some busses have IO space not starting at 0, which causes trouble with
647 * the way we do our IO resource renumbering. The code somewhat deals with
648 * it for 64 bits but I would expect problems on 32 bits.
650 * - Some 32 bits platforms such as 4xx can have physical space larger than
651 * 32 bits so we need to use 64 bits values for the parsing
653 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
654 struct device_node
*dev
,
659 int pna
= of_n_addr_cells(dev
);
661 int memno
= 0, isa_hole
= -1;
663 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
664 unsigned long long isa_mb
= 0;
665 struct resource
*res
;
667 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
668 dev
->full_name
, primary
? "(primary)" : "");
670 /* Get ranges property */
671 ranges
= of_get_property(dev
, "ranges", &rlen
);
676 while ((rlen
-= np
* 4) >= 0) {
677 /* Read next ranges element */
678 pci_space
= ranges
[0];
679 pci_addr
= of_read_number(ranges
+ 1, 2);
680 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
681 size
= of_read_number(ranges
+ pna
+ 3, 2);
684 /* If we failed translation or got a zero-sized region
685 * (some FW try to feed us with non sensical zero sized regions
686 * such as power3 which look like some kind of attempt at exposing
687 * the VGA memory hole)
689 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
692 /* Now consume following elements while they are contiguous */
693 for (; rlen
>= np
* sizeof(u32
);
694 ranges
+= np
, rlen
-= np
* 4) {
695 if (ranges
[0] != pci_space
)
697 pci_next
= of_read_number(ranges
+ 1, 2);
698 cpu_next
= of_translate_address(dev
, ranges
+ 3);
699 if (pci_next
!= pci_addr
+ size
||
700 cpu_next
!= cpu_addr
+ size
)
702 size
+= of_read_number(ranges
+ pna
+ 3, 2);
705 /* Act based on address space type */
707 switch ((pci_space
>> 24) & 0x3) {
708 case 1: /* PCI IO space */
710 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
711 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
713 /* We support only one IO range */
714 if (hose
->pci_io_size
) {
716 " \\--> Skipped (too many) !\n");
720 /* On 32 bits, limit I/O space to 16MB */
721 if (size
> 0x01000000)
724 /* 32 bits needs to map IOs here */
725 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
727 /* Expect trouble if pci_addr is not 0 */
730 (unsigned long)hose
->io_base_virt
;
731 #endif /* CONFIG_PPC32 */
732 /* pci_io_size and io_base_phys always represent IO
733 * space starting at 0 so we factor in pci_addr
735 hose
->pci_io_size
= pci_addr
+ size
;
736 hose
->io_base_phys
= cpu_addr
- pci_addr
;
739 res
= &hose
->io_resource
;
740 res
->flags
= IORESOURCE_IO
;
741 res
->start
= pci_addr
;
743 case 2: /* PCI Memory space */
744 case 3: /* PCI 64 bits Memory space */
746 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
747 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
748 (pci_space
& 0x40000000) ? "Prefetch" : "");
750 /* We support only 3 memory ranges */
753 " \\--> Skipped (too many) !\n");
756 /* Handles ISA memory hole space here */
760 if (primary
|| isa_mem_base
== 0)
761 isa_mem_base
= cpu_addr
;
762 hose
->isa_mem_phys
= cpu_addr
;
763 hose
->isa_mem_size
= size
;
766 /* We get the PCI/Mem offset from the first range or
767 * the, current one if the offset came from an ISA
768 * hole. If they don't match, bugger.
771 (isa_hole
>= 0 && pci_addr
!= 0 &&
772 hose
->pci_mem_offset
== isa_mb
))
773 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
774 else if (pci_addr
!= 0 &&
775 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
777 " \\--> Skipped (offset mismatch) !\n");
782 res
= &hose
->mem_resources
[memno
++];
783 res
->flags
= IORESOURCE_MEM
;
784 if (pci_space
& 0x40000000)
785 res
->flags
|= IORESOURCE_PREFETCH
;
786 res
->start
= cpu_addr
;
790 res
->name
= dev
->full_name
;
791 res
->end
= res
->start
+ size
- 1;
798 /* If there's an ISA hole and the pci_mem_offset is -not- matching
799 * the ISA hole offset, then we need to remove the ISA hole from
800 * the resource list for that brige
802 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
803 unsigned int next
= isa_hole
+ 1;
804 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
806 memmove(&hose
->mem_resources
[isa_hole
],
807 &hose
->mem_resources
[next
],
808 sizeof(struct resource
) * (memno
- next
));
809 hose
->mem_resources
[--memno
].flags
= 0;
813 /* Decide whether to display the domain number in /proc */
814 int pci_proc_domain(struct pci_bus
*bus
)
816 struct pci_controller
*hose
= pci_bus_to_host(bus
);
818 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
820 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
821 return hose
->global_number
!= 0;
825 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
826 struct resource
*res
)
828 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
829 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
833 if (res
->flags
& IORESOURCE_IO
) {
834 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
836 } else if (res
->flags
& IORESOURCE_MEM
)
837 offset
= hose
->pci_mem_offset
;
839 region
->start
= (res
->start
- offset
) & mask
;
840 region
->end
= (res
->end
- offset
) & mask
;
842 EXPORT_SYMBOL(pcibios_resource_to_bus
);
844 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
845 struct pci_bus_region
*region
)
847 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
848 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
852 if (res
->flags
& IORESOURCE_IO
) {
853 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
855 } else if (res
->flags
& IORESOURCE_MEM
)
856 offset
= hose
->pci_mem_offset
;
857 res
->start
= (region
->start
+ offset
) & mask
;
858 res
->end
= (region
->end
+ offset
) & mask
;
860 EXPORT_SYMBOL(pcibios_bus_to_resource
);
862 /* Fixup a bus resource into a linux resource */
863 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
865 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
866 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
868 if (res
->flags
& IORESOURCE_IO
) {
869 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
871 } else if (res
->flags
& IORESOURCE_MEM
)
872 offset
= hose
->pci_mem_offset
;
874 res
->start
= (res
->start
+ offset
) & mask
;
875 res
->end
= (res
->end
+ offset
) & mask
;
879 /* This header fixup will do the resource fixup for all devices as they are
880 * probed, but not for bridge ranges
882 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
884 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
888 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
892 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
893 struct resource
*res
= dev
->resource
+ i
;
896 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
897 * consider 0 as an unassigned BAR value. It's technically
898 * a valid value, but linux doesn't like it... so when we can
899 * re-assign things, we do so, but if we can't, we keep it
900 * around and hope for the best...
902 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
903 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
905 (unsigned long long)res
->start
,
906 (unsigned long long)res
->end
,
907 (unsigned int)res
->flags
);
908 res
->end
-= res
->start
;
910 res
->flags
|= IORESOURCE_UNSET
;
914 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
916 (unsigned long long)res
->start
,\
917 (unsigned long long)res
->end
,
918 (unsigned int)res
->flags
);
920 fixup_resource(res
, dev
);
922 pr_debug("PCI:%s %016llx-%016llx\n",
924 (unsigned long long)res
->start
,
925 (unsigned long long)res
->end
);
928 /* Call machine specific resource fixup */
929 if (ppc_md
.pcibios_fixup_resources
)
930 ppc_md
.pcibios_fixup_resources(dev
);
932 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
934 /* This function tries to figure out if a bridge resource has been initialized
935 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
936 * things go more smoothly when it gets it right. It should covers cases such
937 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
939 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
940 struct resource
*res
)
942 struct pci_controller
*hose
= pci_bus_to_host(bus
);
943 struct pci_dev
*dev
= bus
->self
;
944 resource_size_t offset
;
948 /* We don't do anything if PCI_PROBE_ONLY is set */
949 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
952 /* Job is a bit different between memory and IO */
953 if (res
->flags
& IORESOURCE_MEM
) {
954 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
955 * initialized by somebody
957 if (res
->start
!= hose
->pci_mem_offset
)
960 /* The BAR is 0, let's check if memory decoding is enabled on
961 * the bridge. If not, we consider it unassigned
963 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
964 if ((command
& PCI_COMMAND_MEMORY
) == 0)
967 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
968 * resources covers that starting address (0 then it's good enough for
971 for (i
= 0; i
< 3; i
++) {
972 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
973 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
977 /* Well, it starts at 0 and we know it will collide so we may as
978 * well consider it as unassigned. That covers the Apple case.
982 /* If the BAR is non-0, then we consider it assigned */
983 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
984 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
987 /* Here, we are a bit different than memory as typically IO space
988 * starting at low addresses -is- valid. What we do instead if that
989 * we consider as unassigned anything that doesn't have IO enabled
990 * in the PCI command register, and that's it.
992 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
993 if (command
& PCI_COMMAND_IO
)
996 /* It's starting at 0 and IO is disabled in the bridge, consider
1003 /* Fixup resources of a PCI<->PCI bridge */
1004 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1006 struct resource
*res
;
1009 struct pci_dev
*dev
= bus
->self
;
1011 pci_bus_for_each_resource(bus
, res
, i
) {
1012 if (!res
|| !res
->flags
)
1014 if (i
>= 3 && bus
->self
->transparent
)
1017 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1019 (unsigned long long)res
->start
,\
1020 (unsigned long long)res
->end
,
1021 (unsigned int)res
->flags
);
1024 fixup_resource(res
, dev
);
1026 /* Try to detect uninitialized P2P bridge resources,
1027 * and clear them out so they get re-assigned later
1029 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1031 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1034 pr_debug("PCI:%s %016llx-%016llx\n",
1036 (unsigned long long)res
->start
,
1037 (unsigned long long)res
->end
);
1042 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1044 /* Fix up the bus resources for P2P bridges */
1045 if (bus
->self
!= NULL
)
1046 pcibios_fixup_bridge(bus
);
1048 /* Platform specific bus fixups. This is currently only used
1049 * by fsl_pci and I'm hoping to get rid of it at some point
1051 if (ppc_md
.pcibios_fixup_bus
)
1052 ppc_md
.pcibios_fixup_bus(bus
);
1054 /* Setup bus DMA mappings */
1055 if (ppc_md
.pci_dma_bus_setup
)
1056 ppc_md
.pci_dma_bus_setup(bus
);
1059 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1061 struct pci_dev
*dev
;
1063 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1064 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1066 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1067 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1069 /* Cardbus can call us to add new devices to a bus, so ignore
1070 * those who are already fully discovered
1075 /* Setup OF node pointer in the device */
1076 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
1078 /* Fixup NUMA node as it may not be setup yet by the generic
1079 * code and is needed by the DMA init
1081 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1083 /* Hook up default DMA ops */
1084 sd
->dma_ops
= pci_dma_ops
;
1085 set_dma_offset(&dev
->dev
, PCI_DRAM_OFFSET
);
1087 /* Additional platform DMA/iommu setup */
1088 if (ppc_md
.pci_dma_dev_setup
)
1089 ppc_md
.pci_dma_dev_setup(dev
);
1091 /* Read default IRQs and fixup if necessary */
1092 pci_read_irq_line(dev
);
1093 if (ppc_md
.pci_irq_fixup
)
1094 ppc_md
.pci_irq_fixup(dev
);
1098 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1100 /* When called from the generic PCI probe, read PCI<->PCI bridge
1101 * bases. This is -not- called when generating the PCI tree from
1102 * the OF device-tree.
1104 if (bus
->self
!= NULL
)
1105 pci_read_bridge_bases(bus
);
1107 /* Now fixup the bus bus */
1108 pcibios_setup_bus_self(bus
);
1110 /* Now fixup devices on that bus */
1111 pcibios_setup_bus_devices(bus
);
1113 EXPORT_SYMBOL(pcibios_fixup_bus
);
1115 void __devinit
pci_fixup_cardbus(struct pci_bus
*bus
)
1117 /* Now fixup devices on that bus */
1118 pcibios_setup_bus_devices(bus
);
1122 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1124 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1125 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1131 * We need to avoid collisions with `mirrored' VGA ports
1132 * and other strange ISA hardware, so we always want the
1133 * addresses to be allocated in the 0x000-0x0ff region
1136 * Why? Because some silly external IO cards only decode
1137 * the low 10 bits of the IO address. The 0x00-0xff region
1138 * is reserved for motherboard devices that decode all 16
1139 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1140 * but we want to try to avoid allocating at 0x2900-0x2bff
1141 * which might have be mirrored at 0x0100-0x03ff..
1143 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1144 resource_size_t size
, resource_size_t align
)
1146 struct pci_dev
*dev
= data
;
1147 resource_size_t start
= res
->start
;
1149 if (res
->flags
& IORESOURCE_IO
) {
1150 if (skip_isa_ioresource_align(dev
))
1153 start
= (start
+ 0x3ff) & ~0x3ff;
1158 EXPORT_SYMBOL(pcibios_align_resource
);
1161 * Reparent resource children of pr that conflict with res
1162 * under res, and make res replace those children.
1164 static int reparent_resources(struct resource
*parent
,
1165 struct resource
*res
)
1167 struct resource
*p
, **pp
;
1168 struct resource
**firstpp
= NULL
;
1170 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1171 if (p
->end
< res
->start
)
1173 if (res
->end
< p
->start
)
1175 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1176 return -1; /* not completely contained */
1177 if (firstpp
== NULL
)
1180 if (firstpp
== NULL
)
1181 return -1; /* didn't find any conflicting entries? */
1182 res
->parent
= parent
;
1183 res
->child
= *firstpp
;
1187 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1189 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1191 (unsigned long long)p
->start
,
1192 (unsigned long long)p
->end
, res
->name
);
1198 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1202 struct resource
*res
, *pr
;
1204 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1205 pci_domain_nr(bus
), bus
->number
);
1207 pci_bus_for_each_resource(bus
, res
, i
) {
1208 if (!res
|| !res
->flags
|| res
->start
> res
->end
|| res
->parent
)
1210 if (bus
->parent
== NULL
)
1211 pr
= (res
->flags
& IORESOURCE_IO
) ?
1212 &ioport_resource
: &iomem_resource
;
1214 /* Don't bother with non-root busses when
1215 * re-assigning all resources. We clear the
1216 * resource flags as if they were colliding
1217 * and as such ensure proper re-allocation
1220 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1221 goto clear_resource
;
1222 pr
= pci_find_parent_resource(bus
->self
, res
);
1224 /* this happens when the generic PCI
1225 * code (wrongly) decides that this
1226 * bridge is transparent -- paulus
1232 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1233 "[0x%x], parent %p (%s)\n",
1234 bus
->self
? pci_name(bus
->self
) : "PHB",
1236 (unsigned long long)res
->start
,
1237 (unsigned long long)res
->end
,
1238 (unsigned int)res
->flags
,
1239 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1241 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1242 if (request_resource(pr
, res
) == 0)
1245 * Must be a conflict with an existing entry.
1246 * Move that entry (or entries) under the
1247 * bridge resource and try again.
1249 if (reparent_resources(pr
, res
) == 0)
1252 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1253 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1255 res
->start
= res
->end
= 0;
1259 list_for_each_entry(b
, &bus
->children
, node
)
1260 pcibios_allocate_bus_resources(b
);
1263 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1265 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1267 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1269 (unsigned long long)r
->start
,
1270 (unsigned long long)r
->end
,
1271 (unsigned int)r
->flags
);
1273 pr
= pci_find_parent_resource(dev
, r
);
1274 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1275 request_resource(pr
, r
) < 0) {
1276 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1277 " of device %s, will remap\n", idx
, pci_name(dev
));
1279 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1281 (unsigned long long)pr
->start
,
1282 (unsigned long long)pr
->end
,
1283 (unsigned int)pr
->flags
);
1284 /* We'll assign a new address later */
1285 r
->flags
|= IORESOURCE_UNSET
;
1291 static void __init
pcibios_allocate_resources(int pass
)
1293 struct pci_dev
*dev
= NULL
;
1298 for_each_pci_dev(dev
) {
1299 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1300 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1301 r
= &dev
->resource
[idx
];
1302 if (r
->parent
) /* Already allocated */
1304 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1305 continue; /* Not assigned at all */
1306 /* We only allocate ROMs on pass 1 just in case they
1307 * have been screwed up by firmware
1309 if (idx
== PCI_ROM_RESOURCE
)
1311 if (r
->flags
& IORESOURCE_IO
)
1312 disabled
= !(command
& PCI_COMMAND_IO
);
1314 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1315 if (pass
== disabled
)
1316 alloc_resource(dev
, idx
);
1320 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1322 /* Turn the ROM off, leave the resource region,
1323 * but keep it unregistered.
1326 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1327 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1328 pr_debug("PCI: Switching off ROM of %s\n",
1330 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1331 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1332 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1338 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1340 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1341 resource_size_t offset
;
1342 struct resource
*res
, *pres
;
1345 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1348 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1350 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1351 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1352 BUG_ON(res
== NULL
);
1353 res
->name
= "Legacy IO";
1354 res
->flags
= IORESOURCE_IO
;
1355 res
->start
= offset
;
1356 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1357 pr_debug("Candidate legacy IO: %pR\n", res
);
1358 if (request_resource(&hose
->io_resource
, res
)) {
1360 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1361 pci_domain_nr(bus
), bus
->number
, res
);
1366 /* Check for memory */
1367 offset
= hose
->pci_mem_offset
;
1368 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1369 for (i
= 0; i
< 3; i
++) {
1370 pres
= &hose
->mem_resources
[i
];
1371 if (!(pres
->flags
& IORESOURCE_MEM
))
1373 pr_debug("hose mem res: %pR\n", pres
);
1374 if ((pres
->start
- offset
) <= 0xa0000 &&
1375 (pres
->end
- offset
) >= 0xbffff)
1380 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1381 BUG_ON(res
== NULL
);
1382 res
->name
= "Legacy VGA memory";
1383 res
->flags
= IORESOURCE_MEM
;
1384 res
->start
= 0xa0000 + offset
;
1385 res
->end
= 0xbffff + offset
;
1386 pr_debug("Candidate VGA memory: %pR\n", res
);
1387 if (request_resource(pres
, res
)) {
1389 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1390 pci_domain_nr(bus
), bus
->number
, res
);
1395 void __init
pcibios_resource_survey(void)
1399 /* Allocate and assign resources. If we re-assign everything, then
1400 * we skip the allocate phase
1402 list_for_each_entry(b
, &pci_root_buses
, node
)
1403 pcibios_allocate_bus_resources(b
);
1405 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1406 pcibios_allocate_resources(0);
1407 pcibios_allocate_resources(1);
1410 /* Before we start assigning unassigned resource, we try to reserve
1411 * the low IO area and the VGA memory area if they intersect the
1412 * bus available resources to avoid allocating things on top of them
1414 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1415 list_for_each_entry(b
, &pci_root_buses
, node
)
1416 pcibios_reserve_legacy_regions(b
);
1419 /* Now, if the platform didn't decide to blindly trust the firmware,
1420 * we proceed to assigning things that were left unassigned
1422 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1423 pr_debug("PCI: Assigning unassigned resources...\n");
1424 pci_assign_unassigned_resources();
1427 /* Call machine dependent fixup */
1428 if (ppc_md
.pcibios_fixup
)
1429 ppc_md
.pcibios_fixup();
1432 #ifdef CONFIG_HOTPLUG
1434 /* This is used by the PCI hotplug driver to allocate resource
1435 * of newly plugged busses. We can try to consolidate with the
1436 * rest of the code later, for now, keep it as-is as our main
1437 * resource allocation function doesn't deal with sub-trees yet.
1439 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1441 struct pci_dev
*dev
;
1442 struct pci_bus
*child_bus
;
1444 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1447 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1448 struct resource
*r
= &dev
->resource
[i
];
1450 if (r
->parent
|| !r
->start
|| !r
->flags
)
1453 pr_debug("PCI: Claiming %s: "
1454 "Resource %d: %016llx..%016llx [%x]\n",
1456 (unsigned long long)r
->start
,
1457 (unsigned long long)r
->end
,
1458 (unsigned int)r
->flags
);
1460 pci_claim_resource(dev
, i
);
1464 list_for_each_entry(child_bus
, &bus
->children
, node
)
1465 pcibios_claim_one_bus(child_bus
);
1469 /* pcibios_finish_adding_to_bus
1471 * This is to be called by the hotplug code after devices have been
1472 * added to a bus, this include calling it for a PHB that is just
1475 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1477 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1478 pci_domain_nr(bus
), bus
->number
);
1480 /* Allocate bus and devices resources */
1481 pcibios_allocate_bus_resources(bus
);
1482 pcibios_claim_one_bus(bus
);
1484 /* Add new devices to global lists. Register in proc, sysfs. */
1485 pci_bus_add_devices(bus
);
1488 eeh_add_device_tree_late(bus
);
1490 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1492 #endif /* CONFIG_HOTPLUG */
1494 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1496 if (ppc_md
.pcibios_enable_device_hook
)
1497 if (ppc_md
.pcibios_enable_device_hook(dev
))
1500 return pci_enable_resources(dev
, mask
);
1503 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1505 struct pci_bus
*bus
= hose
->bus
;
1506 struct resource
*res
;
1509 /* Hookup PHB IO resource */
1510 bus
->resource
[0] = res
= &hose
->io_resource
;
1513 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1514 " bridge %s (domain %d)\n",
1515 hose
->dn
->full_name
, hose
->global_number
);
1517 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1518 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1519 res
->flags
= IORESOURCE_IO
;
1520 #endif /* CONFIG_PPC32 */
1523 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1524 (unsigned long long)res
->start
,
1525 (unsigned long long)res
->end
,
1526 (unsigned long)res
->flags
);
1528 /* Hookup PHB Memory resources */
1529 for (i
= 0; i
< 3; ++i
) {
1530 res
= &hose
->mem_resources
[i
];
1534 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1535 "host bridge %s (domain %d)\n",
1536 hose
->dn
->full_name
, hose
->global_number
);
1538 res
->start
= hose
->pci_mem_offset
;
1539 res
->end
= (resource_size_t
)-1LL;
1540 res
->flags
= IORESOURCE_MEM
;
1541 #endif /* CONFIG_PPC32 */
1543 bus
->resource
[i
+1] = res
;
1545 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1546 (unsigned long long)res
->start
,
1547 (unsigned long long)res
->end
,
1548 (unsigned long)res
->flags
);
1551 pr_debug("PCI: PHB MEM offset = %016llx\n",
1552 (unsigned long long)hose
->pci_mem_offset
);
1553 pr_debug("PCI: PHB IO offset = %08lx\n",
1554 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1559 * Null PCI config access functions, for the case when we can't
1562 #define NULL_PCI_OP(rw, size, type) \
1564 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1566 return PCIBIOS_DEVICE_NOT_FOUND; \
1570 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1573 return PCIBIOS_DEVICE_NOT_FOUND
;
1577 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1580 return PCIBIOS_DEVICE_NOT_FOUND
;
1583 static struct pci_ops null_pci_ops
=
1585 .read
= null_read_config
,
1586 .write
= null_write_config
,
1590 * These functions are used early on before PCI scanning is done
1591 * and all of the pci_dev and pci_bus structures have been created.
1593 static struct pci_bus
*
1594 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1596 static struct pci_bus bus
;
1599 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1603 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1607 #define EARLY_PCI_OP(rw, size, type) \
1608 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1609 int devfn, int offset, type value) \
1611 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1612 devfn, offset, value); \
1615 EARLY_PCI_OP(read
, byte
, u8
*)
1616 EARLY_PCI_OP(read
, word
, u16
*)
1617 EARLY_PCI_OP(read
, dword
, u32
*)
1618 EARLY_PCI_OP(write
, byte
, u8
)
1619 EARLY_PCI_OP(write
, word
, u16
)
1620 EARLY_PCI_OP(write
, dword
, u32
)
1622 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1623 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1626 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);
1630 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1631 * @hose: Pointer to the PCI host controller instance structure
1632 * @sysdata: value to use for sysdata pointer. ppc32 and ppc64 differ here
1634 * Note: the 'data' pointer is a temporary measure. As 32 and 64 bit
1635 * pci code gets merged, this parameter should become unnecessary because
1636 * both will use the same value.
1638 void __devinit
pcibios_scan_phb(struct pci_controller
*hose
, void *sysdata
)
1640 struct pci_bus
*bus
;
1641 struct device_node
*node
= hose
->dn
;
1644 pr_debug("PCI: Scanning PHB %s\n",
1645 node
? node
->full_name
: "<NO NAME>");
1647 /* Create an empty bus for the toplevel */
1648 bus
= pci_create_bus(hose
->parent
, hose
->first_busno
, hose
->ops
,
1651 pr_err("Failed to create bus for PCI domain %04x\n",
1652 hose
->global_number
);
1655 bus
->secondary
= hose
->first_busno
;
1658 /* Get some IO space for the new PHB */
1659 pcibios_setup_phb_io_space(hose
);
1661 /* Wire up PHB bus resources */
1662 pcibios_setup_phb_resources(hose
);
1664 /* Get probe mode and perform scan */
1665 mode
= PCI_PROBE_NORMAL
;
1666 if (node
&& ppc_md
.pci_probe_mode
)
1667 mode
= ppc_md
.pci_probe_mode(bus
);
1668 pr_debug(" probe mode: %d\n", mode
);
1669 if (mode
== PCI_PROBE_DEVTREE
) {
1670 bus
->subordinate
= hose
->last_busno
;
1671 of_scan_bus(node
, bus
);
1674 if (mode
== PCI_PROBE_NORMAL
)
1675 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);