[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / powerpc / kernel / head_40x.S
| blob | 123399e89ced5602256f841d91cad9a949c34945 |
1 /*
2 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
3 * Initial PowerPC version.
4 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
5 * Rewritten for PReP
6 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
7 * Low-level exception handers, MMU support, and rewrite.
8 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
9 * PowerPC 8xx modifications.
10 * Copyright (c) 1998-1999 TiVo, Inc.
11 * PowerPC 403GCX modifications.
12 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
13 * PowerPC 403GCX/405GP modifications.
14 * Copyright 2000 MontaVista Software Inc.
15 * PPC405 modifications
16 * PowerPC 403GCX/405GP modifications.
17 * Author: MontaVista Software, Inc.
18 * frank_rowand@mvista.com or source@mvista.com
19 * debbie_chu@mvista.com
20 *
21 *
22 * Module name: head_4xx.S
23 *
24 * Description:
25 * Kernel execution entry point code.
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License
29 * as published by the Free Software Foundation; either version
30 * 2 of the License, or (at your option) any later version.
31 *
32 */
34 #include <linux/init.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
44 /* As with the other PowerPC ports, it is expected that when code
45 * execution begins here, the following registers contain valid, yet
46 * optional, information:
47 *
48 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
49 * r4 - Starting address of the init RAM disk
50 * r5 - Ending address of the init RAM disk
51 * r6 - Start of kernel command line string (e.g. "mem=96m")
52 * r7 - End of kernel command line string
53 *
54 * This is all going to change RSN when we add bi_recs....... -- Dan
55 */
56 __HEAD
57 _ENTRY(_stext);
58 _ENTRY(_start);
60 /* Save parameters we are passed.
61 */
62 mr r31,r3
63 mr r30,r4
64 mr r29,r5
65 mr r28,r6
66 mr r27,r7
68 /* We have to turn on the MMU right away so we get cache modes
69 * set correctly.
70 */
71 bl initial_mmu
73 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
74 * ready to work.
75 */
76 turn_on_mmu:
77 lis r0,MSR_KERNEL@h
78 ori r0,r0,MSR_KERNEL@l
79 mtspr SPRN_SRR1,r0
80 lis r0,start_here@h
81 ori r0,r0,start_here@l
82 mtspr SPRN_SRR0,r0
83 SYNC
84 rfi /* enables MMU */
85 b . /* prevent prefetch past rfi */
87 /*
88 * This area is used for temporarily saving registers during the
89 * critical exception prolog.
90 */
91 . = 0xc0
92 crit_save:
93 _ENTRY(crit_r10)
94 .space 4
95 _ENTRY(crit_r11)
96 .space 4
97 _ENTRY(crit_srr0)
98 .space 4
99 _ENTRY(crit_srr1)
100 .space 4
101 _ENTRY(saved_ksp_limit)
102 .space 4
104 /*
105 * Exception vector entry code. This code runs with address translation
106 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
107 * the physical address of the current task thread_struct.
108 * Note that we have to have decremented r1 before we write to any fields
109 * of the exception frame, since a critical interrupt could occur at any
110 * time, and it will write to the area immediately below the current r1.
111 */
112 #define NORMAL_EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
114 mtspr SPRN_SPRG_SCRATCH1,r11; \
115 mtspr SPRN_SPRG_SCRATCH2,r1; \
116 mfcr r10; /* save CR in r10 for now */\
117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
118 andi. r11,r11,MSR_PR; \
119 beq 1f; \
120 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
121 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
122 addi r1,r1,THREAD_SIZE; \
123 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
124 tophys(r11,r1); \
125 stw r10,_CCR(r11); /* save various registers */\
126 stw r12,GPR12(r11); \
127 stw r9,GPR9(r11); \
128 mfspr r10,SPRN_SPRG_SCRATCH0; \
129 stw r10,GPR10(r11); \
130 mfspr r12,SPRN_SPRG_SCRATCH1; \
131 stw r12,GPR11(r11); \
132 mflr r10; \
133 stw r10,_LINK(r11); \
134 mfspr r10,SPRN_SPRG_SCRATCH2; \
135 mfspr r12,SPRN_SRR0; \
136 stw r10,GPR1(r11); \
137 mfspr r9,SPRN_SRR1; \
138 stw r10,0(r11); \
139 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
140 stw r0,GPR0(r11); \
141 SAVE_4GPRS(3, r11); \
142 SAVE_2GPRS(7, r11)
144 /*
145 * Exception prolog for critical exceptions. This is a little different
146 * from the normal exception prolog above since a critical exception
147 * can potentially occur at any point during normal exception processing.
148 * Thus we cannot use the same SPRG registers as the normal prolog above.
149 * Instead we use a couple of words of memory at low physical addresses.
150 * This is OK since we don't support SMP on these processors.
151 */
152 #define CRITICAL_EXCEPTION_PROLOG \
153 stw r10,crit_r10@l(0); /* save two registers to work with */\
154 stw r11,crit_r11@l(0); \
155 mfcr r10; /* save CR in r10 for now */\
156 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\
157 andi. r11,r11,MSR_PR; \
158 lis r11,critirq_ctx@ha; \
159 tophys(r11,r11); \
160 lwz r11,critirq_ctx@l(r11); \
161 beq 1f; \
162 /* COMING FROM USER MODE */ \
163 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
164 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
165 1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\
166 tophys(r11,r11); \
167 stw r10,_CCR(r11); /* save various registers */\
168 stw r12,GPR12(r11); \
169 stw r9,GPR9(r11); \
170 mflr r10; \
171 stw r10,_LINK(r11); \
172 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
173 stw r12,_DEAR(r11); /* since they may have had stuff */\
174 mfspr r9,SPRN_ESR; /* in them at the point where the */\
175 stw r9,_ESR(r11); /* exception was taken */\
176 mfspr r12,SPRN_SRR2; \
177 stw r1,GPR1(r11); \
178 mfspr r9,SPRN_SRR3; \
179 stw r1,0(r11); \
180 tovirt(r1,r11); \
181 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
182 stw r0,GPR0(r11); \
183 SAVE_4GPRS(3, r11); \
184 SAVE_2GPRS(7, r11)
186 /*
187 * State at this point:
188 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
189 * r10 saved in crit_r10 and in stack frame, trashed
190 * r11 saved in crit_r11 and in stack frame,
191 * now phys stack/exception frame pointer
192 * r12 saved in stack frame, now saved SRR2
193 * CR saved in stack frame, CR0.EQ = !SRR3.PR
194 * LR, DEAR, ESR in stack frame
195 * r1 saved in stack frame, now virt stack/excframe pointer
196 * r0, r3-r8 saved in stack frame
197 */
199 /*
200 * Exception vectors.
201 */
202 #define START_EXCEPTION(n, label) \
203 . = n; \
204 label:
206 #define EXCEPTION(n, label, hdlr, xfer) \
207 START_EXCEPTION(n, label); \
208 NORMAL_EXCEPTION_PROLOG; \
209 addi r3,r1,STACK_FRAME_OVERHEAD; \
210 xfer(n, hdlr)
212 #define CRITICAL_EXCEPTION(n, label, hdlr) \
213 START_EXCEPTION(n, label); \
214 CRITICAL_EXCEPTION_PROLOG; \
215 addi r3,r1,STACK_FRAME_OVERHEAD; \
216 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
217 NOCOPY, crit_transfer_to_handler, \
218 ret_from_crit_exc)
220 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
221 li r10,trap; \
222 stw r10,_TRAP(r11); \
223 lis r10,msr@h; \
224 ori r10,r10,msr@l; \
225 copyee(r10, r9); \
226 bl tfer; \
227 .long hdlr; \
228 .long ret
230 #define COPY_EE(d, s) rlwimi d,s,0,16,16
231 #define NOCOPY(d, s)
233 #define EXC_XFER_STD(n, hdlr) \
234 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
235 ret_from_except_full)
237 #define EXC_XFER_LITE(n, hdlr) \
238 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
239 ret_from_except)
241 #define EXC_XFER_EE(n, hdlr) \
242 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
243 ret_from_except_full)
245 #define EXC_XFER_EE_LITE(n, hdlr) \
246 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
247 ret_from_except)
250 /*
251 * 0x0100 - Critical Interrupt Exception
252 */
253 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
255 /*
256 * 0x0200 - Machine Check Exception
257 */
258 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
260 /*
261 * 0x0300 - Data Storage Exception
262 * This happens for just a few reasons. U0 set (but we don't do that),
263 * or zone protection fault (user violation, write to protected page).
264 * If this is just an update of modified status, we do that quickly
265 * and exit. Otherwise, we call heavywight functions to do the work.
266 */
267 START_EXCEPTION(0x0300, DataStorage)
268 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
269 mtspr SPRN_SPRG_SCRATCH1, r11
270 #ifdef CONFIG_403GCX
271 stw r12, 0(r0)
272 stw r9, 4(r0)
273 mfcr r11
274 mfspr r12, SPRN_PID
275 stw r11, 8(r0)
276 stw r12, 12(r0)
277 #else
278 mtspr SPRN_SPRG_SCRATCH3, r12
279 mtspr SPRN_SPRG_SCRATCH4, r9
280 mfcr r11
281 mfspr r12, SPRN_PID
282 mtspr SPRN_SPRG_SCRATCH6, r11
283 mtspr SPRN_SPRG_SCRATCH5, r12
284 #endif
286 /* First, check if it was a zone fault (which means a user
287 * tried to access a kernel or read-protected page - always
288 * a SEGV). All other faults here must be stores, so no
289 * need to check ESR_DST as well. */
290 mfspr r10, SPRN_ESR
291 andis. r10, r10, ESR_DIZ@h
292 bne 2f
294 mfspr r10, SPRN_DEAR /* Get faulting address */
296 /* If we are faulting a kernel address, we have to use the
297 * kernel page tables.
298 */
299 lis r11, PAGE_OFFSET@h
300 cmplw r10, r11
301 blt+ 3f
302 lis r11, swapper_pg_dir@h
303 ori r11, r11, swapper_pg_dir@l
304 li r9, 0
305 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
306 b 4f
308 /* Get the PGD for the current thread.
309 */
310 3:
311 mfspr r11,SPRN_SPRG_THREAD
312 lwz r11,PGDIR(r11)
313 4:
314 tophys(r11, r11)
315 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
316 lwz r11, 0(r11) /* Get L1 entry */
317 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
318 beq 2f /* Bail if no table */
320 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
321 lwz r11, 0(r12) /* Get Linux PTE */
323 andi. r9, r11, _PAGE_RW /* Is it writeable? */
324 beq 2f /* Bail if not */
326 /* Update 'changed'.
327 */
328 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
329 stw r11, 0(r12) /* Update Linux page table */
331 /* Most of the Linux PTE is ready to load into the TLB LO.
332 * We set ZSEL, where only the LS-bit determines user access.
333 * We set execute, because we don't have the granularity to
334 * properly set this at the page level (Linux problem).
335 * If shared is set, we cause a zero PID->TID load.
336 * Many of these bits are software only. Bits we don't set
337 * here we (properly should) assume have the appropriate value.
338 */
339 li r12, 0x0ce2
340 andc r11, r11, r12 /* Make sure 20, 21 are zero */
342 /* find the TLB index that caused the fault. It has to be here.
343 */
344 tlbsx r9, 0, r10
346 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
348 /* Done...restore registers and get out of here.
349 */
350 #ifdef CONFIG_403GCX
351 lwz r12, 12(r0)
352 lwz r11, 8(r0)
353 mtspr SPRN_PID, r12
354 mtcr r11
355 lwz r9, 4(r0)
356 lwz r12, 0(r0)
357 #else
358 mfspr r12, SPRN_SPRG_SCRATCH5
359 mfspr r11, SPRN_SPRG_SCRATCH6
360 mtspr SPRN_PID, r12
361 mtcr r11
362 mfspr r9, SPRN_SPRG_SCRATCH4
363 mfspr r12, SPRN_SPRG_SCRATCH3
364 #endif
365 mfspr r11, SPRN_SPRG_SCRATCH1
366 mfspr r10, SPRN_SPRG_SCRATCH0
367 PPC405_ERR77_SYNC
368 rfi /* Should sync shadow TLBs */
369 b . /* prevent prefetch past rfi */
371 2:
372 /* The bailout. Restore registers to pre-exception conditions
373 * and call the heavyweights to help us out.
374 */
375 #ifdef CONFIG_403GCX
376 lwz r12, 12(r0)
377 lwz r11, 8(r0)
378 mtspr SPRN_PID, r12
379 mtcr r11
380 lwz r9, 4(r0)
381 lwz r12, 0(r0)
382 #else
383 mfspr r12, SPRN_SPRG_SCRATCH5
384 mfspr r11, SPRN_SPRG_SCRATCH6
385 mtspr SPRN_PID, r12
386 mtcr r11
387 mfspr r9, SPRN_SPRG_SCRATCH4
388 mfspr r12, SPRN_SPRG_SCRATCH3
389 #endif
390 mfspr r11, SPRN_SPRG_SCRATCH1
391 mfspr r10, SPRN_SPRG_SCRATCH0
392 b DataAccess
394 /*
395 * 0x0400 - Instruction Storage Exception
396 * This is caused by a fetch from non-execute or guarded pages.
397 */
398 START_EXCEPTION(0x0400, InstructionAccess)
399 NORMAL_EXCEPTION_PROLOG
400 mr r4,r12 /* Pass SRR0 as arg2 */
401 li r5,0 /* Pass zero as arg3 */
402 EXC_XFER_EE_LITE(0x400, handle_page_fault)
404 /* 0x0500 - External Interrupt Exception */
405 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
407 /* 0x0600 - Alignment Exception */
408 START_EXCEPTION(0x0600, Alignment)
409 NORMAL_EXCEPTION_PROLOG
410 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
411 stw r4,_DEAR(r11)
412 addi r3,r1,STACK_FRAME_OVERHEAD
413 EXC_XFER_EE(0x600, alignment_exception)
415 /* 0x0700 - Program Exception */
416 START_EXCEPTION(0x0700, ProgramCheck)
417 NORMAL_EXCEPTION_PROLOG
418 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
419 stw r4,_ESR(r11)
420 addi r3,r1,STACK_FRAME_OVERHEAD
421 EXC_XFER_STD(0x700, program_check_exception)
423 EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
424 EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
425 EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
426 EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
428 /* 0x0C00 - System Call Exception */
429 START_EXCEPTION(0x0C00, SystemCall)
430 NORMAL_EXCEPTION_PROLOG
431 EXC_XFER_EE_LITE(0xc00, DoSyscall)
433 EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
434 EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
435 EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
437 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
438 START_EXCEPTION(0x1000, Decrementer)
439 NORMAL_EXCEPTION_PROLOG
440 lis r0,TSR_PIS@h
441 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
442 addi r3,r1,STACK_FRAME_OVERHEAD
443 EXC_XFER_LITE(0x1000, timer_interrupt)
446 /* 0x1100 - Data TLB Miss Exception
447 * As the name implies, translation is not in the MMU, so search the
448 * page tables and fix it. The only purpose of this function is to
449 * load TLB entries from the page table if they exist.
450 */
451 START_EXCEPTION(0x1100, DTLBMiss)
452 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
453 mtspr SPRN_SPRG_SCRATCH1, r11
454 #ifdef CONFIG_403GCX
455 stw r12, 0(r0)
456 stw r9, 4(r0)
457 mfcr r11
458 mfspr r12, SPRN_PID
459 stw r11, 8(r0)
460 stw r12, 12(r0)
461 #else
462 mtspr SPRN_SPRG_SCRATCH3, r12
463 mtspr SPRN_SPRG_SCRATCH4, r9
464 mfcr r11
465 mfspr r12, SPRN_PID
466 mtspr SPRN_SPRG_SCRATCH6, r11
467 mtspr SPRN_SPRG_SCRATCH5, r12
468 #endif
469 mfspr r10, SPRN_DEAR /* Get faulting address */
471 /* If we are faulting a kernel address, we have to use the
472 * kernel page tables.
473 */
474 lis r11, PAGE_OFFSET@h
475 cmplw r10, r11
476 blt+ 3f
477 lis r11, swapper_pg_dir@h
478 ori r11, r11, swapper_pg_dir@l
479 li r9, 0
480 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
481 b 4f
483 /* Get the PGD for the current thread.
484 */
485 3:
486 mfspr r11,SPRN_SPRG_THREAD
487 lwz r11,PGDIR(r11)
488 4:
489 tophys(r11, r11)
490 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
491 lwz r12, 0(r11) /* Get L1 entry */
492 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
493 beq 2f /* Bail if no table */
495 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
496 lwz r11, 0(r12) /* Get Linux PTE */
497 andi. r9, r11, _PAGE_PRESENT
498 beq 5f
500 ori r11, r11, _PAGE_ACCESSED
501 stw r11, 0(r12)
503 /* Create TLB tag. This is the faulting address plus a static
504 * set of bits. These are size, valid, E, U0.
505 */
506 li r12, 0x00c0
507 rlwimi r10, r12, 0, 20, 31
509 b finish_tlb_load
511 2: /* Check for possible large-page pmd entry */
512 rlwinm. r9, r12, 2, 22, 24
513 beq 5f
515 /* Create TLB tag. This is the faulting address, plus a static
516 * set of bits (valid, E, U0) plus the size from the PMD.
517 */
518 ori r9, r9, 0x40
519 rlwimi r10, r9, 0, 20, 31
520 mr r11, r12
522 b finish_tlb_load
524 5:
525 /* The bailout. Restore registers to pre-exception conditions
526 * and call the heavyweights to help us out.
527 */
528 #ifdef CONFIG_403GCX
529 lwz r12, 12(r0)
530 lwz r11, 8(r0)
531 mtspr SPRN_PID, r12
532 mtcr r11
533 lwz r9, 4(r0)
534 lwz r12, 0(r0)
535 #else
536 mfspr r12, SPRN_SPRG_SCRATCH5
537 mfspr r11, SPRN_SPRG_SCRATCH6
538 mtspr SPRN_PID, r12
539 mtcr r11
540 mfspr r9, SPRN_SPRG_SCRATCH4
541 mfspr r12, SPRN_SPRG_SCRATCH3
542 #endif
543 mfspr r11, SPRN_SPRG_SCRATCH1
544 mfspr r10, SPRN_SPRG_SCRATCH0
545 b DataAccess
547 /* 0x1200 - Instruction TLB Miss Exception
548 * Nearly the same as above, except we get our information from different
549 * registers and bailout to a different point.
550 */
551 START_EXCEPTION(0x1200, ITLBMiss)
552 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
553 mtspr SPRN_SPRG_SCRATCH1, r11
554 #ifdef CONFIG_403GCX
555 stw r12, 0(r0)
556 stw r9, 4(r0)
557 mfcr r11
558 mfspr r12, SPRN_PID
559 stw r11, 8(r0)
560 stw r12, 12(r0)
561 #else
562 mtspr SPRN_SPRG_SCRATCH3, r12
563 mtspr SPRN_SPRG_SCRATCH4, r9
564 mfcr r11
565 mfspr r12, SPRN_PID
566 mtspr SPRN_SPRG_SCRATCH6, r11
567 mtspr SPRN_SPRG_SCRATCH5, r12
568 #endif
569 mfspr r10, SPRN_SRR0 /* Get faulting address */
571 /* If we are faulting a kernel address, we have to use the
572 * kernel page tables.
573 */
574 lis r11, PAGE_OFFSET@h
575 cmplw r10, r11
576 blt+ 3f
577 lis r11, swapper_pg_dir@h
578 ori r11, r11, swapper_pg_dir@l
579 li r9, 0
580 mtspr SPRN_PID, r9 /* TLB will have 0 TID */
581 b 4f
583 /* Get the PGD for the current thread.
584 */
585 3:
586 mfspr r11,SPRN_SPRG_THREAD
587 lwz r11,PGDIR(r11)
588 4:
589 tophys(r11, r11)
590 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
591 lwz r12, 0(r11) /* Get L1 entry */
592 andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
593 beq 2f /* Bail if no table */
595 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
596 lwz r11, 0(r12) /* Get Linux PTE */
597 andi. r9, r11, _PAGE_PRESENT
598 beq 5f
600 ori r11, r11, _PAGE_ACCESSED
601 stw r11, 0(r12)
603 /* Create TLB tag. This is the faulting address plus a static
604 * set of bits. These are size, valid, E, U0.
605 */
606 li r12, 0x00c0
607 rlwimi r10, r12, 0, 20, 31
609 b finish_tlb_load
611 2: /* Check for possible large-page pmd entry */
612 rlwinm. r9, r12, 2, 22, 24
613 beq 5f
615 /* Create TLB tag. This is the faulting address, plus a static
616 * set of bits (valid, E, U0) plus the size from the PMD.
617 */
618 ori r9, r9, 0x40
619 rlwimi r10, r9, 0, 20, 31
620 mr r11, r12
622 b finish_tlb_load
624 5:
625 /* The bailout. Restore registers to pre-exception conditions
626 * and call the heavyweights to help us out.
627 */
628 #ifdef CONFIG_403GCX
629 lwz r12, 12(r0)
630 lwz r11, 8(r0)
631 mtspr SPRN_PID, r12
632 mtcr r11
633 lwz r9, 4(r0)
634 lwz r12, 0(r0)
635 #else
636 mfspr r12, SPRN_SPRG_SCRATCH5
637 mfspr r11, SPRN_SPRG_SCRATCH6
638 mtspr SPRN_PID, r12
639 mtcr r11
640 mfspr r9, SPRN_SPRG_SCRATCH4
641 mfspr r12, SPRN_SPRG_SCRATCH3
642 #endif
643 mfspr r11, SPRN_SPRG_SCRATCH1
644 mfspr r10, SPRN_SPRG_SCRATCH0
645 b InstructionAccess
647 EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
648 EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE)
649 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
650 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
651 #ifdef CONFIG_IBM405_ERR51
652 /* 405GP errata 51 */
653 START_EXCEPTION(0x1700, Trap_17)
654 b DTLBMiss
655 #else
656 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
657 #endif
658 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
659 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
660 EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE)
661 EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE)
662 EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE)
663 EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE)
664 EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE)
665 EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE)
667 /* Check for a single step debug exception while in an exception
668 * handler before state has been saved. This is to catch the case
669 * where an instruction that we are trying to single step causes
670 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
671 * the exception handler generates a single step debug exception.
672 *
673 * If we get a debug trap on the first instruction of an exception handler,
674 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
675 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
676 * The exception handler was handling a non-critical interrupt, so it will
677 * save (and later restore) the MSR via SPRN_SRR1, which will still have
678 * the MSR_DE bit set.
679 */
680 /* 0x2000 - Debug Exception */
681 START_EXCEPTION(0x2000, DebugTrap)
682 CRITICAL_EXCEPTION_PROLOG
684 /*
685 * If this is a single step or branch-taken exception in an
686 * exception entry sequence, it was probably meant to apply to
687 * the code where the exception occurred (since exception entry
688 * doesn't turn off DE automatically). We simulate the effect
689 * of turning off DE on entry to an exception handler by turning
690 * off DE in the SRR3 value and clearing the debug status.
691 */
692 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
693 andis. r10,r10,DBSR_IC@h
694 beq+ 2f
696 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
697 beq 1f /* branch and fix it up */
699 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
700 cmplwi r10,0x2100
701 bgt+ 2f /* address above exception vectors */
703 /* here it looks like we got an inappropriate debug exception. */
704 1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */
705 lis r10,DBSR_IC@h /* clear the IC event */
706 mtspr SPRN_DBSR,r10
707 /* restore state and get out */
708 lwz r10,_CCR(r11)
709 lwz r0,GPR0(r11)
710 lwz r1,GPR1(r11)
711 mtcrf 0x80,r10
712 mtspr SPRN_SRR2,r12
713 mtspr SPRN_SRR3,r9
714 lwz r9,GPR9(r11)
715 lwz r12,GPR12(r11)
716 lwz r10,crit_r10@l(0)
717 lwz r11,crit_r11@l(0)
718 PPC405_ERR77_SYNC
719 rfci
720 b .
722 /* continue normal handling for a critical exception... */
723 2: mfspr r4,SPRN_DBSR
724 addi r3,r1,STACK_FRAME_OVERHEAD
725 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
726 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
727 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
729 /*
730 * The other Data TLB exceptions bail out to this point
731 * if they can't resolve the lightweight TLB fault.
732 */
733 DataAccess:
734 NORMAL_EXCEPTION_PROLOG
735 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
736 stw r5,_ESR(r11)
737 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
738 EXC_XFER_EE_LITE(0x300, handle_page_fault)
740 /* Other PowerPC processors, namely those derived from the 6xx-series
741 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
742 * However, for the 4xx-series processors these are neither defined nor
743 * reserved.
744 */
746 /* Damn, I came up one instruction too many to fit into the
747 * exception space :-). Both the instruction and data TLB
748 * miss get to this point to load the TLB.
749 * r10 - TLB_TAG value
750 * r11 - Linux PTE
751 * r12, r9 - avilable to use
752 * PID - loaded with proper value when we get here
753 * Upon exit, we reload everything and RFI.
754 * Actually, it will fit now, but oh well.....a common place
755 * to load the TLB.
756 */
757 tlb_4xx_index:
758 .long 0
759 finish_tlb_load:
760 /* load the next available TLB index.
761 */
762 lwz r9, tlb_4xx_index@l(0)
763 addi r9, r9, 1
764 andi. r9, r9, (PPC40X_TLB_SIZE-1)
765 stw r9, tlb_4xx_index@l(0)
767 6:
768 /*
769 * Clear out the software-only bits in the PTE to generate the
770 * TLB_DATA value. These are the bottom 2 bits of the RPM, the
771 * top 3 bits of the zone field, and M.
772 */
773 li r12, 0x0ce2
774 andc r11, r11, r12
776 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
777 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
779 /* Done...restore registers and get out of here.
780 */
781 #ifdef CONFIG_403GCX
782 lwz r12, 12(r0)
783 lwz r11, 8(r0)
784 mtspr SPRN_PID, r12
785 mtcr r11
786 lwz r9, 4(r0)
787 lwz r12, 0(r0)
788 #else
789 mfspr r12, SPRN_SPRG_SCRATCH5
790 mfspr r11, SPRN_SPRG_SCRATCH6
791 mtspr SPRN_PID, r12
792 mtcr r11
793 mfspr r9, SPRN_SPRG_SCRATCH4
794 mfspr r12, SPRN_SPRG_SCRATCH3
795 #endif
796 mfspr r11, SPRN_SPRG_SCRATCH1
797 mfspr r10, SPRN_SPRG_SCRATCH0
798 PPC405_ERR77_SYNC
799 rfi /* Should sync shadow TLBs */
800 b . /* prevent prefetch past rfi */
802 /* extern void giveup_fpu(struct task_struct *prev)
803 *
804 * The PowerPC 4xx family of processors do not have an FPU, so this just
805 * returns.
806 */
807 _ENTRY(giveup_fpu)
808 blr
810 /* This is where the main kernel code starts.
811 */
812 start_here:
814 /* ptr to current */
815 lis r2,init_task@h
816 ori r2,r2,init_task@l
818 /* ptr to phys current thread */
819 tophys(r4,r2)
820 addi r4,r4,THREAD /* init task's THREAD */
821 mtspr SPRN_SPRG_THREAD,r4
823 /* stack */
824 lis r1,init_thread_union@ha
825 addi r1,r1,init_thread_union@l
826 li r0,0
827 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
829 bl early_init /* We have to do this with MMU on */
831 /*
832 * Decide what sort of machine this is and initialize the MMU.
833 */
834 mr r3,r31
835 mr r4,r30
836 mr r5,r29
837 mr r6,r28
838 mr r7,r27
839 bl machine_init
840 bl MMU_init
842 /* Go back to running unmapped so we can load up new values
843 * and change to using our exception vectors.
844 * On the 4xx, all we have to do is invalidate the TLB to clear
845 * the old 16M byte TLB mappings.
846 */
847 lis r4,2f@h
848 ori r4,r4,2f@l
849 tophys(r4,r4)
850 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
851 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
852 mtspr SPRN_SRR0,r4
853 mtspr SPRN_SRR1,r3
854 rfi
855 b . /* prevent prefetch past rfi */
857 /* Load up the kernel context */
858 2:
859 sync /* Flush to memory before changing TLB */
860 tlbia
861 isync /* Flush shadow TLBs */
863 /* set up the PTE pointers for the Abatron bdiGDB.
864 */
865 lis r6, swapper_pg_dir@h
866 ori r6, r6, swapper_pg_dir@l
867 lis r5, abatron_pteptrs@h
868 ori r5, r5, abatron_pteptrs@l
869 stw r5, 0xf0(r0) /* Must match your Abatron config file */
870 tophys(r5,r5)
871 stw r6, 0(r5)
873 /* Now turn on the MMU for real! */
874 lis r4,MSR_KERNEL@h
875 ori r4,r4,MSR_KERNEL@l
876 lis r3,start_kernel@h
877 ori r3,r3,start_kernel@l
878 mtspr SPRN_SRR0,r3
879 mtspr SPRN_SRR1,r4
880 rfi /* enable MMU and jump to start_kernel */
881 b . /* prevent prefetch past rfi */
883 /* Set up the initial MMU state so we can do the first level of
884 * kernel initialization. This maps the first 16 MBytes of memory 1:1
885 * virtual to physical and more importantly sets the cache mode.
886 */
887 initial_mmu:
888 tlbia /* Invalidate all TLB entries */
889 isync
891 /* We should still be executing code at physical address 0x0000xxxx
892 * at this point. However, start_here is at virtual address
893 * 0xC000xxxx. So, set up a TLB mapping to cover this once
894 * translation is enabled.
895 */
897 lis r3,KERNELBASE@h /* Load the kernel virtual address */
898 ori r3,r3,KERNELBASE@l
899 tophys(r4,r3) /* Load the kernel physical address */
901 iccci r0,r3 /* Invalidate the i-cache before use */
903 /* Load the kernel PID.
904 */
905 li r0,0
906 mtspr SPRN_PID,r0
907 sync
909 /* Configure and load two entries into TLB slots 62 and 63.
910 * In case we are pinning TLBs, these are reserved in by the
911 * other TLB functions. If not reserving, then it doesn't
912 * matter where they are loaded.
913 */
914 clrrwi r4,r4,10 /* Mask off the real page number */
915 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
917 clrrwi r3,r3,10 /* Mask off the effective page number */
918 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
920 li r0,63 /* TLB slot 63 */
922 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
923 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
925 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
927 /* Load a TLB entry for the UART, so that ppc4xx_progress() can use
928 * the UARTs nice and early. We use a 4k real==virtual mapping. */
930 lis r3,SERIAL_DEBUG_IO_BASE@h
931 ori r3,r3,SERIAL_DEBUG_IO_BASE@l
932 mr r4,r3
933 clrrwi r4,r4,12
934 ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
936 clrrwi r3,r3,12
937 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
939 li r0,0 /* TLB slot 0 */
940 tlbwe r4,r0,TLB_DATA
941 tlbwe r3,r0,TLB_TAG
942 #endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
944 isync
946 /* Establish the exception vector base
947 */
948 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */
949 tophys(r0,r4) /* Use the physical address */
950 mtspr SPRN_EVPR,r0
952 blr
954 _GLOBAL(abort)
955 mfspr r13,SPRN_DBCR0
956 oris r13,r13,DBCR0_RST_SYSTEM@h
957 mtspr SPRN_DBCR0,r13
959 _GLOBAL(set_context)
961 #ifdef CONFIG_BDI_SWITCH
962 /* Context switch the PTE pointer for the Abatron BDI2000.
963 * The PGDIR is the second parameter.
964 */
965 lis r5, KERNELBASE@h
966 lwz r5, 0xf0(r5)
967 stw r4, 0x4(r5)
968 #endif
969 sync
970 mtspr SPRN_PID,r3
971 isync /* Need an isync to flush shadow */
972 /* TLBs after changing PID */
973 blr
975 /* We put a few things here that have to be page-aligned. This stuff
976 * goes at the beginning of the data segment, which is page-aligned.
977 */
978 .data
979 .align 12
980 .globl sdata
981 sdata:
982 .globl empty_zero_page
983 empty_zero_page:
984 .space 4096
985 .globl swapper_pg_dir
986 swapper_pg_dir:
987 .space PGD_TABLE_SIZE
989 /* Room for two PTE pointers, usually the kernel and current user pointers
990 * to their respective root page table.
991 */
992 abatron_pteptrs:
993 .space 8