release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/kernel_stat.h>
  26
  27 #include <asm/errno.h>
  28 #include <asm/signal.h>
  29 #include <asm/system.h>
  30 #include <asm/time.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/sibyte/sb1250_regs.h>
  34 #include <asm/sibyte/sb1250_int.h>
  35 #include <asm/sibyte/sb1250_uart.h>
  36 #include <asm/sibyte/sb1250_scd.h>
  37 #include <asm/sibyte/sb1250.h>
  38
  39 /*
  40  * These are the routines that handle all the low level interrupt stuff.
  41  * Actions handled here are: initialization of the interrupt map, requesting of
  42  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  43  * for interrupt lines
  44  */
  45
  46
  47 static void end_sb1250_irq(unsigned int irq);
  48 static void enable_sb1250_irq(unsigned int irq);
  49 static void disable_sb1250_irq(unsigned int irq);
  50 static void ack_sb1250_irq(unsigned int irq);
  51 #ifdef CONFIG_SMP
  52 static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
  53 #endif
  54
  55 #ifdef CONFIG_SIBYTE_HAS_LDT
  56 extern unsigned long ldt_eoi_space;
  57 #endif
  58
  59 static struct irq_chip sb1250_irq_type = {
  60         .name = "SB1250-IMR",
  61         .ack = ack_sb1250_irq,
  62         .mask = disable_sb1250_irq,
  63         .mask_ack = ack_sb1250_irq,
  64         .unmask = enable_sb1250_irq,
  65         .end = end_sb1250_irq,
  66 #ifdef CONFIG_SMP
  67         .set_affinity = sb1250_set_affinity
  68 #endif
  69 };
  70
  71 /* Store the CPU id (not the logical number) */
  72 int sb1250_irq_owner[SB1250_NR_IRQS];
  73
  74 static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
  75
  76 void sb1250_mask_irq(int cpu, int irq)
  77 {
  78         unsigned long flags;
  79         u64 cur_ints;
  80
  81         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
  82         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  83                                         R_IMR_INTERRUPT_MASK));
  84         cur_ints |= (((u64) 1) << irq);
  85         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  86                                         R_IMR_INTERRUPT_MASK));
  87         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  88 }
  89
  90 void sb1250_unmask_irq(int cpu, int irq)
  91 {
  92         unsigned long flags;
  93         u64 cur_ints;
  94
  95         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
  96         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  97                                         R_IMR_INTERRUPT_MASK));
  98         cur_ints &= ~(((u64) 1) << irq);
  99         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 100                                         R_IMR_INTERRUPT_MASK));
 101         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 102 }
 103
 104 #ifdef CONFIG_SMP
 105 static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
 106 {
 107         int i = 0, old_cpu, cpu, int_on;
 108         u64 cur_ints;
 109         unsigned long flags;
 110
 111         i = cpumask_first(mask);
 112
 113         /* Convert logical CPU to physical CPU */
 114         cpu = cpu_logical_map(i);
 115
 116         /* Protect against other affinity changers and IMR manipulation */
 117         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
 118
 119         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 120         old_cpu = sb1250_irq_owner[irq];
 121         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 122                                         R_IMR_INTERRUPT_MASK));
 123         int_on = !(cur_ints & (((u64) 1) << irq));
 124         if (int_on) {
 125                 /* If it was on, mask it */
 126                 cur_ints |= (((u64) 1) << irq);
 127                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 128                                         R_IMR_INTERRUPT_MASK));
 129         }
 130         sb1250_irq_owner[irq] = cpu;
 131         if (int_on) {
 132                 /* unmask for the new CPU */
 133                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 134                                         R_IMR_INTERRUPT_MASK));
 135                 cur_ints &= ~(((u64) 1) << irq);
 136                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 137                                         R_IMR_INTERRUPT_MASK));
 138         }
 139         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 140
 141         return 0;
 142 }
 143 #endif
 144
 145 /*****************************************************************************/
 146
 147 static void disable_sb1250_irq(unsigned int irq)
 148 {
 149         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 150 }
 151
 152 static void enable_sb1250_irq(unsigned int irq)
 153 {
 154         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 155 }
 156
 157
 158 static void ack_sb1250_irq(unsigned int irq)
 159 {
 160 #ifdef CONFIG_SIBYTE_HAS_LDT
 161         u64 pending;
 162
 163         /*
 164          * If the interrupt was an HT interrupt, now is the time to
 165          * clear it.  NOTE: we assume the HT bridge was set up to
 166          * deliver the interrupts to all CPUs (which makes affinity
 167          * changing easier for us)
 168          */
 169         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 170                                                     R_IMR_LDT_INTERRUPT)));
 171         pending &= ((u64)1 << (irq));
 172         if (pending) {
 173                 int i;
 174                 for (i=0; i<NR_CPUS; i++) {
 175                         int cpu;
 176 #ifdef CONFIG_SMP
 177                         cpu = cpu_logical_map(i);
 178 #else
 179                         cpu = i;
 180 #endif
 181                         /*
 182                          * Clear for all CPUs so an affinity switch
 183                          * doesn't find an old status
 184                          */
 185                         __raw_writeq(pending,
 186                                      IOADDR(A_IMR_REGISTER(cpu,
 187                                                 R_IMR_LDT_INTERRUPT_CLR)));
 188                 }
 189
 190                 /*
 191                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 192                  * Pass 2, the LDT world may be edge-triggered, but
 193                  * this EOI shouldn't hurt.  If they are
 194                  * level-sensitive, the EOI is required.
 195                  */
 196                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 197         }
 198 #endif
 199         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 200 }
 201
 202
 203 static void end_sb1250_irq(unsigned int irq)
 204 {
 205         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 206                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 207         }
 208 }
 209
 210
 211 void __init init_sb1250_irqs(void)
 212 {
 213         int i;
 214
 215         for (i = 0; i < SB1250_NR_IRQS; i++) {
 216                 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
 217                 sb1250_irq_owner[i] = 0;
 218         }
 219 }
 220
 221
 222 /*
 223  *  arch_init_irq is called early in the boot sequence from init/main.c via
 224  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 225  *  installing the handler that will be responsible for dispatching interrupts
 226  *  to the "right" place.
 227  */
 228 /*
 229  * For now, map all interrupts to IP[2].  We could save
 230  * some cycles by parceling out system interrupts to different
 231  * IP lines, but keep it simple for bringup.  We'll also direct
 232  * all interrupts to a single CPU; we should probably route
 233  * PCI and LDT to one cpu and everything else to the other
 234  * to balance the load a bit.
 235  *
 236  * On the second cpu, everything is set to IP5, which is
 237  * ignored, EXCEPT the mailbox interrupt.  That one is
 238  * set to IP[2] so it is handled.  This is needed so we
 239  * can do cross-cpu function calls, as required by SMP
 240  */
 241
 242 #define IMR_IP2_VAL     K_INT_MAP_I0
 243 #define IMR_IP3_VAL     K_INT_MAP_I1
 244 #define IMR_IP4_VAL     K_INT_MAP_I2
 245 #define IMR_IP5_VAL     K_INT_MAP_I3
 246 #define IMR_IP6_VAL     K_INT_MAP_I4
 247
 248 void __init arch_init_irq(void)
 249 {
 250
 251         unsigned int i;
 252         u64 tmp;
 253         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 254                 STATUSF_IP1 | STATUSF_IP0;
 255
 256         /* Default everything to IP2 */
 257         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 258                 __raw_writeq(IMR_IP2_VAL,
 259                              IOADDR(A_IMR_REGISTER(0,
 260                                                    R_IMR_INTERRUPT_MAP_BASE) +
 261                                     (i << 3)));
 262                 __raw_writeq(IMR_IP2_VAL,
 263                              IOADDR(A_IMR_REGISTER(1,
 264                                                    R_IMR_INTERRUPT_MAP_BASE) +
 265                                     (i << 3)));
 266         }
 267
 268         init_sb1250_irqs();
 269
 270         /*
 271          * Map the high 16 bits of the mailbox registers to IP[3], for
 272          * inter-cpu messages
 273          */
 274         /* Was I1 */
 275         __raw_writeq(IMR_IP3_VAL,
 276                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 277                             (K_INT_MBOX_0 << 3)));
 278         __raw_writeq(IMR_IP3_VAL,
 279                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 280                             (K_INT_MBOX_0 << 3)));
 281
 282         /* Clear the mailboxes.  The firmware may leave them dirty */
 283         __raw_writeq(0xffffffffffffffffULL,
 284                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 285         __raw_writeq(0xffffffffffffffffULL,
 286                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 287
 288         /* Mask everything except the mailbox registers for both cpus */
 289         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 290         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 291         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 292
 293         /*
 294          * Note that the timer interrupts are also mapped, but this is
 295          * done in sb1250_time_init().  Also, the profiling driver
 296          * does its own management of IP7.
 297          */
 298
 299         /* Enable necessary IPs, disable the rest */
 300         change_c0_status(ST0_IM, imask);
 301 }
 302
 303 extern void sb1250_mailbox_interrupt(void);
 304
 305 static inline void dispatch_ip2(void)
 306 {
 307         unsigned int cpu = smp_processor_id();
 308         unsigned long long mask;
 309
 310         /*
 311          * Default...we've hit an IP[2] interrupt, which means we've got to
 312          * check the 1250 interrupt registers to figure out what to do.  Need
 313          * to detect which CPU we're on, now that smp_affinity is supported.
 314          */
 315         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
 316                                   R_IMR_INTERRUPT_STATUS_BASE)));
 317         if (mask)
 318                 do_IRQ(fls64(mask) - 1);
 319 }
 320
 321 asmlinkage void plat_irq_dispatch(void)
 322 {
 323         unsigned int cpu = smp_processor_id();
 324         unsigned int pending;
 325
 326         /*
 327          * What a pain. We have to be really careful saving the upper 32 bits
 328          * of any * register across function calls if we don't want them
 329          * trashed--since were running in -o32, the calling routing never saves
 330          * the full 64 bits of a register across a function call.  Being the
 331          * interrupt handler, we're guaranteed that interrupts are disabled
 332          * during this code so we don't have to worry about random interrupts
 333          * blasting the high 32 bits.
 334          */
 335
 336         pending = read_c0_cause() & read_c0_status() & ST0_IM;
 337
 338         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
 339                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 340         else if (pending & CAUSEF_IP4)
 341                 do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 342
 343 #ifdef CONFIG_SMP
 344         else if (pending & CAUSEF_IP3)
 345                 sb1250_mailbox_interrupt();
 346 #endif
 347
 348         else if (pending & CAUSEF_IP2)
 349                 dispatch_ip2();
 350         else
 351                 spurious_interrupt();
 352 }