release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/pci/pci-ip27.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
   7  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/smp.h>
  14 #include <asm/sn/arch.h>
  15 #include <asm/pci/bridge.h>
  16 #include <asm/paccess.h>
  17 #include <asm/sn/intr.h>
  18 #include <asm/sn/sn0/hub.h>
  19
  20 /*
  21  * Max #PCI busses we can handle; ie, max #PCI bridges.
  22  */
  23 #define MAX_PCI_BUSSES          40
  24
  25 /*
  26  * Max #PCI devices (like scsi controllers) we handle on a bus.
  27  */
  28 #define MAX_DEVICES_PER_PCIBUS  8
  29
  30 static struct bridge_controller bridges[MAX_PCI_BUSSES];
  31
  32 /*
  33  * Translate from irq to software PCI bus number and PCI slot.
  34  */
  35 struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  36 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  37
  38 extern struct pci_ops bridge_pci_ops;
  39
  40 int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
  41 {
  42         unsigned long offset = NODE_OFFSET(nasid);
  43         struct bridge_controller *bc;
  44         static int num_bridges = 0;
  45         bridge_t *bridge;
  46         int slot;
  47
  48         pci_probe_only = 1;
  49
  50         printk("a bridge\n");
  51
  52         if (!num_bridges)
  53                 ioport_resource.end = ~0UL;
  54
  55         bc = &bridges[num_bridges];
  56
  57         bc->pc.pci_ops          = &bridge_pci_ops;
  58         bc->pc.mem_resource     = &bc->mem;
  59         bc->pc.io_resource      = &bc->io;
  60
  61         bc->pc.index            = num_bridges;
  62
  63         bc->mem.name            = "Bridge PCI MEM";
  64         bc->pc.mem_offset       = offset;
  65         bc->mem.start           = 0;
  66         bc->mem.end             = ~0UL;
  67         bc->mem.flags           = IORESOURCE_MEM;
  68
  69         bc->io.name             = "Bridge IO MEM";
  70         bc->pc.io_offset        = offset;
  71         bc->io.start            = 0UL;
  72         bc->io.end              = ~0UL;
  73         bc->io.flags            = IORESOURCE_IO;
  74
  75         bc->irq_cpu = smp_processor_id();
  76         bc->widget_id = widget_id;
  77         bc->nasid = nasid;
  78
  79         bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
  80
  81         /*
  82          * point to this bridge
  83          */
  84         bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
  85
  86         /*
  87          * Clear all pending interrupts.
  88          */
  89         bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
  90
  91         /*
  92          * Until otherwise set up, assume all interrupts are from slot 0
  93          */
  94         bridge->b_int_device = 0x0;
  95
  96         /*
  97          * swap pio's to pci mem and io space (big windows)
  98          */
  99         bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
 100                                  BRIDGE_CTRL_MEM_SWAP;
 101 #ifdef CONFIG_PAGE_SIZE_4KB
 102         bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
 103 #else /* 16kB or larger */
 104         bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
 105 #endif
 106
 107         /*
 108          * Hmm...  IRIX sets additional bits in the address which
 109          * are documented as reserved in the bridge docs.
 110          */
 111         bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
 112         bridge->b_wid_int_lower = 0x01800090;   /* PI_INT_PEND_MOD off*/
 113         bridge->b_dir_map = (masterwid << 20);  /* DMA */
 114         bridge->b_int_enable = 0;
 115
 116         for (slot = 0; slot < 8; slot ++) {
 117                 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 118                 bc->pci_int[slot] = -1;
 119         }
 120         bridge->b_wid_tflush;     /* wait until Bridge PIO complete */
 121
 122         bc->base = bridge;
 123
 124         register_pci_controller(&bc->pc);
 125
 126         num_bridges++;
 127
 128         return 0;
 129 }
 130
 131 /*
 132  * All observed requests have pin == 1. We could have a global here, that
 133  * gets incremented and returned every time - unfortunately, pci_map_irq
 134  * may be called on the same device over and over, and need to return the
 135  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
 136  *
 137  * A given PCI device, in general, should be able to intr any of the cpus
 138  * on any one of the hubs connected to its xbow.
 139  */
 140 int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 141 {
 142         return 0;
 143 }
 144
 145 static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
 146 {
 147         while (dev->bus->parent) {
 148                 /* Move up the chain of bridges. */
 149                 dev = dev->bus->self;
 150         }
 151
 152         return dev;
 153 }
 154
 155 /* Do platform specific device initialization at pci_enable_device() time */
 156 int pcibios_plat_dev_init(struct pci_dev *dev)
 157 {
 158         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 159         struct pci_dev *rdev = bridge_root_dev(dev);
 160         int slot = PCI_SLOT(rdev->devfn);
 161         int irq;
 162
 163         irq = bc->pci_int[slot];
 164         if (irq == -1) {
 165                 irq = request_bridge_irq(bc);
 166                 if (irq < 0)
 167                         return irq;
 168
 169                 bc->pci_int[slot] = irq;
 170         }
 171
 172         irq_to_bridge[irq] = bc;
 173         irq_to_slot[irq] = slot;
 174
 175         dev->irq = irq;
 176
 177         return 0;
 178 }
 179
 180
 181 static inline void pci_disable_swapping(struct pci_dev *dev)
 182 {
 183         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 184         bridge_t *bridge = bc->base;
 185         int slot = PCI_SLOT(dev->devfn);
 186
 187         /* Turn off byte swapping */
 188         bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
 189         bridge->b_widget.w_tflush;      /* Flush */
 190 }
 191
 192 static inline void pci_enable_swapping(struct pci_dev *dev)
 193 {
 194         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 195         bridge_t *bridge = bc->base;
 196         int slot = PCI_SLOT(dev->devfn);
 197
 198         /* Turn on byte swapping */
 199         bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 200         bridge->b_widget.w_tflush;      /* Flush */
 201 }
 202
 203 static void __init pci_fixup_ioc3(struct pci_dev *d)
 204 {
 205         pci_disable_swapping(d);
 206 }
 207
 208 int pcibus_to_node(struct pci_bus *bus)
 209 {
 210         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 211
 212         return bc->nasid;
 213 }
 214 EXPORT_SYMBOL(pcibus_to_node);
 215
 216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
 217         pci_fixup_ioc3);