release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/pci/ops-mace.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000, 2001 Keith M Wesolowski
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/pci.h>
  11 #include <linux/types.h>
  12 #include <asm/pci.h>
  13 #include <asm/ip32/mace.h>
  14
  15 # define DPRINTK(args...)
  16
  17 /*
  18  * O2 has up to 5 PCI devices connected into the MACE bridge.  The device
  19  * map looks like this:
  20  *
  21  * 0  aic7xxx 0
  22  * 1  aic7xxx 1
  23  * 2  expansion slot
  24  * 3  N/C
  25  * 4  N/C
  26  */
  27
  28 static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
  29         unsigned int reg)
  30 {
  31         return ((bus->number & 0xff) << 16) |
  32                 ((devfn & 0xff) << 8) |
  33                 (reg & 0xfc);
  34 }
  35
  36
  37 static int
  38 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  39                      int reg, int size, u32 *val)
  40 {
  41         u32 control = mace->pci.control;
  42
  43         /* disable master aborts interrupts during config read */
  44         mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
  45         mace->pci.config_addr = mkaddr(bus, devfn, reg);
  46         switch (size) {
  47         case 1:
  48                 *val = mace->pci.config_data.b[(reg & 3) ^ 3];
  49                 break;
  50         case 2:
  51                 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
  52                 break;
  53         case 4:
  54                 *val = mace->pci.config_data.l;
  55                 break;
  56         }
  57         /* ack possible master abort */
  58         mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
  59         mace->pci.control = control;
  60         /*
  61          * someone forgot to set the ultra bit for the onboard
  62          * scsi chips; we fake it here
  63          */
  64         if (bus->number == 0 && reg == 0x40 && size == 4 &&
  65             (devfn == (1 << 3) || devfn == (2 << 3)))
  66                 *val |= 0x1000;
  67
  68         DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
  69
  70         return PCIBIOS_SUCCESSFUL;
  71 }
  72
  73 static int
  74 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  75                       int reg, int size, u32 val)
  76 {
  77         mace->pci.config_addr = mkaddr(bus, devfn, reg);
  78         switch (size) {
  79         case 1:
  80                 mace->pci.config_data.b[(reg & 3) ^ 3] = val;
  81                 break;
  82         case 2:
  83                 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
  84                 break;
  85         case 4:
  86                 mace->pci.config_data.l = val;
  87                 break;
  88         }
  89
  90         DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
  91
  92         return PCIBIOS_SUCCESSFUL;
  93 }
  94
  95 struct pci_ops mace_pci_ops = {
  96         .read = mace_pci_read_config,
  97         .write = mace_pci_write_config,
  98 };