release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-malta/malta-setup.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   4  * Copyright (C) 2008 Dmitri Vorobiev
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  */
  19 #include <linux/cpu.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/pci.h>
  25 #include <linux/screen_info.h>
  26 #include <linux/time.h>
  27
  28 #include <asm/bootinfo.h>
  29 #include <asm/mips-boards/generic.h>
  30 #include <asm/mips-boards/prom.h>
  31 #include <asm/mips-boards/malta.h>
  32 #include <asm/mips-boards/maltaint.h>
  33 #include <asm/dma.h>
  34 #include <asm/traps.h>
  35 #include <asm/gcmpregs.h>
  36 #ifdef CONFIG_VT
  37 #include <linux/console.h>
  38 #endif
  39
  40 extern void malta_be_init(void);
  41 extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
  42
  43 static struct resource standard_io_resources[] = {
  44         {
  45                 .name = "dma1",
  46                 .start = 0x00,
  47                 .end = 0x1f,
  48                 .flags = IORESOURCE_BUSY
  49         },
  50         {
  51                 .name = "timer",
  52                 .start = 0x40,
  53                 .end = 0x5f,
  54                 .flags = IORESOURCE_BUSY
  55         },
  56         {
  57                 .name = "keyboard",
  58                 .start = 0x60,
  59                 .end = 0x6f,
  60                 .flags = IORESOURCE_BUSY
  61         },
  62         {
  63                 .name = "dma page reg",
  64                 .start = 0x80,
  65                 .end = 0x8f,
  66                 .flags = IORESOURCE_BUSY
  67         },
  68         {
  69                 .name = "dma2",
  70                 .start = 0xc0,
  71                 .end = 0xdf,
  72                 .flags = IORESOURCE_BUSY
  73         },
  74 };
  75
  76 const char *get_system_type(void)
  77 {
  78         return "MIPS Malta";
  79 }
  80
  81 #if defined(CONFIG_MIPS_MT_SMTC)
  82 const char display_string[] = "       SMTC LINUX ON MALTA       ";
  83 #else
  84 const char display_string[] = "        LINUX ON MALTA       ";
  85 #endif /* CONFIG_MIPS_MT_SMTC */
  86
  87 #ifdef CONFIG_BLK_DEV_FD
  88 static void __init fd_activate(void)
  89 {
  90         /*
  91          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  92          * Controller.
  93          * Done by YAMON 2.00 onwards
  94          */
  95         /* Entering config state. */
  96         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  97
  98         /* Activate floppy controller. */
  99         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
 100         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
 101         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
 102         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
 103
 104         /* Exit config state. */
 105         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
 106 }
 107 #endif
 108
 109 int coherentio = -1;    /* no DMA cache coherency (may be set by user) */
 110 int hw_coherentio;      /* init to 0 => no HW DMA cache coherency (reflects real HW) */
 111 static int __init setcoherentio(char *str)
 112 {
 113         if (coherentio < 0)
 114                 pr_info("Command line checking done before"
 115                                 " plat_setup_iocoherency!!\n");
 116         if (coherentio == 0)
 117                 pr_info("Command line enabling coherentio"
 118                                 " (this will break...)!!\n");
 119
 120         coherentio = 1;
 121         pr_info("Hardware DMA cache coherency (command line)\n");
 122         return 1;
 123 }
 124 __setup("coherentio", setcoherentio);
 125
 126 static int __init setnocoherentio(char *str)
 127 {
 128         if (coherentio < 0)
 129                 pr_info("Command line checking done before"
 130                                 " plat_setup_iocoherency!!\n");
 131         if (coherentio == 1)
 132                 pr_info("Command line disabling coherentio\n");
 133
 134         coherentio = 0;
 135         pr_info("Software DMA cache coherency (command line)\n");
 136         return 1;
 137 }
 138 __setup("nocoherentio", setnocoherentio);
 139
 140 static int __init
 141 plat_enable_iocoherency(void)
 142 {
 143         int supported = 0;
 144         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
 145                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 146                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 147                         pr_info("Enabled Bonito CPU coherency\n");
 148                         supported = 1;
 149                 }
 150                 if (strstr(prom_getcmdline(), "iobcuncached")) {
 151                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 152                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 153                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 154                                   BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 155                         pr_info("Disabled Bonito IOBC coherency\n");
 156                 } else {
 157                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 158                         BONITO_PCIMEMBASECFG |=
 159                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 160                                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 161                         pr_info("Enabled Bonito IOBC coherency\n");
 162                 }
 163         } else if (gcmp_niocu() != 0) {
 164                 /* Nothing special needs to be done to enable coherency */
 165                 pr_info("CMP IOCU detected\n");
 166                 if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
 167                         pr_crit("IOCU OPERATION DISABLED BY SWITCH"
 168                                 " - DEFAULTING TO SW IO COHERENCY\n");
 169                         return 0;
 170                 }
 171                 supported = 1;
 172         }
 173         hw_coherentio = supported;
 174         return supported;
 175 }
 176
 177 static void __init
 178 plat_setup_iocoherency(void)
 179 {
 180 #ifdef CONFIG_DMA_NONCOHERENT
 181         /*
 182          * Kernel has been configured with software coherency
 183          * but we might choose to turn it off
 184          */
 185         if (plat_enable_iocoherency()) {
 186                 if (coherentio == 0)
 187                         pr_info("Hardware DMA cache coherency supported"
 188                                         " but disabled from command line\n");
 189                 else {
 190                         coherentio = 1;
 191                         printk(KERN_INFO "Hardware DMA cache coherency\n");
 192                 }
 193         } else {
 194                 if (coherentio == 1)
 195                         pr_info("Hardware DMA cache coherency not supported"
 196                                 " but enabled from command line\n");
 197                 else {
 198                         coherentio = 0;
 199                         pr_info("Software DMA cache coherency\n");
 200                 }
 201         }
 202 #else
 203         if (!plat_enable_iocoherency())
 204                 panic("Hardware DMA cache coherency not supported");
 205 #endif
 206 }
 207
 208 #ifdef CONFIG_BLK_DEV_IDE
 209 static void __init pci_clock_check(void)
 210 {
 211         unsigned int __iomem *jmpr_p =
 212                 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
 213         int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
 214         static const int pciclocks[] __initdata = {
 215                 33, 20, 25, 30, 12, 16, 37, 10
 216         };
 217         int pciclock = pciclocks[jmpr];
 218         char *argptr = prom_getcmdline();
 219
 220         if (pciclock != 33 && !strstr(argptr, "idebus=")) {
 221                 printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
 222                                 "setting idebus\n", pciclock);
 223                 argptr += strlen(argptr);
 224                 sprintf(argptr, " idebus=%d", pciclock);
 225                 if (pciclock < 20 || pciclock > 66)
 226                         printk(KERN_WARNING "WARNING: IDE timing "
 227                                         "calculations will be incorrect\n");
 228         }
 229 }
 230 #endif
 231
 232 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 233 static void __init screen_info_setup(void)
 234 {
 235         screen_info = (struct screen_info) {
 236                 .orig_x = 0,
 237                 .orig_y = 25,
 238                 .ext_mem_k = 0,
 239                 .orig_video_page = 0,
 240                 .orig_video_mode = 0,
 241                 .orig_video_cols = 80,
 242                 .unused2 = 0,
 243                 .orig_video_ega_bx = 0,
 244                 .unused3 = 0,
 245                 .orig_video_lines = 25,
 246                 .orig_video_isVGA = VIDEO_TYPE_VGAC,
 247                 .orig_video_points = 16
 248         };
 249 }
 250 #endif
 251
 252 static void __init bonito_quirks_setup(void)
 253 {
 254         char *argptr;
 255
 256         argptr = prom_getcmdline();
 257         if (strstr(argptr, "debug")) {
 258                 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
 259                 printk(KERN_INFO "Enabled Bonito debug mode\n");
 260         } else
 261                 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 262
 263 #ifdef CONFIG_DMA_COHERENT
 264         if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 265                 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 266                 printk(KERN_INFO "Enabled Bonito CPU coherency\n");
 267
 268                 argptr = prom_getcmdline();
 269                 if (strstr(argptr, "iobcuncached")) {
 270                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 271                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 272                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 273                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 274                         printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
 275                 } else {
 276                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 277                         BONITO_PCIMEMBASECFG |=
 278                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 279                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 280                         printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
 281                 }
 282         } else
 283                 panic("Hardware DMA cache coherency not supported");
 284 #endif
 285 }
 286
 287 void __init plat_mem_setup(void)
 288 {
 289         unsigned int i;
 290
 291         mips_pcibios_init();
 292
 293         /* Request I/O space for devices used on the Malta board. */
 294         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 295                 request_resource(&ioport_resource, standard_io_resources+i);
 296
 297         /*
 298          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
 299          */
 300         enable_dma(4);
 301
 302 #ifdef CONFIG_DMA_COHERENT
 303         if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
 304                 panic("Hardware DMA cache coherency not supported");
 305 #endif
 306
 307         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
 308                 bonito_quirks_setup();
 309
 310         plat_setup_iocoherency();
 311
 312 #ifdef CONFIG_BLK_DEV_IDE
 313         pci_clock_check();
 314 #endif
 315
 316 #ifdef CONFIG_BLK_DEV_FD
 317         fd_activate();
 318 #endif
 319
 320 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 321         screen_info_setup();
 322 #endif
 323
 324         board_be_init = malta_be_init;
 325         board_be_handler = malta_be_handler;
 326 }
 327 /* Enable PCI 2.1 compatibility in PIIX4 */
 328 static void __init quirk_dlcsetup(struct pci_dev *dev)
 329 {
 330         u8 odlc, ndlc;
 331         (void) pci_read_config_byte(dev, 0x82, &odlc);
 332         /* Enable passive releases and delayed transaction */
 333         ndlc = odlc | 7;
 334         (void) pci_write_config_byte(dev, 0x82, ndlc);
 335 }
 336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
 337                 quirk_dlcsetup);