2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
18 #include <linux/module.h>
19 #include <linux/bitops.h>
21 #include <asm/bcache.h>
22 #include <asm/bootinfo.h>
23 #include <asm/cache.h>
24 #include <asm/cacheops.h>
26 #include <asm/cpu-features.h>
29 #include <asm/pgtable.h>
30 #include <asm/r4kcache.h>
31 #include <asm/sections.h>
32 #include <asm/system.h>
33 #include <asm/mmu_context.h>
35 #include <asm/cacheflush.h> /* for run_uncached() */
39 * Special Variant of smp_call_function for use by cache functions:
42 * o collapses to normal function call on UP kernels
43 * o collapses to normal function call on systems with a single shared
46 static inline void r4k_on_each_cpu(void (*func
) (void *info
), void *info
,
51 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
52 smp_call_function(func
, info
, wait
);
58 #if defined(CONFIG_MIPS_CMP)
59 #define cpu_has_safe_index_cacheops 0
61 #define cpu_has_safe_index_cacheops 1
67 static unsigned long icache_size __read_mostly
;
68 static unsigned long dcache_size __read_mostly
;
69 static unsigned long scache_size __read_mostly
;
72 * Dummy cache handling routines for machines without boardcaches
74 static void cache_noop(void) {}
76 static struct bcache_ops no_sc_ops
= {
77 .bc_enable
= (void *)cache_noop
,
78 .bc_disable
= (void *)cache_noop
,
79 .bc_wback_inv
= (void *)cache_noop
,
80 .bc_inv
= (void *)cache_noop
83 struct bcache_ops
*bcops
= &no_sc_ops
;
85 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
86 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
88 #define R4600_HIT_CACHEOP_WAR_IMPL \
90 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
91 *(volatile unsigned long *)CKSEG1; \
92 if (R4600_V1_HIT_CACHEOP_WAR) \
93 __asm__ __volatile__("nop;nop;nop;nop"); \
96 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
98 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
100 R4600_HIT_CACHEOP_WAR_IMPL
;
101 blast_dcache32_page(addr
);
104 static inline void r4k_blast_dcache_page_dc64(unsigned long addr
)
106 R4600_HIT_CACHEOP_WAR_IMPL
;
107 blast_dcache64_page(addr
);
110 static void __cpuinit
r4k_blast_dcache_page_setup(void)
112 unsigned long dc_lsize
= cpu_dcache_line_size();
115 r4k_blast_dcache_page
= (void *)cache_noop
;
116 else if (dc_lsize
== 16)
117 r4k_blast_dcache_page
= blast_dcache16_page
;
118 else if (dc_lsize
== 32)
119 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
120 else if (dc_lsize
== 64)
121 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc64
;
124 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
126 static void __cpuinit
r4k_blast_dcache_page_indexed_setup(void)
128 unsigned long dc_lsize
= cpu_dcache_line_size();
131 r4k_blast_dcache_page_indexed
= (void *)cache_noop
;
132 else if (dc_lsize
== 16)
133 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
134 else if (dc_lsize
== 32)
135 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
136 else if (dc_lsize
== 64)
137 r4k_blast_dcache_page_indexed
= blast_dcache64_page_indexed
;
140 static void (* r4k_blast_dcache
)(void);
142 static void __cpuinit
r4k_blast_dcache_setup(void)
144 unsigned long dc_lsize
= cpu_dcache_line_size();
147 r4k_blast_dcache
= (void *)cache_noop
;
148 else if (dc_lsize
== 16)
149 r4k_blast_dcache
= blast_dcache16
;
150 else if (dc_lsize
== 32)
151 r4k_blast_dcache
= blast_dcache32
;
152 else if (dc_lsize
== 64)
153 r4k_blast_dcache
= blast_dcache64
;
156 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
157 #define JUMP_TO_ALIGN(order) \
158 __asm__ __volatile__( \
160 ".align\t" #order "\n\t" \
163 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
164 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
166 static inline void blast_r4600_v1_icache32(void)
170 local_irq_save(flags
);
172 local_irq_restore(flags
);
175 static inline void tx49_blast_icache32(void)
177 unsigned long start
= INDEX_BASE
;
178 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
179 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
180 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
181 current_cpu_data
.icache
.waybit
;
182 unsigned long ws
, addr
;
184 CACHE32_UNROLL32_ALIGN2
;
185 /* I'm in even chunk. blast odd chunks */
186 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
187 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
188 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
189 CACHE32_UNROLL32_ALIGN
;
190 /* I'm in odd chunk. blast even chunks */
191 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
192 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
193 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
196 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
200 local_irq_save(flags
);
201 blast_icache32_page_indexed(page
);
202 local_irq_restore(flags
);
205 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
207 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
208 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
209 unsigned long end
= start
+ PAGE_SIZE
;
210 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
211 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
212 current_cpu_data
.icache
.waybit
;
213 unsigned long ws
, addr
;
215 CACHE32_UNROLL32_ALIGN2
;
216 /* I'm in even chunk. blast odd chunks */
217 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
218 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
219 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
220 CACHE32_UNROLL32_ALIGN
;
221 /* I'm in odd chunk. blast even chunks */
222 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
223 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
224 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
227 static void (* r4k_blast_icache_page
)(unsigned long addr
);
229 static void __cpuinit
r4k_blast_icache_page_setup(void)
231 unsigned long ic_lsize
= cpu_icache_line_size();
234 r4k_blast_icache_page
= (void *)cache_noop
;
235 else if (ic_lsize
== 16)
236 r4k_blast_icache_page
= blast_icache16_page
;
237 else if (ic_lsize
== 32)
238 r4k_blast_icache_page
= blast_icache32_page
;
239 else if (ic_lsize
== 64)
240 r4k_blast_icache_page
= blast_icache64_page
;
244 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
246 static void __cpuinit
r4k_blast_icache_page_indexed_setup(void)
248 unsigned long ic_lsize
= cpu_icache_line_size();
251 r4k_blast_icache_page_indexed
= (void *)cache_noop
;
252 else if (ic_lsize
== 16)
253 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
254 else if (ic_lsize
== 32) {
255 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
256 r4k_blast_icache_page_indexed
=
257 blast_icache32_r4600_v1_page_indexed
;
258 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
259 r4k_blast_icache_page_indexed
=
260 tx49_blast_icache32_page_indexed
;
262 r4k_blast_icache_page_indexed
=
263 blast_icache32_page_indexed
;
264 } else if (ic_lsize
== 64)
265 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
268 static void (* r4k_blast_icache
)(void);
270 static void __cpuinit
r4k_blast_icache_setup(void)
272 unsigned long ic_lsize
= cpu_icache_line_size();
275 r4k_blast_icache
= (void *)cache_noop
;
276 else if (ic_lsize
== 16)
277 r4k_blast_icache
= blast_icache16
;
278 else if (ic_lsize
== 32) {
279 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
280 r4k_blast_icache
= blast_r4600_v1_icache32
;
281 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
282 r4k_blast_icache
= tx49_blast_icache32
;
284 r4k_blast_icache
= blast_icache32
;
285 } else if (ic_lsize
== 64)
286 r4k_blast_icache
= blast_icache64
;
289 static void (* r4k_blast_scache_page
)(unsigned long addr
);
291 static void __cpuinit
r4k_blast_scache_page_setup(void)
293 unsigned long sc_lsize
= cpu_scache_line_size();
295 if (scache_size
== 0)
296 r4k_blast_scache_page
= (void *)cache_noop
;
297 else if (sc_lsize
== 16)
298 r4k_blast_scache_page
= blast_scache16_page
;
299 else if (sc_lsize
== 32)
300 r4k_blast_scache_page
= blast_scache32_page
;
301 else if (sc_lsize
== 64)
302 r4k_blast_scache_page
= blast_scache64_page
;
303 else if (sc_lsize
== 128)
304 r4k_blast_scache_page
= blast_scache128_page
;
307 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
309 static void __cpuinit
r4k_blast_scache_page_indexed_setup(void)
311 unsigned long sc_lsize
= cpu_scache_line_size();
313 if (scache_size
== 0)
314 r4k_blast_scache_page_indexed
= (void *)cache_noop
;
315 else if (sc_lsize
== 16)
316 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
317 else if (sc_lsize
== 32)
318 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
319 else if (sc_lsize
== 64)
320 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
321 else if (sc_lsize
== 128)
322 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
325 static void (* r4k_blast_scache
)(void);
327 static void __cpuinit
r4k_blast_scache_setup(void)
329 unsigned long sc_lsize
= cpu_scache_line_size();
331 if (scache_size
== 0)
332 r4k_blast_scache
= (void *)cache_noop
;
333 else if (sc_lsize
== 16)
334 r4k_blast_scache
= blast_scache16
;
335 else if (sc_lsize
== 32)
336 r4k_blast_scache
= blast_scache32
;
337 else if (sc_lsize
== 64)
338 r4k_blast_scache
= blast_scache64
;
339 else if (sc_lsize
== 128)
340 r4k_blast_scache
= blast_scache128
;
343 static inline void local_r4k___flush_cache_all(void * args
)
345 #if defined(CONFIG_CPU_LOONGSON2)
352 switch (current_cpu_type()) {
364 static void r4k___flush_cache_all(void)
366 r4k_on_each_cpu(local_r4k___flush_cache_all
, NULL
, 1);
369 static inline int has_valid_asid(const struct mm_struct
*mm
)
371 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
374 for_each_online_cpu(i
)
375 if (cpu_context(i
, mm
))
380 return cpu_context(smp_processor_id(), mm
);
384 static void r4k__flush_cache_vmap(void)
389 static void r4k__flush_cache_vunmap(void)
394 static inline void local_r4k_flush_cache_range(void * args
)
396 struct vm_area_struct
*vma
= args
;
397 int exec
= vma
->vm_flags
& VM_EXEC
;
399 if (!(has_valid_asid(vma
->vm_mm
)))
407 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
408 unsigned long start
, unsigned long end
)
410 int exec
= vma
->vm_flags
& VM_EXEC
;
412 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
))
413 r4k_on_each_cpu(local_r4k_flush_cache_range
, vma
, 1);
416 static inline void local_r4k_flush_cache_mm(void * args
)
418 struct mm_struct
*mm
= args
;
420 if (!has_valid_asid(mm
))
424 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
425 * only flush the primary caches but R10000 and R12000 behave sane ...
426 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
427 * caches, so we can bail out early.
429 if (current_cpu_type() == CPU_R4000SC
||
430 current_cpu_type() == CPU_R4000MC
||
431 current_cpu_type() == CPU_R4400SC
||
432 current_cpu_type() == CPU_R4400MC
) {
440 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
442 if (!cpu_has_dc_aliases
)
445 r4k_on_each_cpu(local_r4k_flush_cache_mm
, mm
, 1);
448 struct flush_cache_page_args
{
449 struct vm_area_struct
*vma
;
454 static inline void local_r4k_flush_cache_page(void *args
)
456 struct flush_cache_page_args
*fcp_args
= args
;
457 struct vm_area_struct
*vma
= fcp_args
->vma
;
458 unsigned long addr
= fcp_args
->addr
;
459 struct page
*page
= pfn_to_page(fcp_args
->pfn
);
460 int exec
= vma
->vm_flags
& VM_EXEC
;
461 struct mm_struct
*mm
= vma
->vm_mm
;
462 int map_coherent
= 0;
470 * If ownes no valid ASID yet, cannot possibly have gotten
471 * this page into the cache.
473 if (!has_valid_asid(mm
))
477 pgdp
= pgd_offset(mm
, addr
);
478 pudp
= pud_offset(pgdp
, addr
);
479 pmdp
= pmd_offset(pudp
, addr
);
480 ptep
= pte_offset(pmdp
, addr
);
483 * If the page isn't marked valid, the page cannot possibly be
486 if (!(pte_present(*ptep
)))
489 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
))
493 * Use kmap_coherent or kmap_atomic to do flushes for
494 * another ASID than the current one.
496 map_coherent
= (cpu_has_dc_aliases
&&
497 page_mapped(page
) && !Page_dcache_dirty(page
));
499 vaddr
= kmap_coherent(page
, addr
);
501 vaddr
= kmap_atomic(page
, KM_USER0
);
502 addr
= (unsigned long)vaddr
;
505 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
506 r4k_blast_dcache_page(addr
);
507 if (exec
&& !cpu_icache_snoops_remote_store
)
508 r4k_blast_scache_page(addr
);
511 if (vaddr
&& cpu_has_vtag_icache
&& mm
== current
->active_mm
) {
512 int cpu
= smp_processor_id();
514 if (cpu_context(cpu
, mm
) != 0)
515 drop_mmu_context(mm
, cpu
);
517 r4k_blast_icache_page(addr
);
524 kunmap_atomic(vaddr
, KM_USER0
);
528 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
529 unsigned long addr
, unsigned long pfn
)
531 struct flush_cache_page_args args
;
537 r4k_on_each_cpu(local_r4k_flush_cache_page
, &args
, 1);
538 if (cpu_has_dc_aliases
)
539 ClearPageDcacheDirty(pfn_to_page(pfn
));
542 static inline void local_r4k_flush_data_cache_page(void * addr
)
544 r4k_blast_dcache_page((unsigned long) addr
);
547 static void r4k_flush_data_cache_page(unsigned long addr
)
550 local_r4k_flush_data_cache_page((void *)addr
);
552 r4k_on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
,
556 struct flush_icache_range_args
{
561 static inline void local_r4k_flush_icache_range(unsigned long start
, unsigned long end
)
563 if (!cpu_has_ic_fills_f_dc
) {
564 if (end
- start
>= dcache_size
) {
567 R4600_HIT_CACHEOP_WAR_IMPL
;
568 protected_blast_dcache_range(start
, end
);
572 if (end
- start
> icache_size
)
575 protected_blast_icache_range(start
, end
);
578 static inline void local_r4k_flush_icache_range_ipi(void *args
)
580 struct flush_icache_range_args
*fir_args
= args
;
581 unsigned long start
= fir_args
->start
;
582 unsigned long end
= fir_args
->end
;
584 local_r4k_flush_icache_range(start
, end
);
587 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
589 struct flush_icache_range_args args
;
594 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi
, &args
, 1);
595 instruction_hazard();
598 #ifdef CONFIG_DMA_NONCOHERENT
600 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
602 /* Catch bad driver code */
605 if (cpu_has_inclusive_pcaches
) {
606 if (size
>= scache_size
)
609 blast_scache_range(addr
, addr
+ size
);
614 * Either no secondary cache or the available caches don't have the
615 * subset property so we have to flush the primary caches
618 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
621 R4600_HIT_CACHEOP_WAR_IMPL
;
622 blast_dcache_range(addr
, addr
+ size
);
625 bc_wback_inv(addr
, size
);
628 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
630 /* Catch bad driver code */
633 if (cpu_has_inclusive_pcaches
) {
634 if (size
>= scache_size
)
637 unsigned long lsize
= cpu_scache_line_size();
638 unsigned long almask
= ~(lsize
- 1);
641 * There is no clearly documented alignment requirement
642 * for the cache instruction on MIPS processors and
643 * some processors, among them the RM5200 and RM7000
644 * QED processors will throw an address error for cache
645 * hit ops with insufficient alignment. Solved by
646 * aligning the address to cache line size.
648 cache_op(Hit_Writeback_Inv_SD
, addr
& almask
);
649 cache_op(Hit_Writeback_Inv_SD
,
650 (addr
+ size
- 1) & almask
);
651 blast_inv_scache_range(addr
, addr
+ size
);
656 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
659 unsigned long lsize
= cpu_dcache_line_size();
660 unsigned long almask
= ~(lsize
- 1);
662 R4600_HIT_CACHEOP_WAR_IMPL
;
663 cache_op(Hit_Writeback_Inv_D
, addr
& almask
);
664 cache_op(Hit_Writeback_Inv_D
, (addr
+ size
- 1) & almask
);
665 blast_inv_dcache_range(addr
, addr
+ size
);
670 #endif /* CONFIG_DMA_NONCOHERENT */
673 * While we're protected against bad userland addresses we don't care
674 * very much about what happens in that case. Usually a segmentation
675 * fault will dump the process later on anyway ...
677 static void local_r4k_flush_cache_sigtramp(void * arg
)
679 unsigned long ic_lsize
= cpu_icache_line_size();
680 unsigned long dc_lsize
= cpu_dcache_line_size();
681 unsigned long sc_lsize
= cpu_scache_line_size();
682 unsigned long addr
= (unsigned long) arg
;
684 R4600_HIT_CACHEOP_WAR_IMPL
;
686 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
687 if (!cpu_icache_snoops_remote_store
&& scache_size
)
688 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
690 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
691 if (MIPS4K_ICACHE_REFILL_WAR
) {
692 __asm__
__volatile__ (
707 : "i" (Hit_Invalidate_I
));
709 if (MIPS_CACHE_SYNC_WAR
)
710 __asm__
__volatile__ ("sync");
713 static void r4k_flush_cache_sigtramp(unsigned long addr
)
715 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
, 1);
718 static void r4k_flush_icache_all(void)
720 if (cpu_has_vtag_icache
)
724 static inline void rm7k_erratum31(void)
726 const unsigned long ic_lsize
= 32;
729 /* RM7000 erratum #31. The icache is screwed at startup. */
733 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
734 __asm__
__volatile__ (
738 "cache\t%1, 0(%0)\n\t"
739 "cache\t%1, 0x1000(%0)\n\t"
740 "cache\t%1, 0x2000(%0)\n\t"
741 "cache\t%1, 0x3000(%0)\n\t"
742 "cache\t%2, 0(%0)\n\t"
743 "cache\t%2, 0x1000(%0)\n\t"
744 "cache\t%2, 0x2000(%0)\n\t"
745 "cache\t%2, 0x3000(%0)\n\t"
746 "cache\t%1, 0(%0)\n\t"
747 "cache\t%1, 0x1000(%0)\n\t"
748 "cache\t%1, 0x2000(%0)\n\t"
749 "cache\t%1, 0x3000(%0)\n\t"
752 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
756 static char *way_string
[] __cpuinitdata
= { NULL
, "direct mapped", "2-way",
757 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
760 static void __cpuinit
probe_pcache(void)
762 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
763 unsigned int config
= read_c0_config();
764 unsigned int prid
= read_c0_prid();
765 unsigned long config1
;
768 switch (c
->cputype
) {
769 case CPU_R4600
: /* QED style two way caches? */
773 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
774 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
776 c
->icache
.waybit
= __ffs(icache_size
/2);
778 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
779 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
781 c
->dcache
.waybit
= __ffs(dcache_size
/2);
783 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
788 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
789 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
793 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
794 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
796 c
->dcache
.waybit
= 0;
798 c
->options
|= MIPS_CPU_CACHE_CDEX_P
| MIPS_CPU_PREFETCH
;
802 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
803 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
807 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
808 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
810 c
->dcache
.waybit
= 0;
812 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
813 c
->options
|= MIPS_CPU_PREFETCH
;
823 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
824 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
826 c
->icache
.waybit
= 0; /* doesn't matter */
828 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
829 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
831 c
->dcache
.waybit
= 0; /* does not matter */
833 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
839 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
840 c
->icache
.linesz
= 64;
842 c
->icache
.waybit
= 0;
844 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
845 c
->dcache
.linesz
= 32;
847 c
->dcache
.waybit
= 0;
849 c
->options
|= MIPS_CPU_PREFETCH
;
853 write_c0_config(config
& ~VR41_CONF_P4K
);
855 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
856 c
->processor_id
== 0x0c82U
) {
857 config
|= 0x00400000U
;
858 if (c
->processor_id
== 0x0c80U
)
859 config
|= VR41_CONF_BP
;
860 write_c0_config(config
);
862 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
864 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
865 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
867 c
->icache
.waybit
= __ffs(icache_size
/2);
869 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
870 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
872 c
->dcache
.waybit
= __ffs(dcache_size
/2);
881 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
882 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
884 c
->icache
.waybit
= 0; /* doesn't matter */
886 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
887 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
889 c
->dcache
.waybit
= 0; /* does not matter */
891 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
898 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
899 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
901 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
903 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
904 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
906 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
908 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
909 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
911 c
->options
|= MIPS_CPU_PREFETCH
;
915 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
916 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
921 c
->icache
.waybit
= 0;
923 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
924 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
929 c
->dcache
.waybit
= 0;
933 if (!(config
& MIPS_CONF_M
))
934 panic("Don't know how to probe P-caches on this cpu.");
937 * So we seem to be a MIPS32 or MIPS64 CPU
938 * So let's probe the I-cache ...
940 config1
= read_c0_config1();
942 if ((lsize
= ((config1
>> 19) & 7)))
943 c
->icache
.linesz
= 2 << lsize
;
945 c
->icache
.linesz
= lsize
;
946 c
->icache
.sets
= 32 << (((config1
>> 22) + 1) & 7);
947 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
949 icache_size
= c
->icache
.sets
*
952 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
954 if (config
& 0x8) /* VI bit */
955 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
958 * Now probe the MIPS32 / MIPS64 data cache.
962 if ((lsize
= ((config1
>> 10) & 7)))
963 c
->dcache
.linesz
= 2 << lsize
;
965 c
->dcache
.linesz
= lsize
;
966 c
->dcache
.sets
= 32 << (((config1
>> 13) + 1) & 7);
967 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
969 dcache_size
= c
->dcache
.sets
*
972 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
974 c
->options
|= MIPS_CPU_PREFETCH
;
979 * Processor configuration sanity check for the R4000SC erratum
980 * #5. With page sizes larger than 32kB there is no possibility
981 * to get a VCE exception anymore so we don't care about this
982 * misconfiguration. The case is rather theoretical anyway;
983 * presumably no vendor is shipping his hardware in the "bad"
986 if ((prid
& 0xff00) == PRID_IMP_R4000
&& (prid
& 0xff) < 0x40 &&
987 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
989 panic("Improper R4000SC processor configuration detected");
991 /* compute a couple of other cache variables */
992 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
993 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
995 c
->icache
.sets
= c
->icache
.linesz
?
996 icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
) : 0;
997 c
->dcache
.sets
= c
->dcache
.linesz
?
998 dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
) : 0;
1001 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1002 * 2-way virtually indexed so normally would suffer from aliases. So
1003 * normally they'd suffer from aliases but magic in the hardware deals
1004 * with that for us so we don't need to take care ourselves.
1006 switch (c
->cputype
) {
1011 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1021 * Early versions of the 74k do not update
1022 * the cache tags on a vtag miss/ptag hit
1023 * which can occur in the case of KSEG0/KUSEG aliases
1024 * In this case it is better to treat the cache as always
1027 if ((c
->processor_id
& 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
1028 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
1029 if ((c
->processor_id
& 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
1030 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
1034 if ((c
->processor_id
& 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
1035 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
1036 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
1046 if (read_c0_config7() & MIPS_CONF7_AR
) {
1047 /* effectively physically indexed dcache,
1048 thus no virtual aliases. */
1049 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1054 if (c
->dcache
.waysize
> PAGE_SIZE
)
1055 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
1058 switch (c
->cputype
) {
1061 * Some older 20Kc chips doesn't have the 'VI' bit in
1062 * the config register.
1064 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
1068 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
1072 #ifdef CONFIG_CPU_LOONGSON2
1074 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1075 * one op will act on all 4 ways
1080 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1081 icache_size
>> 10, way_string
[c
->icache
.ways
],
1082 c
->icache
.flags
& MIPS_CACHE_VTAG
? "VIVT" : "VIPT",
1085 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1086 dcache_size
>> 10, way_string
[c
->dcache
.ways
],
1087 (c
->dcache
.flags
& MIPS_CACHE_PINDEX
) ? "PIPT" : "VIPT",
1088 (c
->dcache
.flags
& MIPS_CACHE_ALIASES
) ?
1089 "cache aliases" : "no aliases",
1094 * If you even _breathe_ on this function, look at the gcc output and make sure
1095 * it does not pop things on and off the stack for the cache sizing loop that
1096 * executes in KSEG1 space or else you will crash and burn badly. You have
1099 static int __cpuinit
probe_scache(void)
1101 unsigned long flags
, addr
, begin
, end
, pow2
;
1102 unsigned int config
= read_c0_config();
1103 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1105 if (config
& CONF_SC
)
1108 begin
= (unsigned long) &_stext
;
1109 begin
&= ~((4 * 1024 * 1024) - 1);
1110 end
= begin
+ (4 * 1024 * 1024);
1113 * This is such a bitch, you'd think they would make it easy to do
1114 * this. Away you daemons of stupidity!
1116 local_irq_save(flags
);
1118 /* Fill each size-multiple cache line with a valid tag. */
1120 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1121 unsigned long *p
= (unsigned long *) addr
;
1122 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1126 /* Load first line with zero (therefore invalid) tag. */
1129 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1130 cache_op(Index_Store_Tag_I
, begin
);
1131 cache_op(Index_Store_Tag_D
, begin
);
1132 cache_op(Index_Store_Tag_SD
, begin
);
1134 /* Now search for the wrap around point. */
1135 pow2
= (128 * 1024);
1136 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1137 cache_op(Index_Load_Tag_SD
, addr
);
1138 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1139 if (!read_c0_taglo())
1143 local_irq_restore(flags
);
1147 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1149 c
->dcache
.waybit
= 0; /* does not matter */
1154 #if defined(CONFIG_CPU_LOONGSON2)
1155 static void __init
loongson2_sc_init(void)
1157 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1159 scache_size
= 512*1024;
1160 c
->scache
.linesz
= 32;
1162 c
->scache
.waybit
= 0;
1163 c
->scache
.waysize
= scache_size
/ (c
->scache
.ways
);
1164 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1165 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1166 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1168 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1172 extern int r5k_sc_init(void);
1173 extern int rm7k_sc_init(void);
1174 extern int mips_sc_init(void);
1176 static void __cpuinit
setup_scache(void)
1178 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1179 unsigned int config
= read_c0_config();
1183 * Do the probing thing on R4000SC and R4400SC processors. Other
1184 * processors don't have a S-cache that would be relevant to the
1185 * Linux memory management.
1187 switch (c
->cputype
) {
1192 sc_present
= run_uncached(probe_scache
);
1194 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1200 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1201 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1203 c
->scache
.waybit
= 0;
1209 #ifdef CONFIG_R5000_CPU_SCACHE
1216 #ifdef CONFIG_RM7000_CPU_SCACHE
1221 #if defined(CONFIG_CPU_LOONGSON2)
1223 loongson2_sc_init();
1228 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1229 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1230 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1231 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1232 #ifdef CONFIG_MIPS_CPU_SCACHE
1233 if (mips_sc_init ()) {
1234 scache_size
= c
->scache
.ways
* c
->scache
.sets
* c
->scache
.linesz
;
1235 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1237 way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1240 if (!(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1241 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1251 /* compute a couple of other cache variables */
1252 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1254 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1256 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1257 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1259 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1262 void au1x00_fixup_config_od(void)
1265 * c0_config.od (bit 19) was write only (and read as 0)
1266 * on the early revisions of Alchemy SOCs. It disables the bus
1267 * transaction overlapping and needs to be set to fix various errata.
1269 switch (read_c0_prid()) {
1270 case 0x00030100: /* Au1000 DA */
1271 case 0x00030201: /* Au1000 HA */
1272 case 0x00030202: /* Au1000 HB */
1273 case 0x01030200: /* Au1500 AB */
1275 * Au1100 errata actually keeps silence about this bit, so we set it
1276 * just in case for those revisions that require it to be set according
1277 * to the (now gone) cpu table.
1279 case 0x02030200: /* Au1100 AB */
1280 case 0x02030201: /* Au1100 BA */
1281 case 0x02030202: /* Au1100 BC */
1282 set_c0_config(1 << 19);
1287 /* CP0 hazard avoidance. */
1288 #define NXP_BARRIER() \
1289 __asm__ __volatile__( \
1290 ".set noreorder\n\t" \
1291 "nop; nop; nop; nop; nop; nop;\n\t" \
1294 static void nxp_pr4450_fixup_config(void)
1296 unsigned long config0
;
1298 config0
= read_c0_config();
1300 /* clear all three cache coherency fields */
1301 config0
&= ~(0x7 | (7 << 25) | (7 << 28));
1302 config0
|= (((_page_cachable_default
>> _CACHE_SHIFT
) << 0) |
1303 ((_page_cachable_default
>> _CACHE_SHIFT
) << 25) |
1304 ((_page_cachable_default
>> _CACHE_SHIFT
) << 28));
1305 write_c0_config(config0
);
1309 static int __cpuinitdata cca
= -1;
1311 static int __init
cca_setup(char *str
)
1313 get_option(&str
, &cca
);
1318 __setup("cca=", cca_setup
);
1320 static void __cpuinit
coherency_setup(void)
1322 if (cca
< 0 || cca
> 7)
1323 cca
= read_c0_config() & CONF_CM_CMASK
;
1324 _page_cachable_default
= cca
<< _CACHE_SHIFT
;
1326 pr_debug("Using cache attribute %d\n", cca
);
1327 change_c0_config(CONF_CM_CMASK
, cca
);
1330 * c0_status.cu=0 specifies that updates by the sc instruction use
1331 * the coherency mode specified by the TLB; 1 means cachable
1332 * coherent update on write will be used. Not all processors have
1333 * this bit and; some wire it to zero, others like Toshiba had the
1334 * silly idea of putting something else there ...
1336 switch (current_cpu_type()) {
1343 clear_c0_config(CONF_CU
);
1346 * We need to catch the early Alchemy SOCs with
1347 * the write-only co_config.od bit and set it back to one on:
1348 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1351 au1x00_fixup_config_od();
1354 case PRID_IMP_PR4450
:
1355 nxp_pr4450_fixup_config();
1360 void __cpuinit
r4k_cache_init(void)
1362 extern void build_clear_page(void);
1363 extern void build_copy_page(void);
1364 extern char __weak except_vec2_generic
;
1365 extern char __weak except_vec2_sb1
;
1366 extern int coherentio
;
1367 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1369 switch (c
->cputype
) {
1372 set_uncached_handler(0x100, &except_vec2_sb1
, 0x80);
1376 set_uncached_handler(0x100, &except_vec2_generic
, 0x80);
1383 r4k_blast_dcache_page_setup();
1384 r4k_blast_dcache_page_indexed_setup();
1385 r4k_blast_dcache_setup();
1386 r4k_blast_icache_page_setup();
1387 r4k_blast_icache_page_indexed_setup();
1388 r4k_blast_icache_setup();
1389 r4k_blast_scache_page_setup();
1390 r4k_blast_scache_page_indexed_setup();
1391 r4k_blast_scache_setup();
1394 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1395 * This code supports virtually indexed processors and will be
1396 * unnecessarily inefficient on physically indexed processors.
1398 if (c
->dcache
.linesz
)
1399 shm_align_mask
= max_t( unsigned long,
1400 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1403 shm_align_mask
= PAGE_SIZE
-1;
1405 __flush_cache_vmap
= r4k__flush_cache_vmap
;
1406 __flush_cache_vunmap
= r4k__flush_cache_vunmap
;
1408 flush_cache_all
= cache_noop
;
1409 __flush_cache_all
= r4k___flush_cache_all
;
1410 flush_cache_mm
= r4k_flush_cache_mm
;
1411 flush_cache_page
= r4k_flush_cache_page
;
1412 flush_cache_range
= r4k_flush_cache_range
;
1414 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1415 flush_icache_all
= r4k_flush_icache_all
;
1416 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1417 flush_data_cache_page
= r4k_flush_data_cache_page
;
1418 flush_icache_range
= r4k_flush_icache_range
;
1419 local_flush_icache_range
= local_r4k_flush_icache_range
;
1421 #if defined(CONFIG_DMA_NONCOHERENT)
1423 _dma_cache_wback_inv
= (void *)cache_noop
;
1424 _dma_cache_wback
= (void *)cache_noop
;
1425 _dma_cache_inv
= (void *)cache_noop
;
1427 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1428 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1429 _dma_cache_inv
= r4k_dma_cache_inv
;
1436 /* We want to run CMP kernels on core(s) with and without coherent caches */
1437 /* Therefore can't use CONFIG_MIPS_CMP to decide to flush cache */
1438 local_r4k___flush_cache_all(NULL
);