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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / mips / include / asm / sn / sn0 / hubio.h
blob5ac938e1a64e8c220589f5346eaf326e1214f071
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11 #ifndef _ASM_SGI_SN_SN0_HUBIO_H
12 #define _ASM_SGI_SN_SN0_HUBIO_H
13
14 /*
15 * Hub I/O interface registers
16 *
17 * All registers in this file are subject to change until Hub chip tapeout.
18 * In general, the longer software name should be used when available.
19 */
20
21 /*
22 * Slightly friendlier names for some common registers.
23 * The hardware definitions follow.
24 */
25 #define IIO_WIDGET IIO_WID /* Widget identification */
26 #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
27 #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
28 #define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
29 #define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
30 #define IIO_PROTECT IIO_ILAPR /* IO interface protection */
31 #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
32 #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
33 #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
34 #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
35 #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
36 #define IIO_LLP_LOG IIO_ILLR /* LLP log */
37 #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
38 #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
39 #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
40 #define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
41
42 #define IIO_LLP_CSR_IS_UP 0x00002000
43 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
44 #define IIO_LLP_CSR_LLP_STAT_SHFT 12
45
46 /* key to IIO_PROTECT_OVRRD */
47 #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
48
49 /* BTE register names */
50 #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
51 #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
52 #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
53 #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
54 #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
55 #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
56 #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
57 #define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
58
59 /* BTE register offsets from base */
60 #define BTEOFF_STAT 0
61 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
62 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
63 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
64 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
65 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
66
67
68 /*
69 * The following definitions use the names defined in the IO interface
70 * document for ease of reference. When possible, software should
71 * generally use the longer but clearer names defined above.
72 */
73
74 #define IIO_BASE 0x400000
75 #define IIO_BASE_BTE0 0x410000
76 #define IIO_BASE_BTE1 0x420000
77 #define IIO_BASE_PERF 0x430000
78 #define IIO_PERF_CNT 0x430008
79
80 #define IO_PERF_SETS 32
81
82 #define IIO_WID 0x400000 /* Widget identification */
83 #define IIO_WSTAT 0x400008 /* Widget status */
84 #define IIO_WCR 0x400020 /* Widget control */
85
86 #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
87 #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
88 #define IIO_WSTAT_TXRETRY_MASK (0x7F)
89 #define IIO_WSTAT_TXRETRY_SHFT (16)
90 #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
91 IIO_WSTAT_TXRETRY_MASK)
92
93 #define IIO_ILAPR 0x400100 /* Local Access Protection */
94 #define IIO_ILAPO 0x400108 /* Protection override */
95 #define IIO_IOWA 0x400110 /* outbound widget access */
96 #define IIO_IIWA 0x400118 /* inbound widget access */
97 #define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
98 #define IIO_ILCSR 0x400128 /* LLP control and status */
99 #define IIO_ILLR 0x400130 /* LLP Log */
100 #define IIO_IIDSR 0x400138 /* Interrupt destination */
101
102 #define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
103
104 /* IO Interrupt Destination Register */
105 #define IIO_IIDSR_SENT_SHIFT 28
106 #define IIO_IIDSR_SENT_MASK 0x10000000
107 #define IIO_IIDSR_ENB_SHIFT 24
108 #define IIO_IIDSR_ENB_MASK 0x01000000
109 #define IIO_IIDSR_NODE_SHIFT 8
110 #define IIO_IIDSR_NODE_MASK 0x0000ff00
111 #define IIO_IIDSR_LVL_SHIFT 0
112 #define IIO_IIDSR_LVL_MASK 0x0000003f
113
114
115 /* GFX Flow Control Node/Widget Register */
116 #define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
117 #define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
118 #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
119 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
120 #define IIO_IGFX_W_NUM_SHIFT 0
121 #define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
122 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
123 #define IIO_IGFX_N_NUM_SHIFT 4
124 #define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
125 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
126 #define IIO_IGFX_P_NUM_SHIFT 16
127 #define IIO_IGFX_VLD_BITS 1 /* size of valid field */
128 #define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
129 #define IIO_IGFX_VLD_SHIFT 20
130 #define IIO_IGFX_INIT(widget, node, cpu, valid) (\
131 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
132 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
133 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
134 (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
135
136 /* Scratch registers (not all bits available) */
137 #define IIO_SCRATCH_REG0 0x400150
138 #define IIO_SCRATCH_REG1 0x400158
139 #define IIO_SCRATCH_MASK 0x0000000f00f11fff
140
141 #define IIO_SCRATCH_BIT0_0 0x0000000800000000
142 #define IIO_SCRATCH_BIT0_1 0x0000000400000000
143 #define IIO_SCRATCH_BIT0_2 0x0000000200000000
144 #define IIO_SCRATCH_BIT0_3 0x0000000100000000
145 #define IIO_SCRATCH_BIT0_4 0x0000000000800000
146 #define IIO_SCRATCH_BIT0_5 0x0000000000400000
147 #define IIO_SCRATCH_BIT0_6 0x0000000000200000
148 #define IIO_SCRATCH_BIT0_7 0x0000000000100000
149 #define IIO_SCRATCH_BIT0_8 0x0000000000010000
150 #define IIO_SCRATCH_BIT0_9 0x0000000000001000
151 #define IIO_SCRATCH_BIT0_R 0x0000000000000fff
152
153 /* IO Translation Table Entries */
154 #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
155 /* Hw manuals number them 1..7! */
156
157 #define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
158
159 /*
160 * Use the top big window as a surrogate for the first small window
161 */
162 #define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
163
164 #define ILCSR_WARM_RESET 0x100
165 /*
166 * The IO LLP control status register and widget control register
167 */
168 #ifndef __ASSEMBLY__
169
170 typedef union hubii_wid_u {
171 u64 wid_reg_value;
172 struct {
173 u64 wid_rsvd: 32, /* unused */
174 wid_rev_num: 4, /* revision number */
175 wid_part_num: 16, /* the widget type: hub=c101 */
176 wid_mfg_num: 11, /* Manufacturer id (IBM) */
177 wid_rsvd1: 1; /* Reserved */
178 } wid_fields_s;
179 } hubii_wid_t;
180
181
182 typedef union hubii_wcr_u {
183 u64 wcr_reg_value;
184 struct {
185 u64 wcr_rsvd: 41, /* unused */
186 wcr_e_thresh: 5, /* elasticity threshold */
187 wcr_dir_con: 1, /* widget direct connect */
188 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
189 wcr_xbar_crd: 3, /* LLP crossbar credit */
190 wcr_rsvd1: 8, /* Reserved */
191 wcr_tag_mode: 1, /* Tag mode */
192 wcr_widget_id: 4; /* LLP crossbar credit */
193 } wcr_fields_s;
194 } hubii_wcr_t;
195
196 #define iwcr_dir_con wcr_fields_s.wcr_dir_con
197
198 typedef union hubii_wstat_u {
199 u64 reg_value;
200 struct {
201 u64 rsvd1: 31,
202 crazy: 1, /* Crazy bit */
203 rsvd2: 8,
204 llp_tx_cnt: 8, /* LLP Xmit retry counter */
205 rsvd3: 6,
206 tx_max_rtry: 1, /* LLP Retry Timeout Signal */
207 rsvd4: 2,
208 xt_tail_to: 1, /* Xtalk Tail Timeout */
209 xt_crd_to: 1, /* Xtalk Credit Timeout */
210 pending: 4; /* Pending Requests */
211 } wstat_fields_s;
212 } hubii_wstat_t;
213
214
215 typedef union hubii_ilcsr_u {
216 u64 icsr_reg_value;
217 struct {
218 u64 icsr_rsvd: 22, /* unused */
219 icsr_max_burst: 10, /* max burst */
220 icsr_rsvd4: 6, /* reserved */
221 icsr_max_retry: 10, /* max retry */
222 icsr_rsvd3: 2, /* reserved */
223 icsr_lnk_stat: 2, /* link status */
224 icsr_bm8: 1, /* Bit mode 8 */
225 icsr_llp_en: 1, /* LLP enable bit */
226 icsr_rsvd2: 1, /* reserver */
227 icsr_wrm_reset: 1, /* Warm reset bit */
228 icsr_rsvd1: 2, /* Data ready offset */
229 icsr_null_to: 6; /* Null timeout */
230
231 } icsr_fields_s;
232 } hubii_ilcsr_t;
233
234
235 typedef union hubii_iowa_u {
236 u64 iowa_reg_value;
237 struct {
238 u64 iowa_rsvd: 48, /* unused */
239 iowa_wxoac: 8, /* xtalk widget access bits */
240 iowa_rsvd1: 7, /* xtalk widget access bits */
241 iowa_w0oac: 1; /* xtalk widget access bits */
242 } iowa_fields_s;
243 } hubii_iowa_t;
244
245 typedef union hubii_iiwa_u {
246 u64 iiwa_reg_value;
247 struct {
248 u64 iiwa_rsvd: 48, /* unused */
249 iiwa_wxiac: 8, /* hub wid access bits */
250 iiwa_rsvd1: 7, /* reserved */
251 iiwa_w0iac: 1; /* hub wid0 access */
252 } iiwa_fields_s;
253 } hubii_iiwa_t;
254
255 typedef union hubii_illr_u {
256 u64 illr_reg_value;
257 struct {
258 u64 illr_rsvd: 32, /* unused */
259 illr_cb_cnt: 16, /* checkbit error count */
260 illr_sn_cnt: 16; /* sequence number count */
261 } illr_fields_s;
262 } hubii_illr_t;
263
264 /* The structures below are defined to extract and modify the ii
265 performance registers */
266
267 /* io_perf_sel allows the caller to specify what tests will be
268 performed */
269 typedef union io_perf_sel {
270 u64 perf_sel_reg;
271 struct {
272 u64 perf_rsvd : 48,
273 perf_icct : 8,
274 perf_ippr1 : 4,
275 perf_ippr0 : 4;
276 } perf_sel_bits;
277 } io_perf_sel_t;
278
279 /* io_perf_cnt is to extract the count from the hub registers. Due to
280 hardware problems there is only one counter, not two. */
281
282 typedef union io_perf_cnt {
283 u64 perf_cnt;
284 struct {
285 u64 perf_rsvd1 : 32,
286 perf_rsvd2 : 12,
287 perf_cnt : 20;
288 } perf_cnt_bits;
289 } io_perf_cnt_t;
290
291 #endif /* !__ASSEMBLY__ */
292
293
294 #define LNK_STAT_WORKING 0x2
295
296 #define IIO_LLP_CB_MAX 0xffff
297 #define IIO_LLP_SN_MAX 0xffff
298
299 /* IO PRB Entries */
300 #define IIO_NUM_IPRBS (9)
301 #define IIO_IOPRB_0 0x400198 /* PRB entry 0 */
302 #define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */
303 #define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */
304 #define IIO_IOPRB_A 0x4001b0 /* PRB entry a */
305 #define IIO_IOPRB_B 0x4001b8 /* PRB entry b */
306 #define IIO_IOPRB_C 0x4001c0 /* PRB entry c */
307 #define IIO_IOPRB_D 0x4001c8 /* PRB entry d */
308 #define IIO_IOPRB_E 0x4001d0 /* PRB entry e */
309 #define IIO_IOPRB_F 0x4001d8 /* PRB entry f */
310
311
312 #define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */
313 #define IIO_IXTCC IIO_IXCC
314 #define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */
315 #define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */
316 #define IIO_IECLR 0x4001f8 /* IO error clear */
317 #define IIO_IBCN 0x400200 /* IO BTE CRB count */
318
319 /*
320 * IIO_IMEM Register fields.
321 */
322 #define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
323 #define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
324 #define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
325
326 /* PIO Read address Table Entries */
327 #define IIO_IPCA 0x400300 /* PRB Counter adjust */
328 #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
329 #define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */
330 #define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
331 #define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
332 #define IIO_IPDR 0x400388 /* PIO table entry deallocation */
333 #define IIO_ICDR 0x400390 /* CRB Entry Deallocation */
334 #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
335 #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
336 #define IIO_IMMR IIO_IIAP
337 #define IIO_ICMR 0x4003a8 /* CRB Management Register */
338 #define IIO_ICCR 0x4003b0 /* CRB Control Register */
339 #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
340 #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
341
342
343 /*
344 * ICMR register fields
345 */
346 #define IIO_ICMR_PC_VLD_SHFT 36
347 #define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
348
349 #define IIO_ICMR_CRB_VLD_SHFT 20
350 #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
351
352 #define IIO_ICMR_FC_CNT_SHFT 16
353 #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
354
355 #define IIO_ICMR_C_CNT_SHFT 4
356 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
357
358 #define IIO_ICMR_P_CNT_SHFT 0
359 #define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
360
361 #define IIO_ICMR_PRECISE (1UL << 52)
362 #define IIO_ICMR_CLR_RPPD (1UL << 13)
363 #define IIO_ICMR_CLR_RQPD (1UL << 12)
364
365 /*
366 * IIO PIO Deallocation register field masks : (IIO_IPDR)
367 */
368 #define IIO_IPDR_PND (1 << 4)
369
370 /*
371 * IIO CRB deallocation register field masks: (IIO_ICDR)
372 */
373 #define IIO_ICDR_PND (1 << 4)
374
375 /*
376 * IIO CRB control register Fields: IIO_ICCR
377 */
378 #define IIO_ICCR_PENDING (0x10000)
379 #define IIO_ICCR_CMD_MASK (0xFF)
380 #define IIO_ICCR_CMD_SHFT (7)
381 #define IIO_ICCR_CMD_NOP (0x0) /* No Op */
382 #define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
383 #define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
384 #define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
385 * via a WB
386 */
387 #define IIO_ICCR_CMD_FLUSH (0x800)
388
389 /*
390 * CRB manipulation macros
391 * The CRB macros are slightly complicated, since there are up to
392 * four registers associated with each CRB entry.
393 */
394 #define IIO_NUM_CRBS 15 /* Number of CRBs */
395 #define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */
396 #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
397 #define IIO_ICRB_OFFSET 8
398 #define IIO_ICRB_0 0x400400
399
400 #define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
401 #define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
402 #define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
403 #define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
404
405
406 /*
407 *
408 * CRB Register description.
409 *
410 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
411 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
412 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
413 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
414 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
415 *
416 * Many of the fields in CRB are status bits used by hardware
417 * for implementation of the protocol. It's very dangerous to
418 * mess around with the CRB registers.
419 *
420 * It's OK to read the CRB registers and try to make sense out of the
421 * fields in CRB.
422 *
423 * Updating CRB requires all activities in Hub IIO to be quiesced.
424 * otherwise, a write to CRB could corrupt other CRB entries.
425 * CRBs are here only as a back door peek to hub IIO's status.
426 * Quiescing implies no dmas no PIOs
427 * either directly from the cpu or from sn0net.
428 * this is not something that can be done easily. So, AVOID updating
429 * CRBs.
430 */
431
432 /*
433 * Fields in CRB Register A
434 */
435 #ifndef __ASSEMBLY__
436 typedef union icrba_u {
437 u64 reg_value;
438 struct {
439 u64 resvd: 6,
440 stall_bte0: 1, /* Stall BTE 0 */
441 stall_bte1: 1, /* Stall BTE 1 */
442 error: 1, /* CRB has an error */
443 ecode: 3, /* Error Code */
444 lnetuce: 1, /* SN0net Uncorrectable error */
445 mark: 1, /* CRB Has been marked */
446 xerr: 1, /* Error bit set in xtalk header */
447 sidn: 4, /* SIDN field from xtalk */
448 tnum: 5, /* TNUM field in xtalk */
449 addr: 38, /* Address of request */
450 valid: 1, /* Valid status */
451 iow: 1; /* IO Write operation */
452 } icrba_fields_s;
453 } icrba_t;
454
455 /* This is an alternate typedef for the HUB1 CRB A in order to allow
456 runtime selection of the format based on the REV_ID field of the
457 NI_STATUS_REV_ID register. */
458 typedef union h1_icrba_u {
459 u64 reg_value;
460
461 struct {
462 u64 resvd: 6,
463 unused: 1, /* Unused but RW!! */
464 error: 1, /* CRB has an error */
465 ecode: 4, /* Error Code */
466 lnetuce: 1, /* SN0net Uncorrectable error */
467 mark: 1, /* CRB Has been marked */
468 xerr: 1, /* Error bit set in xtalk header */
469 sidn: 4, /* SIDN field from xtalk */
470 tnum: 5, /* TNUM field in xtalk */
471 addr: 38, /* Address of request */
472 valid: 1, /* Valid status */
473 iow: 1; /* IO Write operation */
474 } h1_icrba_fields_s;
475 } h1_icrba_t;
476
477 #define ICRBN_A_CERR_SHFT 54
478 #define ICRBN_A_ERR_MASK 0x3ff
479
480 #endif /* !__ASSEMBLY__ */
481
482 #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
483
484 /*
485 * values for "ecode" field
486 */
487 #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
488 #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
489 #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
490 * e.g. WINV to a Read only line.
491 */
492 #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
493 #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
494 #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
495 #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
496 #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
497
498
499
500 /*
501 * Fields in CRB Register B
502 */
503 #ifndef __ASSEMBLY__
504 typedef union icrbb_u {
505 u64 reg_value;
506 struct {
507 u64 rsvd1: 5,
508 btenum: 1, /* BTE to which entry belongs to */
509 cohtrans: 1, /* Coherent transaction */
510 xtsize: 2, /* Xtalk operation size
511 * 0: Double Word
512 * 1: 32 Bytes.
513 * 2: 128 Bytes,
514 * 3: Reserved.
515 */
516 srcnode: 9, /* Source Node ID */
517 srcinit: 2, /* Source Initiator:
518 * See below for field values.
519 */
520 useold: 1, /* Use OLD command for processing */
521 imsgtype: 2, /* Incoming message type
522 * see below for field values
523 */
524 imsg: 8, /* Incoming message */
525 initator: 3, /* Initiator of original request
526 * See below for field values.
527 */
528 reqtype: 5, /* Identifies type of request
529 * See below for field values.
530 */
531 rsvd2: 7,
532 ackcnt: 11, /* Invalidate ack count */
533 resp: 1, /* data response given to processor */
534 ack: 1, /* indicates data ack received */
535 hold: 1, /* entry is gathering inval acks */
536 wb_pend:1, /* waiting for writeback to complete */
537 intvn: 1, /* Intervention */
538 stall_ib: 1, /* Stall Ibuf (from crosstalk) */
539 stall_intr: 1; /* Stall internal interrupts */
540 } icrbb_field_s;
541 } icrbb_t;
542
543 /* This is an alternate typedef for the HUB1 CRB B in order to allow
544 runtime selection of the format based on the REV_ID field of the
545 NI_STATUS_REV_ID register. */
546 typedef union h1_icrbb_u {
547 u64 reg_value;
548 struct {
549 u64 rsvd1: 5,
550 btenum: 1, /* BTE to which entry belongs to */
551 cohtrans: 1, /* Coherent transaction */
552 xtsize: 2, /* Xtalk operation size
553 * 0: Double Word
554 * 1: 32 Bytes.
555 * 2: 128 Bytes,
556 * 3: Reserved.
557 */
558 srcnode: 9, /* Source Node ID */
559 srcinit: 2, /* Source Initiator:
560 * See below for field values.
561 */
562 useold: 1, /* Use OLD command for processing */
563 imsgtype: 2, /* Incoming message type
564 * see below for field values
565 */
566 imsg: 8, /* Incoming message */
567 initator: 3, /* Initiator of original request
568 * See below for field values.
569 */
570 rsvd2: 1,
571 pcache: 1, /* entry belongs to partial cache */
572 reqtype: 5, /* Identifies type of request
573 * See below for field values.
574 */
575 stl_ib: 1, /* stall Ibus coming from xtalk */
576 stl_intr: 1, /* Stall internal interrupts */
577 stl_bte0: 1, /* Stall BTE 0 */
578 stl_bte1: 1, /* Stall BTE 1 */
579 intrvn: 1, /* Req was target of intervention */
580 ackcnt: 11, /* Invalidate ack count */
581 resp: 1, /* data response given to processor */
582 ack: 1, /* indicates data ack received */
583 hold: 1, /* entry is gathering inval acks */
584 wb_pend:1, /* waiting for writeback to complete */
585 sleep: 1, /* xtalk req sleeping till IO-sync */
586 pnd_reply: 1, /* replies not issed due to IOQ full */
587 pnd_req: 1; /* reqs not issued due to IOQ full */
588 } h1_icrbb_field_s;
589 } h1_icrbb_t;
590
591
592 #define b_imsgtype icrbb_field_s.imsgtype
593 #define b_btenum icrbb_field_s.btenum
594 #define b_cohtrans icrbb_field_s.cohtrans
595 #define b_xtsize icrbb_field_s.xtsize
596 #define b_srcnode icrbb_field_s.srcnode
597 #define b_srcinit icrbb_field_s.srcinit
598 #define b_imsgtype icrbb_field_s.imsgtype
599 #define b_imsg icrbb_field_s.imsg
600 #define b_initiator icrbb_field_s.initiator
601
602 #endif /* !__ASSEMBLY__ */
603
604 /*
605 * values for field xtsize
606 */
607 #define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */
608 #define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */
609 #define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */
610
611 /*
612 * values for field srcinit
613 */
614 #define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
615 #define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
616 #define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */
617 #define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
618
619 /*
620 * Values for field imsgtype
621 */
622 #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
623 #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
624 #define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
625 #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
626
627 /*
628 * values for field initiator.
629 */
630 #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
631 #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
632 #define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */
633 #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
634 #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
635
636 /*
637 * Values for field reqtype.
638 */
639 #define IIO_ICRB_REQ_DWRD 0 /* Request type double word */
640 #define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */
641 #define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */
642 #define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */
643 #define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */
644 #define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */
645 #define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */
646 #define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */
647 #define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */
648 #define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */
649 #define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */
650 #define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */
651 #define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */
652 #define IIO_ICRB_REQ_WB 16 /* Request is Write back */
653 #define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */
654
655 /*
656 * Fields in CRB Register C
657 */
658
659 #ifndef __ASSEMBLY__
660
661 typedef union icrbc_s {
662 u64 reg_value;
663 struct {
664 u64 rsvd: 6,
665 sleep: 1,
666 pricnt: 4, /* Priority count sent with Read req */
667 pripsc: 4, /* Priority Pre scalar */
668 bteop: 1, /* BTE Operation */
669 push_be: 34, /* Push address Byte enable
670 * Holds push addr, if CRB is for BTE
671 * If CRB belongs to Partial cache,
672 * this contains byte enables bits
673 * ([47:46] = 0)
674 */
675 suppl: 11, /* Supplemental field */
676 barrop: 1, /* Barrier Op bit set in xtalk req */
677 doresp: 1, /* Xtalk req needs a response */
678 gbr: 1; /* GBR bit set in xtalk packet */
679 } icrbc_field_s;
680 } icrbc_t;
681
682 #define c_pricnt icrbc_field_s.pricnt
683 #define c_pripsc icrbc_field_s.pripsc
684 #define c_bteop icrbc_field_s.bteop
685 #define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */
686 #define c_benable icrbc_field_s.push_be /* push_be field has 2 names */
687 #define c_suppl icrbc_field_s.suppl
688 #define c_barrop icrbc_field_s.barrop
689 #define c_doresp icrbc_field_s.doresp
690 #define c_gbr icrbc_field_s.gbr
691 #endif /* !__ASSEMBLY__ */
692
693 /*
694 * Fields in CRB Register D
695 */
696
697 #ifndef __ASSEMBLY__
698 typedef union icrbd_s {
699 u64 reg_value;
700 struct {
701 u64 rsvd: 38,
702 toutvld: 1, /* Timeout in progress for this CRB */
703 ctxtvld: 1, /* Context field below is valid */
704 rsvd2: 1,
705 context: 15, /* Bit vector:
706 * Has a bit set for each CRB entry
707 * which needs to be deallocated
708 * before this CRB entry is processed.
709 * Set only for barrier operations.
710 */
711 timeout: 8; /* Timeout Upper 8 bits */
712 } icrbd_field_s;
713 } icrbd_t;
714
715 #define icrbd_toutvld icrbd_field_s.toutvld
716 #define icrbd_ctxtvld icrbd_field_s.ctxtvld
717 #define icrbd_context icrbd_field_s.context
718
719
720 typedef union hubii_ifdr_u {
721 u64 hi_ifdr_value;
722 struct {
723 u64 ifdr_rsvd: 49,
724 ifdr_maxrp: 7,
725 ifdr_rsvd1: 1,
726 ifdr_maxrq: 7;
727 } hi_ifdr_fields;
728 } hubii_ifdr_t;
729
730 #endif /* !__ASSEMBLY__ */
731
732 /*
733 * Hardware designed names for the BTE control registers.
734 */
735 #define IIO_IBLS_0 0x410000 /* BTE length/status 0 */
736 #define IIO_IBSA_0 0x410008 /* BTE source address 0 */
737 #define IIO_IBDA_0 0x410010 /* BTE destination address 0 */
738 #define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */
739 #define IIO_IBNA_0 0x410020 /* BTE notification address 0 */
740 #define IIO_IBNR_0 IIO_IBNA_0
741 #define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */
742
743 #define IIO_IBLS_1 0x420000 /* BTE length/status 1 */
744 #define IIO_IBSA_1 0x420008 /* BTE source address 1 */
745 #define IIO_IBDA_1 0x420010 /* BTE destination address 1 */
746 #define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */
747 #define IIO_IBNA_1 0x420020 /* BTE notification address 1 */
748 #define IIO_IBNR_1 IIO_IBNA_1
749 #define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */
750
751 /*
752 * More miscellaneous registers
753 */
754 #define IIO_IPCR 0x430000 /* Performance Control */
755 #define IIO_IPPR 0x430008 /* Performance Profiling */
756
757 /*
758 * IO Error Clear register bit field definitions
759 */
760 #define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */
761 #define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */
762 #define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
763 #define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
764 #define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
765 #define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
766 #define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
767 #define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
768 #define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
769 #define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
770 #define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
771 #define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
772
773 /*
774 * IO PIO Read Table Entry format
775 */
776
777 #ifndef __ASSEMBLY__
778
779 typedef union iprte_a {
780 u64 entry;
781 struct {
782 u64 rsvd1 : 7, /* Reserved field */
783 valid : 1, /* Maps to a timeout entry */
784 rsvd2 : 1,
785 srcnode : 9, /* Node which did this PIO */
786 initiator : 2, /* If T5A or T5B or IO */
787 rsvd3 : 3,
788 addr : 38, /* Physical address of PIO */
789 rsvd4 : 3;
790 } iprte_fields;
791 } iprte_a_t;
792
793 #define iprte_valid iprte_fields.valid
794 #define iprte_timeout iprte_fields.timeout
795 #define iprte_srcnode iprte_fields.srcnode
796 #define iprte_init iprte_fields.initiator
797 #define iprte_addr iprte_fields.addr
798
799 #endif /* !__ASSEMBLY__ */
800
801 #define IPRTE_ADDRSHFT 3
802
803 /*
804 * Hub IIO PRB Register format.
805 */
806
807 #ifndef __ASSEMBLY__
808 /*
809 * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
810 * "Status" fields, and should only be used in case of clean up after errors.
811 */
812
813 typedef union iprb_u {
814 u64 reg_value;
815 struct {
816 u64 rsvd1: 15,
817 error: 1, /* Widget rcvd wr resp pkt w/ error */
818 ovflow: 5, /* Overflow count. perf measurement */
819 fire_and_forget: 1, /* Launch Write without response */
820 mode: 2, /* Widget operation Mode */
821 rsvd2: 2,
822 bnakctr: 14,
823 rsvd3: 2,
824 anakctr: 14,
825 xtalkctr: 8;
826 } iprb_fields_s;
827 } iprb_t;
828
829 #define iprb_regval reg_value
830
831 #define iprb_error iprb_fields_s.error
832 #define iprb_ovflow iprb_fields_s.ovflow
833 #define iprb_ff iprb_fields_s.fire_and_forget
834 #define iprb_mode iprb_fields_s.mode
835 #define iprb_bnakctr iprb_fields_s.bnakctr
836 #define iprb_anakctr iprb_fields_s.anakctr
837 #define iprb_xtalkctr iprb_fields_s.xtalkctr
838
839 #endif /* !__ASSEMBLY__ */
840
841 /*
842 * values for mode field in iprb_t.
843 * For details of the meanings of NAK and Accept, refer the PIO flow
844 * document
845 */
846 #define IPRB_MODE_NORMAL (0)
847 #define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
848 #define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
849 #define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
850
851 /*
852 * IO CRB entry C_A to E_A : Partial (cache) CRBS
853 */
854 #ifndef __ASSEMBLY__
855 typedef union icrbp_a {
856 u64 ip_reg; /* the entire register value */
857 struct {
858 u64 error: 1, /* 63, error occurred */
859 ln_uce: 1, /* 62: uncorrectable memory */
860 ln_ae: 1, /* 61: protection violation */
861 ln_werr:1, /* 60: write access error */
862 ln_aerr:1, /* 59: sn0net: Address error */
863 ln_perr:1, /* 58: sn0net: poison error */
864 timeout:1, /* 57: CRB timed out */
865 l_bdpkt:1, /* 56: truncated pkt on sn0net */
866 c_bdpkt:1, /* 55: truncated pkt on xtalk */
867 c_err: 1, /* 54: incoming xtalk req, err set*/
868 rsvd1: 12, /* 53-42: reserved */
869 valid: 1, /* 41: Valid status */
870 sidn: 4, /* 40-37: SIDN field of xtalk rqst */
871 tnum: 5, /* 36-32: TNUM of xtalk request */
872 bo: 1, /* 31: barrier op set in xtalk rqst*/
873 resprqd:1, /* 30: xtalk rqst requires response*/
874 gbr: 1, /* 29: gbr bit set in xtalk rqst */
875 size: 2, /* 28-27: size of xtalk request */
876 excl: 4, /* 26-23: exclusive bit(s) */
877 stall: 3, /* 22-20: stall (xtalk, bte 0/1) */
878 intvn: 1, /* 19: rqst target of intervention*/
879 resp: 1, /* 18: Data response given to t5 */
880 ack: 1, /* 17: Data ack received. */
881 hold: 1, /* 16: crb gathering invalidate acks*/
882 wb: 1, /* 15: writeback pending. */
883 ack_cnt:11, /* 14-04: counter of invalidate acks*/
884 tscaler:4; /* 03-00: Timeout prescaler */
885 } ip_fmt;
886 } icrbp_a_t;
887
888 #endif /* !__ASSEMBLY__ */
889
890 /*
891 * A couple of defines to go with the above structure.
892 */
893 #define ICRBP_A_CERR_SHFT 54
894 #define ICRBP_A_ERR_MASK 0x3ff
895
896 #ifndef __ASSEMBLY__
897 typedef union hubii_idsr {
898 u64 iin_reg;
899 struct {
900 u64 rsvd1 : 35,
901 isent : 1,
902 rsvd2 : 3,
903 ienable: 1,
904 rsvd : 7,
905 node : 9,
906 rsvd4 : 1,
907 level : 7;
908 } iin_fmt;
909 } hubii_idsr_t;
910 #endif /* !__ASSEMBLY__ */
911
912 /*
913 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
914 */
915 #define IBLS_BUSY (0x1 << 20)
916 #define IBLS_ERROR_SHFT 16
917 #define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
918 #define IBLS_LENGTH_MASK 0xffff
919
920 /*
921 * IO BTE Control/Terminate register (IBCT) register bit field definitions
922 */
923 #define IBCT_POISON (0x1 << 8)
924 #define IBCT_NOTIFY (0x1 << 4)
925 #define IBCT_ZFIL_MODE (0x1 << 0)
926
927 /*
928 * IO BTE Interrupt Address Register (IBIA) register bit field definitions
929 */
930 #define IBIA_LEVEL_SHFT 16
931 #define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT)
932 #define IBIA_NODE_ID_SHFT 0
933 #define IBIA_NODE_ID_MASK (0x1ff)
934
935 /*
936 * Miscellaneous hub constants
937 */
938
939 /* Number of widgets supported by hub */
940 #define HUB_NUM_WIDGET 9
941 #define HUB_WIDGET_ID_MIN 0x8
942 #define HUB_WIDGET_ID_MAX 0xf
943
944 #define HUB_WIDGET_PART_NUM 0xc101
945 #define MAX_HUBS_PER_XBOW 2
946
947 /*
948 * Get a hub's widget id from widget control register
949 */
950 #define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
951 #define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
952
953 /*
954 * Number of credits Hub widget has while sending req/response to
955 * xbow.
956 * Value of 3 is required by Xbow 1.1
957 * We may be able to increase this to 4 with Xbow 1.2.
958 */
959 #define HUBII_XBOW_CREDIT 3
960 #define HUBII_XBOW_REV2_CREDIT 4
961
962 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */
Tomato firmware and modifications.