release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-rc32434/integ.h

   1 /*
   2  *  Definitions for the Watchdog registers
   3  *
   4  *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
   5  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  */
  28
  29 #ifndef __RC32434_INTEG_H__
  30 #define __RC32434_INTEG_H__
  31
  32 #include <asm/mach-rc32434/rb.h>
  33
  34 #define INTEG0_BASE_ADDR        0x18030030
  35
  36 struct integ {
  37         u32 errcs;                      /* sticky use ERRCS_ */
  38         u32 wtcount;                    /* Watchdog timer count reg. */
  39         u32 wtcompare;                  /* Watchdog timer timeout value. */
  40         u32 wtc;                        /* Watchdog timer control. use WTC_ */
  41 };
  42
  43 /* Error counters */
  44 #define RC32434_ERR_WTO         0
  45 #define RC32434_ERR_WNE         1
  46 #define RC32434_ERR_UCW         2
  47 #define RC32434_ERR_UCR         3
  48 #define RC32434_ERR_UPW         4
  49 #define RC32434_ERR_UPR         5
  50 #define RC32434_ERR_UDW         6
  51 #define RC32434_ERR_UDR         7
  52 #define RC32434_ERR_SAE         8
  53 #define RC32434_ERR_WRE         9
  54
  55 /* Watchdog control bits */
  56 #define RC32434_WTC_EN          0
  57 #define RC32434_WTC_TO          1
  58
  59 #endif  /* __RC32434_INTEG_H__ */