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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / mips / include / asm / mach-au1x00 / au1000.h
blob5ae6aa258f512399f47df84cc13f6478fdfe8dc9
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34 #ifndef _AU1000_H_
35 #define _AU1000_H_
36
37
38 #ifndef _LANGUAGE_ASSEMBLY
39
40 #include <linux/delay.h>
41 #include <linux/types.h>
42
43 #include <linux/io.h>
44 #include <linux/irq.h>
45
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
48 {
49 __asm__ volatile ("sync");
50 }
51
52 void static inline au_sync_udelay(int us)
53 {
54 __asm__ volatile ("sync");
55 udelay(us);
56 }
57
58 void static inline au_sync_delay(int ms)
59 {
60 __asm__ volatile ("sync");
61 mdelay(ms);
62 }
63
64 void static inline au_writeb(u8 val, unsigned long reg)
65 {
66 *(volatile u8 *)reg = val;
67 }
68
69 void static inline au_writew(u16 val, unsigned long reg)
70 {
71 *(volatile u16 *)reg = val;
72 }
73
74 void static inline au_writel(u32 val, unsigned long reg)
75 {
76 *(volatile u32 *)reg = val;
77 }
78
79 static inline u8 au_readb(unsigned long reg)
80 {
81 return *(volatile u8 *)reg;
82 }
83
84 static inline u16 au_readw(unsigned long reg)
85 {
86 return *(volatile u16 *)reg;
87 }
88
89 static inline u32 au_readl(unsigned long reg)
90 {
91 return *(volatile u32 *)reg;
92 }
93
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
96 {
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104 }
105
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
108 {
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131 }
132
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
139
140 static inline int alchemy_get_cputype(void)
141 {
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162 }
163
164 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165 {
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
167 int timeout, i;
168
169 /* check LSR TX_EMPTY bit */
170 timeout = 0xffffff;
171 do {
172 if (__raw_readl(base + 0x1c) & 0x20)
173 break;
174 /* slow down */
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
177 } while (--timeout);
178
179 __raw_writel(c, base + 0x04); /* tx */
180 wmb();
181 }
182
183 /* arch/mips/au1000/common/clocks.c */
184 extern void set_au1x00_speed(unsigned int new_freq);
185 extern unsigned int get_au1x00_speed(void);
186 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
187 extern unsigned long get_au1x00_uart_baud_base(void);
188 extern unsigned long au1xxx_calc_clock(void);
189
190 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
191 void alchemy_sleep_au1000(void);
192 void alchemy_sleep_au1550(void);
193 void au_sleep(void);
194
195
196 /* SOC Interrupt numbers */
197
198 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
199 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
200 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
201 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
202 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
203
204 enum soc_au1000_ints {
205 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
206 AU1000_UART0_INT = AU1000_FIRST_INT,
207 AU1000_UART1_INT,
208 AU1000_UART2_INT,
209 AU1000_UART3_INT,
210 AU1000_SSI0_INT,
211 AU1000_SSI1_INT,
212 AU1000_DMA_INT_BASE,
213
214 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
215 AU1000_TOY_MATCH0_INT,
216 AU1000_TOY_MATCH1_INT,
217 AU1000_TOY_MATCH2_INT,
218 AU1000_RTC_INT,
219 AU1000_RTC_MATCH0_INT,
220 AU1000_RTC_MATCH1_INT,
221 AU1000_RTC_MATCH2_INT,
222 AU1000_IRDA_TX_INT,
223 AU1000_IRDA_RX_INT,
224 AU1000_USB_DEV_REQ_INT,
225 AU1000_USB_DEV_SUS_INT,
226 AU1000_USB_HOST_INT,
227 AU1000_ACSYNC_INT,
228 AU1000_MAC0_DMA_INT,
229 AU1000_MAC1_DMA_INT,
230 AU1000_I2S_UO_INT,
231 AU1000_AC97C_INT,
232 AU1000_GPIO0_INT,
233 AU1000_GPIO1_INT,
234 AU1000_GPIO2_INT,
235 AU1000_GPIO3_INT,
236 AU1000_GPIO4_INT,
237 AU1000_GPIO5_INT,
238 AU1000_GPIO6_INT,
239 AU1000_GPIO7_INT,
240 AU1000_GPIO8_INT,
241 AU1000_GPIO9_INT,
242 AU1000_GPIO10_INT,
243 AU1000_GPIO11_INT,
244 AU1000_GPIO12_INT,
245 AU1000_GPIO13_INT,
246 AU1000_GPIO14_INT,
247 AU1000_GPIO15_INT,
248 AU1000_GPIO16_INT,
249 AU1000_GPIO17_INT,
250 AU1000_GPIO18_INT,
251 AU1000_GPIO19_INT,
252 AU1000_GPIO20_INT,
253 AU1000_GPIO21_INT,
254 AU1000_GPIO22_INT,
255 AU1000_GPIO23_INT,
256 AU1000_GPIO24_INT,
257 AU1000_GPIO25_INT,
258 AU1000_GPIO26_INT,
259 AU1000_GPIO27_INT,
260 AU1000_GPIO28_INT,
261 AU1000_GPIO29_INT,
262 AU1000_GPIO30_INT,
263 AU1000_GPIO31_INT,
264 };
265
266 enum soc_au1100_ints {
267 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
268 AU1100_UART0_INT = AU1100_FIRST_INT,
269 AU1100_UART1_INT,
270 AU1100_SD_INT,
271 AU1100_UART3_INT,
272 AU1100_SSI0_INT,
273 AU1100_SSI1_INT,
274 AU1100_DMA_INT_BASE,
275
276 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
277 AU1100_TOY_MATCH0_INT,
278 AU1100_TOY_MATCH1_INT,
279 AU1100_TOY_MATCH2_INT,
280 AU1100_RTC_INT,
281 AU1100_RTC_MATCH0_INT,
282 AU1100_RTC_MATCH1_INT,
283 AU1100_RTC_MATCH2_INT,
284 AU1100_IRDA_TX_INT,
285 AU1100_IRDA_RX_INT,
286 AU1100_USB_DEV_REQ_INT,
287 AU1100_USB_DEV_SUS_INT,
288 AU1100_USB_HOST_INT,
289 AU1100_ACSYNC_INT,
290 AU1100_MAC0_DMA_INT,
291 AU1100_GPIO208_215_INT,
292 AU1100_LCD_INT,
293 AU1100_AC97C_INT,
294 AU1100_GPIO0_INT,
295 AU1100_GPIO1_INT,
296 AU1100_GPIO2_INT,
297 AU1100_GPIO3_INT,
298 AU1100_GPIO4_INT,
299 AU1100_GPIO5_INT,
300 AU1100_GPIO6_INT,
301 AU1100_GPIO7_INT,
302 AU1100_GPIO8_INT,
303 AU1100_GPIO9_INT,
304 AU1100_GPIO10_INT,
305 AU1100_GPIO11_INT,
306 AU1100_GPIO12_INT,
307 AU1100_GPIO13_INT,
308 AU1100_GPIO14_INT,
309 AU1100_GPIO15_INT,
310 AU1100_GPIO16_INT,
311 AU1100_GPIO17_INT,
312 AU1100_GPIO18_INT,
313 AU1100_GPIO19_INT,
314 AU1100_GPIO20_INT,
315 AU1100_GPIO21_INT,
316 AU1100_GPIO22_INT,
317 AU1100_GPIO23_INT,
318 AU1100_GPIO24_INT,
319 AU1100_GPIO25_INT,
320 AU1100_GPIO26_INT,
321 AU1100_GPIO27_INT,
322 AU1100_GPIO28_INT,
323 AU1100_GPIO29_INT,
324 AU1100_GPIO30_INT,
325 AU1100_GPIO31_INT,
326 };
327
328 enum soc_au1500_ints {
329 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
330 AU1500_UART0_INT = AU1500_FIRST_INT,
331 AU1500_PCI_INTA,
332 AU1500_PCI_INTB,
333 AU1500_UART3_INT,
334 AU1500_PCI_INTC,
335 AU1500_PCI_INTD,
336 AU1500_DMA_INT_BASE,
337
338 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
339 AU1500_TOY_MATCH0_INT,
340 AU1500_TOY_MATCH1_INT,
341 AU1500_TOY_MATCH2_INT,
342 AU1500_RTC_INT,
343 AU1500_RTC_MATCH0_INT,
344 AU1500_RTC_MATCH1_INT,
345 AU1500_RTC_MATCH2_INT,
346 AU1500_PCI_ERR_INT,
347 AU1500_RESERVED_INT,
348 AU1500_USB_DEV_REQ_INT,
349 AU1500_USB_DEV_SUS_INT,
350 AU1500_USB_HOST_INT,
351 AU1500_ACSYNC_INT,
352 AU1500_MAC0_DMA_INT,
353 AU1500_MAC1_DMA_INT,
354 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
355 AU1500_GPIO0_INT,
356 AU1500_GPIO1_INT,
357 AU1500_GPIO2_INT,
358 AU1500_GPIO3_INT,
359 AU1500_GPIO4_INT,
360 AU1500_GPIO5_INT,
361 AU1500_GPIO6_INT,
362 AU1500_GPIO7_INT,
363 AU1500_GPIO8_INT,
364 AU1500_GPIO9_INT,
365 AU1500_GPIO10_INT,
366 AU1500_GPIO11_INT,
367 AU1500_GPIO12_INT,
368 AU1500_GPIO13_INT,
369 AU1500_GPIO14_INT,
370 AU1500_GPIO15_INT,
371 AU1500_GPIO200_INT,
372 AU1500_GPIO201_INT,
373 AU1500_GPIO202_INT,
374 AU1500_GPIO203_INT,
375 AU1500_GPIO20_INT,
376 AU1500_GPIO204_INT,
377 AU1500_GPIO205_INT,
378 AU1500_GPIO23_INT,
379 AU1500_GPIO24_INT,
380 AU1500_GPIO25_INT,
381 AU1500_GPIO26_INT,
382 AU1500_GPIO27_INT,
383 AU1500_GPIO28_INT,
384 AU1500_GPIO206_INT,
385 AU1500_GPIO207_INT,
386 AU1500_GPIO208_215_INT,
387 };
388
389 enum soc_au1550_ints {
390 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
391 AU1550_UART0_INT = AU1550_FIRST_INT,
392 AU1550_PCI_INTA,
393 AU1550_PCI_INTB,
394 AU1550_DDMA_INT,
395 AU1550_CRYPTO_INT,
396 AU1550_PCI_INTC,
397 AU1550_PCI_INTD,
398 AU1550_PCI_RST_INT,
399 AU1550_UART1_INT,
400 AU1550_UART3_INT,
401 AU1550_PSC0_INT,
402 AU1550_PSC1_INT,
403 AU1550_PSC2_INT,
404 AU1550_PSC3_INT,
405 AU1550_TOY_INT,
406 AU1550_TOY_MATCH0_INT,
407 AU1550_TOY_MATCH1_INT,
408 AU1550_TOY_MATCH2_INT,
409 AU1550_RTC_INT,
410 AU1550_RTC_MATCH0_INT,
411 AU1550_RTC_MATCH1_INT,
412 AU1550_RTC_MATCH2_INT,
413
414 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
415 AU1550_USB_DEV_REQ_INT,
416 AU1550_USB_DEV_SUS_INT,
417 AU1550_USB_HOST_INT,
418 AU1550_MAC0_DMA_INT,
419 AU1550_MAC1_DMA_INT,
420 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
421 AU1550_GPIO1_INT,
422 AU1550_GPIO2_INT,
423 AU1550_GPIO3_INT,
424 AU1550_GPIO4_INT,
425 AU1550_GPIO5_INT,
426 AU1550_GPIO6_INT,
427 AU1550_GPIO7_INT,
428 AU1550_GPIO8_INT,
429 AU1550_GPIO9_INT,
430 AU1550_GPIO10_INT,
431 AU1550_GPIO11_INT,
432 AU1550_GPIO12_INT,
433 AU1550_GPIO13_INT,
434 AU1550_GPIO14_INT,
435 AU1550_GPIO15_INT,
436 AU1550_GPIO200_INT,
437 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
438 AU1550_GPIO16_INT,
439 AU1550_GPIO17_INT,
440 AU1550_GPIO20_INT,
441 AU1550_GPIO21_INT,
442 AU1550_GPIO22_INT,
443 AU1550_GPIO23_INT,
444 AU1550_GPIO24_INT,
445 AU1550_GPIO25_INT,
446 AU1550_GPIO26_INT,
447 AU1550_GPIO27_INT,
448 AU1550_GPIO28_INT,
449 AU1550_GPIO206_INT,
450 AU1550_GPIO207_INT,
451 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
452 };
453
454 enum soc_au1200_ints {
455 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
456 AU1200_UART0_INT = AU1200_FIRST_INT,
457 AU1200_SWT_INT,
458 AU1200_SD_INT,
459 AU1200_DDMA_INT,
460 AU1200_MAE_BE_INT,
461 AU1200_GPIO200_INT,
462 AU1200_GPIO201_INT,
463 AU1200_GPIO202_INT,
464 AU1200_UART1_INT,
465 AU1200_MAE_FE_INT,
466 AU1200_PSC0_INT,
467 AU1200_PSC1_INT,
468 AU1200_AES_INT,
469 AU1200_CAMERA_INT,
470 AU1200_TOY_INT,
471 AU1200_TOY_MATCH0_INT,
472 AU1200_TOY_MATCH1_INT,
473 AU1200_TOY_MATCH2_INT,
474 AU1200_RTC_INT,
475 AU1200_RTC_MATCH0_INT,
476 AU1200_RTC_MATCH1_INT,
477 AU1200_RTC_MATCH2_INT,
478 AU1200_GPIO203_INT,
479 AU1200_NAND_INT,
480 AU1200_GPIO204_INT,
481 AU1200_GPIO205_INT,
482 AU1200_GPIO206_INT,
483 AU1200_GPIO207_INT,
484 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
485 AU1200_USB_INT,
486 AU1200_LCD_INT,
487 AU1200_MAE_BOTH_INT,
488 AU1200_GPIO0_INT,
489 AU1200_GPIO1_INT,
490 AU1200_GPIO2_INT,
491 AU1200_GPIO3_INT,
492 AU1200_GPIO4_INT,
493 AU1200_GPIO5_INT,
494 AU1200_GPIO6_INT,
495 AU1200_GPIO7_INT,
496 AU1200_GPIO8_INT,
497 AU1200_GPIO9_INT,
498 AU1200_GPIO10_INT,
499 AU1200_GPIO11_INT,
500 AU1200_GPIO12_INT,
501 AU1200_GPIO13_INT,
502 AU1200_GPIO14_INT,
503 AU1200_GPIO15_INT,
504 AU1200_GPIO16_INT,
505 AU1200_GPIO17_INT,
506 AU1200_GPIO18_INT,
507 AU1200_GPIO19_INT,
508 AU1200_GPIO20_INT,
509 AU1200_GPIO21_INT,
510 AU1200_GPIO22_INT,
511 AU1200_GPIO23_INT,
512 AU1200_GPIO24_INT,
513 AU1200_GPIO25_INT,
514 AU1200_GPIO26_INT,
515 AU1200_GPIO27_INT,
516 AU1200_GPIO28_INT,
517 AU1200_GPIO29_INT,
518 AU1200_GPIO30_INT,
519 AU1200_GPIO31_INT,
520 };
521
522 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
523
524 /*
525 * SDRAM register offsets
526 */
527 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
528 defined(CONFIG_SOC_AU1100)
529 #define MEM_SDMODE0 0x0000
530 #define MEM_SDMODE1 0x0004
531 #define MEM_SDMODE2 0x0008
532 #define MEM_SDADDR0 0x000C
533 #define MEM_SDADDR1 0x0010
534 #define MEM_SDADDR2 0x0014
535 #define MEM_SDREFCFG 0x0018
536 #define MEM_SDPRECMD 0x001C
537 #define MEM_SDAUTOREF 0x0020
538 #define MEM_SDWRMD0 0x0024
539 #define MEM_SDWRMD1 0x0028
540 #define MEM_SDWRMD2 0x002C
541 #define MEM_SDSLEEP 0x0030
542 #define MEM_SDSMCKE 0x0034
543
544 /*
545 * MEM_SDMODE register content definitions
546 */
547 #define MEM_SDMODE_F (1 << 22)
548 #define MEM_SDMODE_SR (1 << 21)
549 #define MEM_SDMODE_BS (1 << 20)
550 #define MEM_SDMODE_RS (3 << 18)
551 #define MEM_SDMODE_CS (7 << 15)
552 #define MEM_SDMODE_TRAS (15 << 11)
553 #define MEM_SDMODE_TMRD (3 << 9)
554 #define MEM_SDMODE_TWR (3 << 7)
555 #define MEM_SDMODE_TRP (3 << 5)
556 #define MEM_SDMODE_TRCD (3 << 3)
557 #define MEM_SDMODE_TCL (7 << 0)
558
559 #define MEM_SDMODE_BS_2Bank (0 << 20)
560 #define MEM_SDMODE_BS_4Bank (1 << 20)
561 #define MEM_SDMODE_RS_11Row (0 << 18)
562 #define MEM_SDMODE_RS_12Row (1 << 18)
563 #define MEM_SDMODE_RS_13Row (2 << 18)
564 #define MEM_SDMODE_RS_N(N) ((N) << 18)
565 #define MEM_SDMODE_CS_7Col (0 << 15)
566 #define MEM_SDMODE_CS_8Col (1 << 15)
567 #define MEM_SDMODE_CS_9Col (2 << 15)
568 #define MEM_SDMODE_CS_10Col (3 << 15)
569 #define MEM_SDMODE_CS_11Col (4 << 15)
570 #define MEM_SDMODE_CS_N(N) ((N) << 15)
571 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
572 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
573 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
574 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
575 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
576 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
577
578 /*
579 * MEM_SDADDR register contents definitions
580 */
581 #define MEM_SDADDR_E (1 << 20)
582 #define MEM_SDADDR_CSBA (0x03FF << 10)
583 #define MEM_SDADDR_CSMASK (0x03FF << 0)
584 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
585 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
586
587 /*
588 * MEM_SDREFCFG register content definitions
589 */
590 #define MEM_SDREFCFG_TRC (15 << 28)
591 #define MEM_SDREFCFG_TRPM (3 << 26)
592 #define MEM_SDREFCFG_E (1 << 25)
593 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
594 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
595 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
596 #define MEM_SDREFCFG_REF_N(N) (N)
597 #endif
598
599 /***********************************************************************/
600
601 /*
602 * Au1550 SDRAM Register Offsets
603 */
604
605 /***********************************************************************/
606
607 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
608 #define MEM_SDMODE0 0x0800
609 #define MEM_SDMODE1 0x0808
610 #define MEM_SDMODE2 0x0810
611 #define MEM_SDADDR0 0x0820
612 #define MEM_SDADDR1 0x0828
613 #define MEM_SDADDR2 0x0830
614 #define MEM_SDCONFIGA 0x0840
615 #define MEM_SDCONFIGB 0x0848
616 #define MEM_SDSTAT 0x0850
617 #define MEM_SDERRADDR 0x0858
618 #define MEM_SDSTRIDE0 0x0860
619 #define MEM_SDSTRIDE1 0x0868
620 #define MEM_SDSTRIDE2 0x0870
621 #define MEM_SDWRMD0 0x0880
622 #define MEM_SDWRMD1 0x0888
623 #define MEM_SDWRMD2 0x0890
624 #define MEM_SDPRECMD 0x08C0
625 #define MEM_SDAUTOREF 0x08C8
626 #define MEM_SDSREF 0x08D0
627 #define MEM_SDSLEEP MEM_SDSREF
628
629 #endif
630
631 /*
632 * Physical base addresses for integrated peripherals
633 */
634
635 #ifdef CONFIG_SOC_AU1000
636 #define MEM_PHYS_ADDR 0x14000000
637 #define STATIC_MEM_PHYS_ADDR 0x14001000
638 #define DMA0_PHYS_ADDR 0x14002000
639 #define DMA1_PHYS_ADDR 0x14002100
640 #define DMA2_PHYS_ADDR 0x14002200
641 #define DMA3_PHYS_ADDR 0x14002300
642 #define DMA4_PHYS_ADDR 0x14002400
643 #define DMA5_PHYS_ADDR 0x14002500
644 #define DMA6_PHYS_ADDR 0x14002600
645 #define DMA7_PHYS_ADDR 0x14002700
646 #define IC0_PHYS_ADDR 0x10400000
647 #define IC1_PHYS_ADDR 0x11800000
648 #define AC97_PHYS_ADDR 0x10000000
649 #define USBH_PHYS_ADDR 0x10100000
650 #define USBD_PHYS_ADDR 0x10200000
651 #define IRDA_PHYS_ADDR 0x10300000
652 #define MAC0_PHYS_ADDR 0x10500000
653 #define MAC1_PHYS_ADDR 0x10510000
654 #define MACEN_PHYS_ADDR 0x10520000
655 #define MACDMA0_PHYS_ADDR 0x14004000
656 #define MACDMA1_PHYS_ADDR 0x14004200
657 #define I2S_PHYS_ADDR 0x11000000
658 #define UART0_PHYS_ADDR 0x11100000
659 #define UART1_PHYS_ADDR 0x11200000
660 #define UART2_PHYS_ADDR 0x11300000
661 #define UART3_PHYS_ADDR 0x11400000
662 #define SSI0_PHYS_ADDR 0x11600000
663 #define SSI1_PHYS_ADDR 0x11680000
664 #define SYS_PHYS_ADDR 0x11900000
665 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
666 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
667 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
668 #endif
669
670 /********************************************************************/
671
672 #ifdef CONFIG_SOC_AU1500
673 #define MEM_PHYS_ADDR 0x14000000
674 #define STATIC_MEM_PHYS_ADDR 0x14001000
675 #define DMA0_PHYS_ADDR 0x14002000
676 #define DMA1_PHYS_ADDR 0x14002100
677 #define DMA2_PHYS_ADDR 0x14002200
678 #define DMA3_PHYS_ADDR 0x14002300
679 #define DMA4_PHYS_ADDR 0x14002400
680 #define DMA5_PHYS_ADDR 0x14002500
681 #define DMA6_PHYS_ADDR 0x14002600
682 #define DMA7_PHYS_ADDR 0x14002700
683 #define IC0_PHYS_ADDR 0x10400000
684 #define IC1_PHYS_ADDR 0x11800000
685 #define AC97_PHYS_ADDR 0x10000000
686 #define USBH_PHYS_ADDR 0x10100000
687 #define USBD_PHYS_ADDR 0x10200000
688 #define PCI_PHYS_ADDR 0x14005000
689 #define MAC0_PHYS_ADDR 0x11500000
690 #define MAC1_PHYS_ADDR 0x11510000
691 #define MACEN_PHYS_ADDR 0x11520000
692 #define MACDMA0_PHYS_ADDR 0x14004000
693 #define MACDMA1_PHYS_ADDR 0x14004200
694 #define I2S_PHYS_ADDR 0x11000000
695 #define UART0_PHYS_ADDR 0x11100000
696 #define UART3_PHYS_ADDR 0x11400000
697 #define GPIO2_PHYS_ADDR 0x11700000
698 #define SYS_PHYS_ADDR 0x11900000
699 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
700 #define PCI_IO_PHYS_ADDR 0x500000000ULL
701 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
702 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
703 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
704 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
705 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
706 #endif
707
708 /********************************************************************/
709
710 #ifdef CONFIG_SOC_AU1100
711 #define MEM_PHYS_ADDR 0x14000000
712 #define STATIC_MEM_PHYS_ADDR 0x14001000
713 #define DMA0_PHYS_ADDR 0x14002000
714 #define DMA1_PHYS_ADDR 0x14002100
715 #define DMA2_PHYS_ADDR 0x14002200
716 #define DMA3_PHYS_ADDR 0x14002300
717 #define DMA4_PHYS_ADDR 0x14002400
718 #define DMA5_PHYS_ADDR 0x14002500
719 #define DMA6_PHYS_ADDR 0x14002600
720 #define DMA7_PHYS_ADDR 0x14002700
721 #define IC0_PHYS_ADDR 0x10400000
722 #define SD0_PHYS_ADDR 0x10600000
723 #define SD1_PHYS_ADDR 0x10680000
724 #define IC1_PHYS_ADDR 0x11800000
725 #define AC97_PHYS_ADDR 0x10000000
726 #define USBH_PHYS_ADDR 0x10100000
727 #define USBD_PHYS_ADDR 0x10200000
728 #define IRDA_PHYS_ADDR 0x10300000
729 #define MAC0_PHYS_ADDR 0x10500000
730 #define MACEN_PHYS_ADDR 0x10520000
731 #define MACDMA0_PHYS_ADDR 0x14004000
732 #define MACDMA1_PHYS_ADDR 0x14004200
733 #define I2S_PHYS_ADDR 0x11000000
734 #define UART0_PHYS_ADDR 0x11100000
735 #define UART1_PHYS_ADDR 0x11200000
736 #define UART3_PHYS_ADDR 0x11400000
737 #define SSI0_PHYS_ADDR 0x11600000
738 #define SSI1_PHYS_ADDR 0x11680000
739 #define GPIO2_PHYS_ADDR 0x11700000
740 #define SYS_PHYS_ADDR 0x11900000
741 #define LCD_PHYS_ADDR 0x15000000
742 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
743 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
744 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
745 #endif
746
747 /***********************************************************************/
748
749 #ifdef CONFIG_SOC_AU1550
750 #define MEM_PHYS_ADDR 0x14000000
751 #define STATIC_MEM_PHYS_ADDR 0x14001000
752 #define IC0_PHYS_ADDR 0x10400000
753 #define IC1_PHYS_ADDR 0x11800000
754 #define USBH_PHYS_ADDR 0x14020000
755 #define USBD_PHYS_ADDR 0x10200000
756 #define PCI_PHYS_ADDR 0x14005000
757 #define MAC0_PHYS_ADDR 0x10500000
758 #define MAC1_PHYS_ADDR 0x10510000
759 #define MACEN_PHYS_ADDR 0x10520000
760 #define MACDMA0_PHYS_ADDR 0x14004000
761 #define MACDMA1_PHYS_ADDR 0x14004200
762 #define UART0_PHYS_ADDR 0x11100000
763 #define UART1_PHYS_ADDR 0x11200000
764 #define UART3_PHYS_ADDR 0x11400000
765 #define GPIO2_PHYS_ADDR 0x11700000
766 #define SYS_PHYS_ADDR 0x11900000
767 #define DDMA_PHYS_ADDR 0x14002000
768 #define PE_PHYS_ADDR 0x14008000
769 #define PSC0_PHYS_ADDR 0x11A00000
770 #define PSC1_PHYS_ADDR 0x11B00000
771 #define PSC2_PHYS_ADDR 0x10A00000
772 #define PSC3_PHYS_ADDR 0x10B00000
773 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
774 #define PCI_IO_PHYS_ADDR 0x500000000ULL
775 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
776 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
777 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
778 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
779 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
780 #endif
781
782 /***********************************************************************/
783
784 #ifdef CONFIG_SOC_AU1200
785 #define MEM_PHYS_ADDR 0x14000000
786 #define STATIC_MEM_PHYS_ADDR 0x14001000
787 #define AES_PHYS_ADDR 0x10300000
788 #define CIM_PHYS_ADDR 0x14004000
789 #define IC0_PHYS_ADDR 0x10400000
790 #define IC1_PHYS_ADDR 0x11800000
791 #define USBM_PHYS_ADDR 0x14020000
792 #define USBH_PHYS_ADDR 0x14020100
793 #define UART0_PHYS_ADDR 0x11100000
794 #define UART1_PHYS_ADDR 0x11200000
795 #define GPIO2_PHYS_ADDR 0x11700000
796 #define SYS_PHYS_ADDR 0x11900000
797 #define DDMA_PHYS_ADDR 0x14002000
798 #define PSC0_PHYS_ADDR 0x11A00000
799 #define PSC1_PHYS_ADDR 0x11B00000
800 #define SD0_PHYS_ADDR 0x10600000
801 #define SD1_PHYS_ADDR 0x10680000
802 #define LCD_PHYS_ADDR 0x15000000
803 #define SWCNT_PHYS_ADDR 0x1110010C
804 #define MAEFE_PHYS_ADDR 0x14012000
805 #define MAEBE_PHYS_ADDR 0x14010000
806 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
807 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
808 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
809 #endif
810
811 /* Static Bus Controller */
812 #define MEM_STCFG0 0xB4001000
813 #define MEM_STTIME0 0xB4001004
814 #define MEM_STADDR0 0xB4001008
815
816 #define MEM_STCFG1 0xB4001010
817 #define MEM_STTIME1 0xB4001014
818 #define MEM_STADDR1 0xB4001018
819
820 #define MEM_STCFG2 0xB4001020
821 #define MEM_STTIME2 0xB4001024
822 #define MEM_STADDR2 0xB4001028
823
824 #define MEM_STCFG3 0xB4001030
825 #define MEM_STTIME3 0xB4001034
826 #define MEM_STADDR3 0xB4001038
827
828 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
829 #define MEM_STNDCTL 0xB4001100
830 #define MEM_STSTAT 0xB4001104
831
832 #define MEM_STNAND_CMD 0x0
833 #define MEM_STNAND_ADDR 0x4
834 #define MEM_STNAND_DATA 0x20
835 #endif
836
837
838 /* Interrupt Controller register offsets */
839 #define IC_CFG0RD 0x40
840 #define IC_CFG0SET 0x40
841 #define IC_CFG0CLR 0x44
842 #define IC_CFG1RD 0x48
843 #define IC_CFG1SET 0x48
844 #define IC_CFG1CLR 0x4C
845 #define IC_CFG2RD 0x50
846 #define IC_CFG2SET 0x50
847 #define IC_CFG2CLR 0x54
848 #define IC_REQ0INT 0x54
849 #define IC_SRCRD 0x58
850 #define IC_SRCSET 0x58
851 #define IC_SRCCLR 0x5C
852 #define IC_REQ1INT 0x5C
853 #define IC_ASSIGNRD 0x60
854 #define IC_ASSIGNSET 0x60
855 #define IC_ASSIGNCLR 0x64
856 #define IC_WAKERD 0x68
857 #define IC_WAKESET 0x68
858 #define IC_WAKECLR 0x6C
859 #define IC_MASKRD 0x70
860 #define IC_MASKSET 0x70
861 #define IC_MASKCLR 0x74
862 #define IC_RISINGRD 0x78
863 #define IC_RISINGCLR 0x78
864 #define IC_FALLINGRD 0x7C
865 #define IC_FALLINGCLR 0x7C
866 #define IC_TESTBIT 0x80
867
868
869 /* Interrupt Controller 0 */
870 #define IC0_CFG0RD 0xB0400040
871 #define IC0_CFG0SET 0xB0400040
872 #define IC0_CFG0CLR 0xB0400044
873
874 #define IC0_CFG1RD 0xB0400048
875 #define IC0_CFG1SET 0xB0400048
876 #define IC0_CFG1CLR 0xB040004C
877
878 #define IC0_CFG2RD 0xB0400050
879 #define IC0_CFG2SET 0xB0400050
880 #define IC0_CFG2CLR 0xB0400054
881
882 #define IC0_REQ0INT 0xB0400054
883 #define IC0_SRCRD 0xB0400058
884 #define IC0_SRCSET 0xB0400058
885 #define IC0_SRCCLR 0xB040005C
886 #define IC0_REQ1INT 0xB040005C
887
888 #define IC0_ASSIGNRD 0xB0400060
889 #define IC0_ASSIGNSET 0xB0400060
890 #define IC0_ASSIGNCLR 0xB0400064
891
892 #define IC0_WAKERD 0xB0400068
893 #define IC0_WAKESET 0xB0400068
894 #define IC0_WAKECLR 0xB040006C
895
896 #define IC0_MASKRD 0xB0400070
897 #define IC0_MASKSET 0xB0400070
898 #define IC0_MASKCLR 0xB0400074
899
900 #define IC0_RISINGRD 0xB0400078
901 #define IC0_RISINGCLR 0xB0400078
902 #define IC0_FALLINGRD 0xB040007C
903 #define IC0_FALLINGCLR 0xB040007C
904
905 #define IC0_TESTBIT 0xB0400080
906
907 /* Interrupt Controller 1 */
908 #define IC1_CFG0RD 0xB1800040
909 #define IC1_CFG0SET 0xB1800040
910 #define IC1_CFG0CLR 0xB1800044
911
912 #define IC1_CFG1RD 0xB1800048
913 #define IC1_CFG1SET 0xB1800048
914 #define IC1_CFG1CLR 0xB180004C
915
916 #define IC1_CFG2RD 0xB1800050
917 #define IC1_CFG2SET 0xB1800050
918 #define IC1_CFG2CLR 0xB1800054
919
920 #define IC1_REQ0INT 0xB1800054
921 #define IC1_SRCRD 0xB1800058
922 #define IC1_SRCSET 0xB1800058
923 #define IC1_SRCCLR 0xB180005C
924 #define IC1_REQ1INT 0xB180005C
925
926 #define IC1_ASSIGNRD 0xB1800060
927 #define IC1_ASSIGNSET 0xB1800060
928 #define IC1_ASSIGNCLR 0xB1800064
929
930 #define IC1_WAKERD 0xB1800068
931 #define IC1_WAKESET 0xB1800068
932 #define IC1_WAKECLR 0xB180006C
933
934 #define IC1_MASKRD 0xB1800070
935 #define IC1_MASKSET 0xB1800070
936 #define IC1_MASKCLR 0xB1800074
937
938 #define IC1_RISINGRD 0xB1800078
939 #define IC1_RISINGCLR 0xB1800078
940 #define IC1_FALLINGRD 0xB180007C
941 #define IC1_FALLINGCLR 0xB180007C
942
943 #define IC1_TESTBIT 0xB1800080
944
945
946 /* Au1000 */
947 #ifdef CONFIG_SOC_AU1000
948
949 #define UART0_ADDR 0xB1100000
950 #define UART3_ADDR 0xB1400000
951
952 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
953 #define USB_HOST_CONFIG 0xB017FFFC
954 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
955
956 #define AU1000_ETH0_BASE 0xB0500000
957 #define AU1000_ETH1_BASE 0xB0510000
958 #define AU1000_MAC0_ENABLE 0xB0520000
959 #define AU1000_MAC1_ENABLE 0xB0520004
960 #define NUM_ETH_INTERFACES 2
961 #endif /* CONFIG_SOC_AU1000 */
962
963 /* Au1500 */
964 #ifdef CONFIG_SOC_AU1500
965
966 #define UART0_ADDR 0xB1100000
967 #define UART3_ADDR 0xB1400000
968
969 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
970 #define USB_HOST_CONFIG 0xB017fffc
971 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
972
973 #define AU1500_ETH0_BASE 0xB1500000
974 #define AU1500_ETH1_BASE 0xB1510000
975 #define AU1500_MAC0_ENABLE 0xB1520000
976 #define AU1500_MAC1_ENABLE 0xB1520004
977 #define NUM_ETH_INTERFACES 2
978 #endif /* CONFIG_SOC_AU1500 */
979
980 /* Au1100 */
981 #ifdef CONFIG_SOC_AU1100
982
983 #define UART0_ADDR 0xB1100000
984 #define UART3_ADDR 0xB1400000
985
986 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
987 #define USB_HOST_CONFIG 0xB017FFFC
988 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
989
990 #define AU1100_ETH0_BASE 0xB0500000
991 #define AU1100_MAC0_ENABLE 0xB0520000
992 #define NUM_ETH_INTERFACES 1
993 #endif /* CONFIG_SOC_AU1100 */
994
995 #ifdef CONFIG_SOC_AU1550
996 #define UART0_ADDR 0xB1100000
997
998 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
999 #define USB_OHCI_LEN 0x00060000
1000 #define USB_HOST_CONFIG 0xB4027ffc
1001 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
1002
1003 #define AU1550_ETH0_BASE 0xB0500000
1004 #define AU1550_ETH1_BASE 0xB0510000
1005 #define AU1550_MAC0_ENABLE 0xB0520000
1006 #define AU1550_MAC1_ENABLE 0xB0520004
1007 #define NUM_ETH_INTERFACES 2
1008 #endif /* CONFIG_SOC_AU1550 */
1009
1010
1011 #ifdef CONFIG_SOC_AU1200
1012
1013 #define UART0_ADDR 0xB1100000
1014
1015 #define USB_UOC_BASE 0x14020020
1016 #define USB_UOC_LEN 0x20
1017 #define USB_OHCI_BASE 0x14020100
1018 #define USB_OHCI_LEN 0x100
1019 #define USB_EHCI_BASE 0x14020200
1020 #define USB_EHCI_LEN 0x100
1021 #define USB_UDC_BASE 0x14022000
1022 #define USB_UDC_LEN 0x2000
1023 #define USB_MSR_BASE 0xB4020000
1024 #define USB_MSR_MCFG 4
1025 #define USBMSRMCFG_OMEMEN 0
1026 #define USBMSRMCFG_OBMEN 1
1027 #define USBMSRMCFG_EMEMEN 2
1028 #define USBMSRMCFG_EBMEN 3
1029 #define USBMSRMCFG_DMEMEN 4
1030 #define USBMSRMCFG_DBMEN 5
1031 #define USBMSRMCFG_GMEMEN 6
1032 #define USBMSRMCFG_OHCCLKEN 16
1033 #define USBMSRMCFG_EHCCLKEN 17
1034 #define USBMSRMCFG_UDCCLKEN 18
1035 #define USBMSRMCFG_PHYPLLEN 19
1036 #define USBMSRMCFG_RDCOMB 30
1037 #define USBMSRMCFG_PFEN 31
1038
1039 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
1040
1041 #endif /* CONFIG_SOC_AU1200 */
1042
1043 /* Programmable Counters 0 and 1 */
1044 #define SYS_BASE 0xB1900000
1045 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1046 # define SYS_CNTRL_E1S (1 << 23)
1047 # define SYS_CNTRL_T1S (1 << 20)
1048 # define SYS_CNTRL_M21 (1 << 19)
1049 # define SYS_CNTRL_M11 (1 << 18)
1050 # define SYS_CNTRL_M01 (1 << 17)
1051 # define SYS_CNTRL_C1S (1 << 16)
1052 # define SYS_CNTRL_BP (1 << 14)
1053 # define SYS_CNTRL_EN1 (1 << 13)
1054 # define SYS_CNTRL_BT1 (1 << 12)
1055 # define SYS_CNTRL_EN0 (1 << 11)
1056 # define SYS_CNTRL_BT0 (1 << 10)
1057 # define SYS_CNTRL_E0 (1 << 8)
1058 # define SYS_CNTRL_E0S (1 << 7)
1059 # define SYS_CNTRL_32S (1 << 5)
1060 # define SYS_CNTRL_T0S (1 << 4)
1061 # define SYS_CNTRL_M20 (1 << 3)
1062 # define SYS_CNTRL_M10 (1 << 2)
1063 # define SYS_CNTRL_M00 (1 << 1)
1064 # define SYS_CNTRL_C0S (1 << 0)
1065
1066 /* Programmable Counter 0 Registers */
1067 #define SYS_TOYTRIM (SYS_BASE + 0)
1068 #define SYS_TOYWRITE (SYS_BASE + 4)
1069 #define SYS_TOYMATCH0 (SYS_BASE + 8)
1070 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1071 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1072 #define SYS_TOYREAD (SYS_BASE + 0x40)
1073
1074 /* Programmable Counter 1 Registers */
1075 #define SYS_RTCTRIM (SYS_BASE + 0x44)
1076 #define SYS_RTCWRITE (SYS_BASE + 0x48)
1077 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1078 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1079 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1080 #define SYS_RTCREAD (SYS_BASE + 0x58)
1081
1082 /* I2S Controller */
1083 #define I2S_DATA 0xB1000000
1084 # define I2S_DATA_MASK 0xffffff
1085 #define I2S_CONFIG 0xB1000004
1086 # define I2S_CONFIG_XU (1 << 25)
1087 # define I2S_CONFIG_XO (1 << 24)
1088 # define I2S_CONFIG_RU (1 << 23)
1089 # define I2S_CONFIG_RO (1 << 22)
1090 # define I2S_CONFIG_TR (1 << 21)
1091 # define I2S_CONFIG_TE (1 << 20)
1092 # define I2S_CONFIG_TF (1 << 19)
1093 # define I2S_CONFIG_RR (1 << 18)
1094 # define I2S_CONFIG_RE (1 << 17)
1095 # define I2S_CONFIG_RF (1 << 16)
1096 # define I2S_CONFIG_PD (1 << 11)
1097 # define I2S_CONFIG_LB (1 << 10)
1098 # define I2S_CONFIG_IC (1 << 9)
1099 # define I2S_CONFIG_FM_BIT 7
1100 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1101 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1102 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1103 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1104 # define I2S_CONFIG_TN (1 << 6)
1105 # define I2S_CONFIG_RN (1 << 5)
1106 # define I2S_CONFIG_SZ_BIT 0
1107 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1108
1109 #define I2S_CONTROL 0xB1000008
1110 # define I2S_CONTROL_D (1 << 1)
1111 # define I2S_CONTROL_CE (1 << 0)
1112
1113 /* USB Host Controller */
1114 #ifndef USB_OHCI_LEN
1115 #define USB_OHCI_LEN 0x00100000
1116 #endif
1117
1118 #ifndef CONFIG_SOC_AU1200
1119
1120 /* USB Device Controller */
1121 #define USBD_EP0RD 0xB0200000
1122 #define USBD_EP0WR 0xB0200004
1123 #define USBD_EP2WR 0xB0200008
1124 #define USBD_EP3WR 0xB020000C
1125 #define USBD_EP4RD 0xB0200010
1126 #define USBD_EP5RD 0xB0200014
1127 #define USBD_INTEN 0xB0200018
1128 #define USBD_INTSTAT 0xB020001C
1129 # define USBDEV_INT_SOF (1 << 12)
1130 # define USBDEV_INT_HF_BIT 6
1131 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1132 # define USBDEV_INT_CMPLT_BIT 0
1133 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1134 #define USBD_CONFIG 0xB0200020
1135 #define USBD_EP0CS 0xB0200024
1136 #define USBD_EP2CS 0xB0200028
1137 #define USBD_EP3CS 0xB020002C
1138 #define USBD_EP4CS 0xB0200030
1139 #define USBD_EP5CS 0xB0200034
1140 # define USBDEV_CS_SU (1 << 14)
1141 # define USBDEV_CS_NAK (1 << 13)
1142 # define USBDEV_CS_ACK (1 << 12)
1143 # define USBDEV_CS_BUSY (1 << 11)
1144 # define USBDEV_CS_TSIZE_BIT 1
1145 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1146 # define USBDEV_CS_STALL (1 << 0)
1147 #define USBD_EP0RDSTAT 0xB0200040
1148 #define USBD_EP0WRSTAT 0xB0200044
1149 #define USBD_EP2WRSTAT 0xB0200048
1150 #define USBD_EP3WRSTAT 0xB020004C
1151 #define USBD_EP4RDSTAT 0xB0200050
1152 #define USBD_EP5RDSTAT 0xB0200054
1153 # define USBDEV_FSTAT_FLUSH (1 << 6)
1154 # define USBDEV_FSTAT_UF (1 << 5)
1155 # define USBDEV_FSTAT_OF (1 << 4)
1156 # define USBDEV_FSTAT_FCNT_BIT 0
1157 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1158 #define USBD_ENABLE 0xB0200058
1159 # define USBDEV_ENABLE (1 << 1)
1160 # define USBDEV_CE (1 << 0)
1161
1162 #endif /* !CONFIG_SOC_AU1200 */
1163
1164 /* Ethernet Controllers */
1165
1166 /* 4 byte offsets from AU1000_ETH_BASE */
1167 #define MAC_CONTROL 0x0
1168 # define MAC_RX_ENABLE (1 << 2)
1169 # define MAC_TX_ENABLE (1 << 3)
1170 # define MAC_DEF_CHECK (1 << 5)
1171 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1172 # define MAC_AUTO_PAD (1 << 8)
1173 # define MAC_DISABLE_RETRY (1 << 10)
1174 # define MAC_DISABLE_BCAST (1 << 11)
1175 # define MAC_LATE_COL (1 << 12)
1176 # define MAC_HASH_MODE (1 << 13)
1177 # define MAC_HASH_ONLY (1 << 15)
1178 # define MAC_PASS_ALL (1 << 16)
1179 # define MAC_INVERSE_FILTER (1 << 17)
1180 # define MAC_PROMISCUOUS (1 << 18)
1181 # define MAC_PASS_ALL_MULTI (1 << 19)
1182 # define MAC_FULL_DUPLEX (1 << 20)
1183 # define MAC_NORMAL_MODE 0
1184 # define MAC_INT_LOOPBACK (1 << 21)
1185 # define MAC_EXT_LOOPBACK (1 << 22)
1186 # define MAC_DISABLE_RX_OWN (1 << 23)
1187 # define MAC_BIG_ENDIAN (1 << 30)
1188 # define MAC_RX_ALL (1 << 31)
1189 #define MAC_ADDRESS_HIGH 0x4
1190 #define MAC_ADDRESS_LOW 0x8
1191 #define MAC_MCAST_HIGH 0xC
1192 #define MAC_MCAST_LOW 0x10
1193 #define MAC_MII_CNTRL 0x14
1194 # define MAC_MII_BUSY (1 << 0)
1195 # define MAC_MII_READ 0
1196 # define MAC_MII_WRITE (1 << 1)
1197 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1198 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1199 #define MAC_MII_DATA 0x18
1200 #define MAC_FLOW_CNTRL 0x1C
1201 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1202 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1203 # define MAC_PASS_CONTROL (1 << 2)
1204 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1205 #define MAC_VLAN1_TAG 0x20
1206 #define MAC_VLAN2_TAG 0x24
1207
1208 /* Ethernet Controller Enable */
1209
1210 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1211 # define MAC_EN_RESET0 (1 << 1)
1212 # define MAC_EN_TOSS (0 << 2)
1213 # define MAC_EN_CACHEABLE (1 << 3)
1214 # define MAC_EN_RESET1 (1 << 4)
1215 # define MAC_EN_RESET2 (1 << 5)
1216 # define MAC_DMA_RESET (1 << 6)
1217
1218 /* Ethernet Controller DMA Channels */
1219
1220 #define MAC0_TX_DMA_ADDR 0xB4004000
1221 #define MAC1_TX_DMA_ADDR 0xB4004200
1222 /* offsets from MAC_TX_RING_ADDR address */
1223 #define MAC_TX_BUFF0_STATUS 0x0
1224 # define TX_FRAME_ABORTED (1 << 0)
1225 # define TX_JAB_TIMEOUT (1 << 1)
1226 # define TX_NO_CARRIER (1 << 2)
1227 # define TX_LOSS_CARRIER (1 << 3)
1228 # define TX_EXC_DEF (1 << 4)
1229 # define TX_LATE_COLL_ABORT (1 << 5)
1230 # define TX_EXC_COLL (1 << 6)
1231 # define TX_UNDERRUN (1 << 7)
1232 # define TX_DEFERRED (1 << 8)
1233 # define TX_LATE_COLL (1 << 9)
1234 # define TX_COLL_CNT_MASK (0xF << 10)
1235 # define TX_PKT_RETRY (1 << 31)
1236 #define MAC_TX_BUFF0_ADDR 0x4
1237 # define TX_DMA_ENABLE (1 << 0)
1238 # define TX_T_DONE (1 << 1)
1239 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1240 #define MAC_TX_BUFF0_LEN 0x8
1241 #define MAC_TX_BUFF1_STATUS 0x10
1242 #define MAC_TX_BUFF1_ADDR 0x14
1243 #define MAC_TX_BUFF1_LEN 0x18
1244 #define MAC_TX_BUFF2_STATUS 0x20
1245 #define MAC_TX_BUFF2_ADDR 0x24
1246 #define MAC_TX_BUFF2_LEN 0x28
1247 #define MAC_TX_BUFF3_STATUS 0x30
1248 #define MAC_TX_BUFF3_ADDR 0x34
1249 #define MAC_TX_BUFF3_LEN 0x38
1250
1251 #define MAC0_RX_DMA_ADDR 0xB4004100
1252 #define MAC1_RX_DMA_ADDR 0xB4004300
1253 /* offsets from MAC_RX_RING_ADDR */
1254 #define MAC_RX_BUFF0_STATUS 0x0
1255 # define RX_FRAME_LEN_MASK 0x3fff
1256 # define RX_WDOG_TIMER (1 << 14)
1257 # define RX_RUNT (1 << 15)
1258 # define RX_OVERLEN (1 << 16)
1259 # define RX_COLL (1 << 17)
1260 # define RX_ETHER (1 << 18)
1261 # define RX_MII_ERROR (1 << 19)
1262 # define RX_DRIBBLING (1 << 20)
1263 # define RX_CRC_ERROR (1 << 21)
1264 # define RX_VLAN1 (1 << 22)
1265 # define RX_VLAN2 (1 << 23)
1266 # define RX_LEN_ERROR (1 << 24)
1267 # define RX_CNTRL_FRAME (1 << 25)
1268 # define RX_U_CNTRL_FRAME (1 << 26)
1269 # define RX_MCAST_FRAME (1 << 27)
1270 # define RX_BCAST_FRAME (1 << 28)
1271 # define RX_FILTER_FAIL (1 << 29)
1272 # define RX_PACKET_FILTER (1 << 30)
1273 # define RX_MISSED_FRAME (1 << 31)
1274
1275 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1276 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1277 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1278 #define MAC_RX_BUFF0_ADDR 0x4
1279 # define RX_DMA_ENABLE (1 << 0)
1280 # define RX_T_DONE (1 << 1)
1281 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1282 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1283 #define MAC_RX_BUFF1_STATUS 0x10
1284 #define MAC_RX_BUFF1_ADDR 0x14
1285 #define MAC_RX_BUFF2_STATUS 0x20
1286 #define MAC_RX_BUFF2_ADDR 0x24
1287 #define MAC_RX_BUFF3_STATUS 0x30
1288 #define MAC_RX_BUFF3_ADDR 0x34
1289
1290 #define UART_RX 0 /* Receive buffer */
1291 #define UART_TX 4 /* Transmit buffer */
1292 #define UART_IER 8 /* Interrupt Enable Register */
1293 #define UART_IIR 0xC /* Interrupt ID Register */
1294 #define UART_FCR 0x10 /* FIFO Control Register */
1295 #define UART_LCR 0x14 /* Line Control Register */
1296 #define UART_MCR 0x18 /* Modem Control Register */
1297 #define UART_LSR 0x1C /* Line Status Register */
1298 #define UART_MSR 0x20 /* Modem Status Register */
1299 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1300 #define UART_MOD_CNTRL 0x100 /* Module Control */
1301
1302 /* SSIO */
1303 #define SSI0_STATUS 0xB1600000
1304 # define SSI_STATUS_BF (1 << 4)
1305 # define SSI_STATUS_OF (1 << 3)
1306 # define SSI_STATUS_UF (1 << 2)
1307 # define SSI_STATUS_D (1 << 1)
1308 # define SSI_STATUS_B (1 << 0)
1309 #define SSI0_INT 0xB1600004
1310 # define SSI_INT_OI (1 << 3)
1311 # define SSI_INT_UI (1 << 2)
1312 # define SSI_INT_DI (1 << 1)
1313 #define SSI0_INT_ENABLE 0xB1600008
1314 # define SSI_INTE_OIE (1 << 3)
1315 # define SSI_INTE_UIE (1 << 2)
1316 # define SSI_INTE_DIE (1 << 1)
1317 #define SSI0_CONFIG 0xB1600020
1318 # define SSI_CONFIG_AO (1 << 24)
1319 # define SSI_CONFIG_DO (1 << 23)
1320 # define SSI_CONFIG_ALEN_BIT 20
1321 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1322 # define SSI_CONFIG_DLEN_BIT 16
1323 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1324 # define SSI_CONFIG_DD (1 << 11)
1325 # define SSI_CONFIG_AD (1 << 10)
1326 # define SSI_CONFIG_BM_BIT 8
1327 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1328 # define SSI_CONFIG_CE (1 << 7)
1329 # define SSI_CONFIG_DP (1 << 6)
1330 # define SSI_CONFIG_DL (1 << 5)
1331 # define SSI_CONFIG_EP (1 << 4)
1332 #define SSI0_ADATA 0xB1600024
1333 # define SSI_AD_D (1 << 24)
1334 # define SSI_AD_ADDR_BIT 16
1335 # define SSI_AD_ADDR_MASK (0xff << 16)
1336 # define SSI_AD_DATA_BIT 0
1337 # define SSI_AD_DATA_MASK (0xfff << 0)
1338 #define SSI0_CLKDIV 0xB1600028
1339 #define SSI0_CONTROL 0xB1600100
1340 # define SSI_CONTROL_CD (1 << 1)
1341 # define SSI_CONTROL_E (1 << 0)
1342
1343 /* SSI1 */
1344 #define SSI1_STATUS 0xB1680000
1345 #define SSI1_INT 0xB1680004
1346 #define SSI1_INT_ENABLE 0xB1680008
1347 #define SSI1_CONFIG 0xB1680020
1348 #define SSI1_ADATA 0xB1680024
1349 #define SSI1_CLKDIV 0xB1680028
1350 #define SSI1_ENABLE 0xB1680100
1351
1352 /*
1353 * Register content definitions
1354 */
1355 #define SSI_STATUS_BF (1 << 4)
1356 #define SSI_STATUS_OF (1 << 3)
1357 #define SSI_STATUS_UF (1 << 2)
1358 #define SSI_STATUS_D (1 << 1)
1359 #define SSI_STATUS_B (1 << 0)
1360
1361 /* SSI_INT */
1362 #define SSI_INT_OI (1 << 3)
1363 #define SSI_INT_UI (1 << 2)
1364 #define SSI_INT_DI (1 << 1)
1365
1366 /* SSI_INTEN */
1367 #define SSI_INTEN_OIE (1 << 3)
1368 #define SSI_INTEN_UIE (1 << 2)
1369 #define SSI_INTEN_DIE (1 << 1)
1370
1371 #define SSI_CONFIG_AO (1 << 24)
1372 #define SSI_CONFIG_DO (1 << 23)
1373 #define SSI_CONFIG_ALEN (7 << 20)
1374 #define SSI_CONFIG_DLEN (15 << 16)
1375 #define SSI_CONFIG_DD (1 << 11)
1376 #define SSI_CONFIG_AD (1 << 10)
1377 #define SSI_CONFIG_BM (3 << 8)
1378 #define SSI_CONFIG_CE (1 << 7)
1379 #define SSI_CONFIG_DP (1 << 6)
1380 #define SSI_CONFIG_DL (1 << 5)
1381 #define SSI_CONFIG_EP (1 << 4)
1382 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1383 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1384 #define SSI_CONFIG_BM_HI (0 << 8)
1385 #define SSI_CONFIG_BM_LO (1 << 8)
1386 #define SSI_CONFIG_BM_CY (2 << 8)
1387
1388 #define SSI_ADATA_D (1 << 24)
1389 #define SSI_ADATA_ADDR (0xFF << 16)
1390 #define SSI_ADATA_DATA 0x0FFF
1391 #define SSI_ADATA_ADDR_N(N) (N << 16)
1392
1393 #define SSI_ENABLE_CD (1 << 1)
1394 #define SSI_ENABLE_E (1 << 0)
1395
1396 /* IrDA Controller */
1397 #define IRDA_BASE 0xB0300000
1398 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1399 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1400 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1401 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1402 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1403 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1404 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1405 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1406 # define IR_RX_INVERT_LED (1 << 0)
1407 # define IR_TX_INVERT_LED (1 << 1)
1408 # define IR_ST (1 << 2)
1409 # define IR_SF (1 << 3)
1410 # define IR_SIR (1 << 4)
1411 # define IR_MIR (1 << 5)
1412 # define IR_FIR (1 << 6)
1413 # define IR_16CRC (1 << 7)
1414 # define IR_TD (1 << 8)
1415 # define IR_RX_ALL (1 << 9)
1416 # define IR_DMA_ENABLE (1 << 10)
1417 # define IR_RX_ENABLE (1 << 11)
1418 # define IR_TX_ENABLE (1 << 12)
1419 # define IR_LOOPBACK (1 << 14)
1420 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1421 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1422 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1423 #define IR_ENABLE (IRDA_BASE + 0x28)
1424 # define IR_RX_STATUS (1 << 9)
1425 # define IR_TX_STATUS (1 << 10)
1426 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1427 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1428 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1429 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1430 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1431 # define IR_MODE_INV (1 << 0)
1432 # define IR_ONE_PIN (1 << 1)
1433 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1434
1435 /* GPIO */
1436 #define SYS_PINFUNC 0xB190002C
1437 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1438 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1439 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1440 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1441 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1442 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1443 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1444 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1445 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1446 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1447 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1448 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1449 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1450 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1451 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1452 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1453
1454 /* Au1100 only */
1455 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1456 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1457 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1458 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1459
1460 /* Au1550 only. Redefines lots of pins */
1461 # define SYS_PF_PSC2_MASK (7 << 17)
1462 # define SYS_PF_PSC2_AC97 0
1463 # define SYS_PF_PSC2_SPI 0
1464 # define SYS_PF_PSC2_I2S (1 << 17)
1465 # define SYS_PF_PSC2_SMBUS (3 << 17)
1466 # define SYS_PF_PSC2_GPIO (7 << 17)
1467 # define SYS_PF_PSC3_MASK (7 << 20)
1468 # define SYS_PF_PSC3_AC97 0
1469 # define SYS_PF_PSC3_SPI 0
1470 # define SYS_PF_PSC3_I2S (1 << 20)
1471 # define SYS_PF_PSC3_SMBUS (3 << 20)
1472 # define SYS_PF_PSC3_GPIO (7 << 20)
1473 # define SYS_PF_PSC1_S1 (1 << 1)
1474 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1475
1476 /* Au1200 only */
1477 #ifdef CONFIG_SOC_AU1200
1478 #define SYS_PINFUNC_DMA (1 << 31)
1479 #define SYS_PINFUNC_S0A (1 << 30)
1480 #define SYS_PINFUNC_S1A (1 << 29)
1481 #define SYS_PINFUNC_LP0 (1 << 28)
1482 #define SYS_PINFUNC_LP1 (1 << 27)
1483 #define SYS_PINFUNC_LD16 (1 << 26)
1484 #define SYS_PINFUNC_LD8 (1 << 25)
1485 #define SYS_PINFUNC_LD1 (1 << 24)
1486 #define SYS_PINFUNC_LD0 (1 << 23)
1487 #define SYS_PINFUNC_P1A (3 << 21)
1488 #define SYS_PINFUNC_P1B (1 << 20)
1489 #define SYS_PINFUNC_FS3 (1 << 19)
1490 #define SYS_PINFUNC_P0A (3 << 17)
1491 #define SYS_PINFUNC_CS (1 << 16)
1492 #define SYS_PINFUNC_CIM (1 << 15)
1493 #define SYS_PINFUNC_P1C (1 << 14)
1494 #define SYS_PINFUNC_U1T (1 << 12)
1495 #define SYS_PINFUNC_U1R (1 << 11)
1496 #define SYS_PINFUNC_EX1 (1 << 10)
1497 #define SYS_PINFUNC_EX0 (1 << 9)
1498 #define SYS_PINFUNC_U0R (1 << 8)
1499 #define SYS_PINFUNC_MC (1 << 7)
1500 #define SYS_PINFUNC_S0B (1 << 6)
1501 #define SYS_PINFUNC_S0C (1 << 5)
1502 #define SYS_PINFUNC_P0B (1 << 4)
1503 #define SYS_PINFUNC_U0T (1 << 3)
1504 #define SYS_PINFUNC_S1B (1 << 2)
1505 #endif
1506
1507 #define SYS_TRIOUTRD 0xB1900100
1508 #define SYS_TRIOUTCLR 0xB1900100
1509 #define SYS_OUTPUTRD 0xB1900108
1510 #define SYS_OUTPUTSET 0xB1900108
1511 #define SYS_OUTPUTCLR 0xB190010C
1512 #define SYS_PINSTATERD 0xB1900110
1513 #define SYS_PININPUTEN 0xB1900110
1514
1515 /* GPIO2, Au1500, Au1550 only */
1516 #define GPIO2_BASE 0xB1700000
1517 #define GPIO2_DIR (GPIO2_BASE + 0)
1518 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1519 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1520 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1521 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1522
1523 /* Power Management */
1524 #define SYS_SCRATCH0 0xB1900018
1525 #define SYS_SCRATCH1 0xB190001C
1526 #define SYS_WAKEMSK 0xB1900034
1527 #define SYS_ENDIAN 0xB1900038
1528 #define SYS_POWERCTRL 0xB190003C
1529 #define SYS_WAKESRC 0xB190005C
1530 #define SYS_SLPPWR 0xB1900078
1531 #define SYS_SLEEP 0xB190007C
1532
1533 #define SYS_WAKEMSK_D2 (1 << 9)
1534 #define SYS_WAKEMSK_M2 (1 << 8)
1535 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1536
1537 /* Clock Controller */
1538 #define SYS_FREQCTRL0 0xB1900020
1539 # define SYS_FC_FRDIV2_BIT 22
1540 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1541 # define SYS_FC_FE2 (1 << 21)
1542 # define SYS_FC_FS2 (1 << 20)
1543 # define SYS_FC_FRDIV1_BIT 12
1544 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1545 # define SYS_FC_FE1 (1 << 11)
1546 # define SYS_FC_FS1 (1 << 10)
1547 # define SYS_FC_FRDIV0_BIT 2
1548 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1549 # define SYS_FC_FE0 (1 << 1)
1550 # define SYS_FC_FS0 (1 << 0)
1551 #define SYS_FREQCTRL1 0xB1900024
1552 # define SYS_FC_FRDIV5_BIT 22
1553 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1554 # define SYS_FC_FE5 (1 << 21)
1555 # define SYS_FC_FS5 (1 << 20)
1556 # define SYS_FC_FRDIV4_BIT 12
1557 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1558 # define SYS_FC_FE4 (1 << 11)
1559 # define SYS_FC_FS4 (1 << 10)
1560 # define SYS_FC_FRDIV3_BIT 2
1561 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1562 # define SYS_FC_FE3 (1 << 1)
1563 # define SYS_FC_FS3 (1 << 0)
1564 #define SYS_CLKSRC 0xB1900028
1565 # define SYS_CS_ME1_BIT 27
1566 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1567 # define SYS_CS_DE1 (1 << 26)
1568 # define SYS_CS_CE1 (1 << 25)
1569 # define SYS_CS_ME0_BIT 22
1570 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1571 # define SYS_CS_DE0 (1 << 21)
1572 # define SYS_CS_CE0 (1 << 20)
1573 # define SYS_CS_MI2_BIT 17
1574 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1575 # define SYS_CS_DI2 (1 << 16)
1576 # define SYS_CS_CI2 (1 << 15)
1577 #ifdef CONFIG_SOC_AU1100
1578 # define SYS_CS_ML_BIT 7
1579 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1580 # define SYS_CS_DL (1 << 6)
1581 # define SYS_CS_CL (1 << 5)
1582 #else
1583 # define SYS_CS_MUH_BIT 12
1584 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1585 # define SYS_CS_DUH (1 << 11)
1586 # define SYS_CS_CUH (1 << 10)
1587 # define SYS_CS_MUD_BIT 7
1588 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1589 # define SYS_CS_DUD (1 << 6)
1590 # define SYS_CS_CUD (1 << 5)
1591 #endif
1592 # define SYS_CS_MIR_BIT 2
1593 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1594 # define SYS_CS_DIR (1 << 1)
1595 # define SYS_CS_CIR (1 << 0)
1596
1597 # define SYS_CS_MUX_AUX 0x1
1598 # define SYS_CS_MUX_FQ0 0x2
1599 # define SYS_CS_MUX_FQ1 0x3
1600 # define SYS_CS_MUX_FQ2 0x4
1601 # define SYS_CS_MUX_FQ3 0x5
1602 # define SYS_CS_MUX_FQ4 0x6
1603 # define SYS_CS_MUX_FQ5 0x7
1604 #define SYS_CPUPLL 0xB1900060
1605 #define SYS_AUXPLL 0xB1900064
1606
1607 /* AC97 Controller */
1608 #define AC97C_CONFIG 0xB0000000
1609 # define AC97C_RECV_SLOTS_BIT 13
1610 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1611 # define AC97C_XMIT_SLOTS_BIT 3
1612 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1613 # define AC97C_SG (1 << 2)
1614 # define AC97C_SYNC (1 << 1)
1615 # define AC97C_RESET (1 << 0)
1616 #define AC97C_STATUS 0xB0000004
1617 # define AC97C_XU (1 << 11)
1618 # define AC97C_XO (1 << 10)
1619 # define AC97C_RU (1 << 9)
1620 # define AC97C_RO (1 << 8)
1621 # define AC97C_READY (1 << 7)
1622 # define AC97C_CP (1 << 6)
1623 # define AC97C_TR (1 << 5)
1624 # define AC97C_TE (1 << 4)
1625 # define AC97C_TF (1 << 3)
1626 # define AC97C_RR (1 << 2)
1627 # define AC97C_RE (1 << 1)
1628 # define AC97C_RF (1 << 0)
1629 #define AC97C_DATA 0xB0000008
1630 #define AC97C_CMD 0xB000000C
1631 # define AC97C_WD_BIT 16
1632 # define AC97C_READ (1 << 7)
1633 # define AC97C_INDEX_MASK 0x7f
1634 #define AC97C_CNTRL 0xB0000010
1635 # define AC97C_RS (1 << 1)
1636 # define AC97C_CE (1 << 0)
1637
1638 /* Secure Digital (SD) Controller */
1639 #define SD0_XMIT_FIFO 0xB0600000
1640 #define SD0_RECV_FIFO 0xB0600004
1641 #define SD1_XMIT_FIFO 0xB0680000
1642 #define SD1_RECV_FIFO 0xB0680004
1643
1644 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1645 /* Au1500 PCI Controller */
1646 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1647 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1648 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1649 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1650 (1 << 25) | (1 << 26) | (1 << 27))
1651 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1652 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1653 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1654 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1655 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1656 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1657 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1658 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1659 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1660 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1661 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1662 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1663
1664 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1665
1666 /*
1667 * All of our structures, like PCI resource, have 32-bit members.
1668 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1669 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1670 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1671 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1672 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1673 * ourselves and then adjust the device's resources.
1674 */
1675 #define Au1500_EXT_CFG 0x600000000ULL
1676 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1677 #define Au1500_PCI_IO_START 0x500000000ULL
1678 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1679 #define Au1500_PCI_MEM_START 0x440000000ULL
1680 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1681
1682 #define PCI_IO_START 0x00001000
1683 #define PCI_IO_END 0x000FFFFF
1684 #define PCI_MEM_START 0x40000000
1685 #define PCI_MEM_END 0x4FFFFFFF
1686
1687 #define PCI_FIRST_DEVFN (0 << 3)
1688 #define PCI_LAST_DEVFN (19 << 3)
1689
1690 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1691 #define IOPORT_RESOURCE_END 0xffffffff
1692 #define IOMEM_RESOURCE_START 0x10000000
1693 #define IOMEM_RESOURCE_END 0xfffffffffULL
1694
1695 #else /* Au1000 and Au1100 and Au1200 */
1696
1697 /* Don't allow any legacy ports probing */
1698 #define IOPORT_RESOURCE_START 0x10000000
1699 #define IOPORT_RESOURCE_END 0xffffffff
1700 #define IOMEM_RESOURCE_START 0x10000000
1701 #define IOMEM_RESOURCE_END 0xfffffffffULL
1702
1703 #define PCI_IO_START 0
1704 #define PCI_IO_END 0
1705 #define PCI_MEM_START 0
1706 #define PCI_MEM_END 0
1707 #define PCI_FIRST_DEVFN 0
1708 #define PCI_LAST_DEVFN 0
1709
1710 #endif
1711
1712 #endif
Tomato firmware and modifications.