release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/div64.h

   1 /*
   2  * Copyright (C) 2000, 2004  Maciej W. Rozycki
   3  * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  */
   9 #ifndef __ASM_DIV64_H
  10 #define __ASM_DIV64_H
  11
  12 #include <asm-generic/div64.h>
  13
  14 #if BITS_PER_LONG == 64
  15
  16 #include <linux/types.h>
  17
  18 /*
  19  * No traps on overflows for any of these...
  20  */
  21
  22 #define __div64_32(n, base)                                             \
  23 ({                                                                      \
  24         unsigned long __cf, __tmp, __tmp2, __i;                         \
  25         unsigned long __quot32, __mod32;                                \
  26         unsigned long __high, __low;                                    \
  27         unsigned long long __n;                                         \
  28                                                                         \
  29         __high = *__n >> 32;                                            \
  30         __low = __n;                                                    \
  31         __asm__(                                                        \
  32         "       .set    push                                    \n"     \
  33         "       .set    noat                                    \n"     \
  34         "       .set    noreorder                               \n"     \
  35         "       move    %2, $0                                  \n"     \
  36         "       move    %3, $0                                  \n"     \
  37         "       b       1f                                      \n"     \
  38         "        li     %4, 0x21                                \n"     \
  39         "0:                                                     \n"     \
  40         "       sll     $1, %0, 0x1                             \n"     \
  41         "       srl     %3, %0, 0x1f                            \n"     \
  42         "       or      %0, $1, %5                              \n"     \
  43         "       sll     %1, %1, 0x1                             \n"     \
  44         "       sll     %2, %2, 0x1                             \n"     \
  45         "1:                                                     \n"     \
  46         "       bnez    %3, 2f                                  \n"     \
  47         "        sltu   %5, %0, %z6                             \n"     \
  48         "       bnez    %5, 3f                                  \n"     \
  49         "2:                                                     \n"     \
  50         "        addiu  %4, %4, -1                              \n"     \
  51         "       subu    %0, %0, %z6                             \n"     \
  52         "       addiu   %2, %2, 1                               \n"     \
  53         "3:                                                     \n"     \
  54         "       bnez    %4, 0b\n\t"                                     \
  55         "        srl    %5, %1, 0x1f\n\t"                               \
  56         "       .set    pop"                                            \
  57         : "=&r" (__mod32), "=&r" (__tmp),                               \
  58           "=&r" (__quot32), "=&r" (__cf),                               \
  59           "=&r" (__i), "=&r" (__tmp2)                                   \
  60         : "Jr" (base), "0" (__high), "1" (__low));                      \
  61                                                                         \
  62         (__n) = __quot32;                                               \
  63         __mod32;                                                        \
  64 })
  65
  66 #endif /* BITS_PER_LONG == 64 */
  67
  68 #endif /* __ASM_DIV64_H */