release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/dec/kn02-irq.c

   1 /*
   2  *      DECstation 5000/200 (KN02) Control and Status Register
   3  *      interrupts.
   4  *
   5  *      Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
   6  *
   7  *      This program is free software; you can redistribute it and/or
   8  *      modify it under the terms of the GNU General Public License
   9  *      as published by the Free Software Foundation; either version
  10  *      2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/types.h>
  16
  17 #include <asm/dec/kn02.h>
  18
  19
  20 /*
  21  * Bits 7:0 of the Control Register are write-only -- the
  22  * corresponding bits of the Status Register have a different
  23  * meaning.  Hence we use a cache.  It speeds up things a bit
  24  * as well.
  25  *
  26  * There is no default value -- it has to be initialized.
  27  */
  28 u32 cached_kn02_csr;
  29
  30
  31 static int kn02_irq_base;
  32
  33
  34 static inline void unmask_kn02_irq(unsigned int irq)
  35 {
  36         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  37                                                        KN02_CSR);
  38
  39         cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
  40         *csr = cached_kn02_csr;
  41 }
  42
  43 static inline void mask_kn02_irq(unsigned int irq)
  44 {
  45         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  46                                                        KN02_CSR);
  47
  48         cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
  49         *csr = cached_kn02_csr;
  50 }
  51
  52 static void ack_kn02_irq(unsigned int irq)
  53 {
  54         mask_kn02_irq(irq);
  55         iob();
  56 }
  57
  58 static struct irq_chip kn02_irq_type = {
  59         .name = "KN02-CSR",
  60         .ack = ack_kn02_irq,
  61         .mask = mask_kn02_irq,
  62         .mask_ack = ack_kn02_irq,
  63         .unmask = unmask_kn02_irq,
  64 };
  65
  66
  67 void __init init_kn02_irqs(int base)
  68 {
  69         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  70                                                        KN02_CSR);
  71         int i;
  72
  73         /* Mask interrupts. */
  74         cached_kn02_csr &= ~KN02_CSR_IOINTEN;
  75         *csr = cached_kn02_csr;
  76         iob();
  77
  78         for (i = base; i < base + KN02_IRQ_LINES; i++)
  79                 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
  80
  81         kn02_irq_base = base;
  82 }