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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / m32r / include / asm / system.h
blob06115a5b320089b5dea230b2d064b30a783eb246
1 #ifndef _ASM_M32R_SYSTEM_H
2 #define _ASM_M32R_SYSTEM_H
3
4 /*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
10 * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
11 */
12
13 #include <linux/compiler.h>
14 #include <asm/assembler.h>
15
16 #ifdef __KERNEL__
17
18 /*
19 * switch_to(prev, next) should switch from task `prev' to `next'
20 * `prev' will never be the same as `next'.
21 *
22 * `next' and `prev' should be struct task_struct, but it isn't always defined
23 */
24
25 #if defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
26 #define M32R_PUSH_FP " push fp\n"
27 #define M32R_POP_FP " pop fp\n"
28 #else
29 #define M32R_PUSH_FP ""
30 #define M32R_POP_FP ""
31 #endif
32
33 #define switch_to(prev, next, last) do { \
34 __asm__ __volatile__ ( \
35 " seth lr, #high(1f) \n" \
36 " or3 lr, lr, #low(1f) \n" \
37 " st lr, @%4 ; store old LR \n" \
38 " ld lr, @%5 ; load new LR \n" \
39 M32R_PUSH_FP \
40 " st sp, @%2 ; store old SP \n" \
41 " ld sp, @%3 ; load new SP \n" \
42 " push %1 ; store `prev' on new stack \n" \
43 " jmp lr \n" \
44 " .fillinsn \n" \
45 "1: \n" \
46 " pop %0 ; restore `__last' from new stack \n" \
47 M32R_POP_FP \
48 : "=r" (last) \
49 : "0" (prev), \
50 "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
51 "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
52 : "memory", "lr" \
53 ); \
54 } while(0)
55
56 /* Interrupt Control */
57 #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
58 #define local_irq_enable() \
59 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
60 #define local_irq_disable() \
61 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
62 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
63 static inline void local_irq_enable(void)
64 {
65 unsigned long tmpreg;
66 __asm__ __volatile__(
67 "mvfc %0, psw; \n\t"
68 "or3 %0, %0, #0x0040; \n\t"
69 "mvtc %0, psw; \n\t"
70 : "=&r" (tmpreg) : : "cbit", "memory");
71 }
72
73 static inline void local_irq_disable(void)
74 {
75 unsigned long tmpreg0, tmpreg1;
76 __asm__ __volatile__(
77 "ld24 %0, #0 ; Use 32-bit insn. \n\t"
78 "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
79 "mvtc %0, psw \n\t"
80 "and3 %0, %1, #0xffbf \n\t"
81 "mvtc %0, psw \n\t"
82 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
83 }
84 #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
85
86 #define local_save_flags(x) \
87 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
88
89 #define local_irq_restore(x) \
90 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
91 : "r" (x) : "cbit", "memory")
92
93 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
94 #define local_irq_save(x) \
95 __asm__ __volatile__( \
96 "mvfc %0, psw; \n\t" \
97 "clrpsw #0x40 -> nop; \n\t" \
98 : "=r" (x) : /* no input */ : "memory")
99 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
100 #define local_irq_save(x) \
101 ({ \
102 unsigned long tmpreg; \
103 __asm__ __volatile__( \
104 "ld24 %1, #0 \n\t" \
105 "mvfc %0, psw \n\t" \
106 "mvtc %1, psw \n\t" \
107 "and3 %1, %0, #0xffbf \n\t" \
108 "mvtc %1, psw \n\t" \
109 : "=r" (x), "=&r" (tmpreg) \
110 : : "cbit", "memory"); \
111 })
112 #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
113
114 #define irqs_disabled() \
115 ({ \
116 unsigned long flags; \
117 local_save_flags(flags); \
118 !(flags & 0x40); \
119 })
120
121 #define nop() __asm__ __volatile__ ("nop" : : )
122
123 #define xchg(ptr, x) \
124 ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
125 #define xchg_local(ptr, x) \
126 ((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
127 sizeof(*(ptr))))
128
129 extern void __xchg_called_with_bad_pointer(void);
130
131 #ifdef CONFIG_CHIP_M32700_TS1
132 #define DCACHE_CLEAR(reg0, reg1, addr) \
133 "seth "reg1", #high(dcache_dummy); \n\t" \
134 "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
135 "lock "reg0", @"reg1"; \n\t" \
136 "add3 "reg0", "addr", #0x1000; \n\t" \
137 "ld "reg0", @"reg0"; \n\t" \
138 "add3 "reg0", "addr", #0x2000; \n\t" \
139 "ld "reg0", @"reg0"; \n\t" \
140 "unlock "reg0", @"reg1"; \n\t"
141 #else /* CONFIG_CHIP_M32700_TS1 */
142 #define DCACHE_CLEAR(reg0, reg1, addr)
143 #endif /* CONFIG_CHIP_M32700_TS1 */
144
145 static __always_inline unsigned long
146 __xchg(unsigned long x, volatile void *ptr, int size)
147 {
148 unsigned long flags;
149 unsigned long tmp = 0;
150
151 local_irq_save(flags);
152
153 switch (size) {
154 #ifndef CONFIG_SMP
155 case 1:
156 __asm__ __volatile__ (
157 "ldb %0, @%2 \n\t"
158 "stb %1, @%2 \n\t"
159 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
160 break;
161 case 2:
162 __asm__ __volatile__ (
163 "ldh %0, @%2 \n\t"
164 "sth %1, @%2 \n\t"
165 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
166 break;
167 case 4:
168 __asm__ __volatile__ (
169 "ld %0, @%2 \n\t"
170 "st %1, @%2 \n\t"
171 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
172 break;
173 #else /* CONFIG_SMP */
174 case 4:
175 __asm__ __volatile__ (
176 DCACHE_CLEAR("%0", "r4", "%2")
177 "lock %0, @%2; \n\t"
178 "unlock %1, @%2; \n\t"
179 : "=&r" (tmp) : "r" (x), "r" (ptr)
180 : "memory"
181 #ifdef CONFIG_CHIP_M32700_TS1
182 , "r4"
183 #endif /* CONFIG_CHIP_M32700_TS1 */
184 );
185 break;
186 #endif /* CONFIG_SMP */
187 default:
188 __xchg_called_with_bad_pointer();
189 }
190
191 local_irq_restore(flags);
192
193 return (tmp);
194 }
195
196 static __always_inline unsigned long
197 __xchg_local(unsigned long x, volatile void *ptr, int size)
198 {
199 unsigned long flags;
200 unsigned long tmp = 0;
201
202 local_irq_save(flags);
203
204 switch (size) {
205 case 1:
206 __asm__ __volatile__ (
207 "ldb %0, @%2 \n\t"
208 "stb %1, @%2 \n\t"
209 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
210 break;
211 case 2:
212 __asm__ __volatile__ (
213 "ldh %0, @%2 \n\t"
214 "sth %1, @%2 \n\t"
215 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
216 break;
217 case 4:
218 __asm__ __volatile__ (
219 "ld %0, @%2 \n\t"
220 "st %1, @%2 \n\t"
221 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
222 break;
223 default:
224 __xchg_called_with_bad_pointer();
225 }
226
227 local_irq_restore(flags);
228
229 return (tmp);
230 }
231
232 #define __HAVE_ARCH_CMPXCHG 1
233
234 static inline unsigned long
235 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
236 {
237 unsigned long flags;
238 unsigned int retval;
239
240 local_irq_save(flags);
241 __asm__ __volatile__ (
242 DCACHE_CLEAR("%0", "r4", "%1")
243 M32R_LOCK" %0, @%1; \n"
244 " bne %0, %2, 1f; \n"
245 M32R_UNLOCK" %3, @%1; \n"
246 " bra 2f; \n"
247 " .fillinsn \n"
248 "1:"
249 M32R_UNLOCK" %0, @%1; \n"
250 " .fillinsn \n"
251 "2:"
252 : "=&r" (retval)
253 : "r" (p), "r" (old), "r" (new)
254 : "cbit", "memory"
255 #ifdef CONFIG_CHIP_M32700_TS1
256 , "r4"
257 #endif /* CONFIG_CHIP_M32700_TS1 */
258 );
259 local_irq_restore(flags);
260
261 return retval;
262 }
263
264 static inline unsigned long
265 __cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
266 unsigned int new)
267 {
268 unsigned long flags;
269 unsigned int retval;
270
271 local_irq_save(flags);
272 __asm__ __volatile__ (
273 DCACHE_CLEAR("%0", "r4", "%1")
274 "ld %0, @%1; \n"
275 " bne %0, %2, 1f; \n"
276 "st %3, @%1; \n"
277 " bra 2f; \n"
278 " .fillinsn \n"
279 "1:"
280 "st %0, @%1; \n"
281 " .fillinsn \n"
282 "2:"
283 : "=&r" (retval)
284 : "r" (p), "r" (old), "r" (new)
285 : "cbit", "memory"
286 #ifdef CONFIG_CHIP_M32700_TS1
287 , "r4"
288 #endif /* CONFIG_CHIP_M32700_TS1 */
289 );
290 local_irq_restore(flags);
291
292 return retval;
293 }
294
295 /* This function doesn't exist, so you'll get a linker error
296 if something tries to do an invalid cmpxchg(). */
297 extern void __cmpxchg_called_with_bad_pointer(void);
298
299 static inline unsigned long
300 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
301 {
302 switch (size) {
303 case 4:
304 return __cmpxchg_u32(ptr, old, new);
305 }
306 __cmpxchg_called_with_bad_pointer();
307 return old;
308 }
309
310 #define cmpxchg(ptr, o, n) \
311 ((__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)(o), \
312 (unsigned long)(n), sizeof(*(ptr))))
313
314 #include <asm-generic/cmpxchg-local.h>
315
316 static inline unsigned long __cmpxchg_local(volatile void *ptr,
317 unsigned long old,
318 unsigned long new, int size)
319 {
320 switch (size) {
321 case 4:
322 return __cmpxchg_local_u32(ptr, old, new);
323 default:
324 return __cmpxchg_local_generic(ptr, old, new, size);
325 }
326
327 return old;
328 }
329
330 /*
331 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
332 * them available.
333 */
334 #define cmpxchg_local(ptr, o, n) \
335 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
336 (unsigned long)(n), sizeof(*(ptr))))
337 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
338
339 #endif /* __KERNEL__ */
340
341 /*
342 * Memory barrier.
343 *
344 * mb() prevents loads and stores being reordered across this point.
345 * rmb() prevents loads being reordered across this point.
346 * wmb() prevents stores being reordered across this point.
347 */
348 #define mb() barrier()
349 #define rmb() mb()
350 #define wmb() mb()
351
352 /**
353 * read_barrier_depends - Flush all pending reads that subsequents reads
354 * depend on.
355 *
356 * No data-dependent reads from memory-like regions are ever reordered
357 * over this barrier. All reads preceding this primitive are guaranteed
358 * to access memory (but not necessarily other CPUs' caches) before any
359 * reads following this primitive that depend on the data return by
360 * any of the preceding reads. This primitive is much lighter weight than
361 * rmb() on most CPUs, and is never heavier weight than is
362 * rmb().
363 *
364 * These ordering constraints are respected by both the local CPU
365 * and the compiler.
366 *
367 * Ordering is not guaranteed by anything other than these primitives,
368 * not even by data dependencies. See the documentation for
369 * memory_barrier() for examples and URLs to more information.
370 *
371 * For example, the following code would force ordering (the initial
372 * value of "a" is zero, "b" is one, and "p" is "&a"):
373 *
374 * <programlisting>
375 * CPU 0 CPU 1
376 *
377 * b = 2;
378 * memory_barrier();
379 * p = &b; q = p;
380 * read_barrier_depends();
381 * d = *q;
382 * </programlisting>
383 *
384 *
385 * because the read of "*q" depends on the read of "p" and these
386 * two reads are separated by a read_barrier_depends(). However,
387 * the following code, with the same initial values for "a" and "b":
388 *
389 * <programlisting>
390 * CPU 0 CPU 1
391 *
392 * a = 2;
393 * memory_barrier();
394 * b = 3; y = b;
395 * read_barrier_depends();
396 * x = a;
397 * </programlisting>
398 *
399 * does not enforce ordering, since there is no data dependency between
400 * the read of "a" and the read of "b". Therefore, on some CPUs, such
401 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
402 * in cases like this where there are no data dependencies.
403 **/
404
405 #define read_barrier_depends() do { } while (0)
406
407 #ifdef CONFIG_SMP
408 #define smp_mb() mb()
409 #define smp_rmb() rmb()
410 #define smp_wmb() wmb()
411 #define smp_read_barrier_depends() read_barrier_depends()
412 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
413 #else
414 #define smp_mb() barrier()
415 #define smp_rmb() barrier()
416 #define smp_wmb() barrier()
417 #define smp_read_barrier_depends() do { } while (0)
418 #define set_mb(var, value) do { var = value; barrier(); } while (0)
419 #endif
420
421 #define arch_align_stack(x) (x)
422
423 #endif /* _ASM_M32R_SYSTEM_H */
Tomato firmware and modifications.