release/src-rt-6.x.4708/linux/linux-2.6.36/arch/ia64/include/asm/sn/pic.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PCI_PIC_H
   9 #define _ASM_IA64_SN_PCI_PIC_H
  10
  11 /*
  12  * PIC AS DEVICE ZERO
  13  * ------------------
  14  *
  15  * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
  16  * be designated as 'device 0'.   That is a departure from earlier SGI
  17  * PCI bridges.  Because of that we use config space 1 to access the
  18  * config space of the first actual PCI device on the bus.
  19  * Here's what the PIC manual says:
  20  *
  21  *     The current PCI-X bus specification now defines that the parent
  22  *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
  23  *     reduced the total number of devices from 8 to 4 and removed the
  24  *     device registers and windows, now only supporting devices 0,1,2, and
  25  *     3. PIC did leave all 8 configuration space windows. The reason was
  26  *     there was nothing to gain by removing them. Here in lies the problem.
  27  *     The device numbering we do using 0 through 3 is unrelated to the device
  28  *     numbering which PCI-X requires in configuration space. In the past we
  29  *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
  30  *     PCI-X requires we start a 1, not 0 and currently the PX brick
  31  *     does associate our:
  32  *
  33  *         device 0 with configuration space window 1,
  34  *         device 1 with configuration space window 2,
  35  *         device 2 with configuration space window 3,
  36  *         device 3 with configuration space window 4.
  37  *
  38  * The net effect is that all config space access are off-by-one with
  39  * relation to other per-slot accesses on the PIC.
  40  * Here is a table that shows some of that:
  41  *
  42  *                               Internal Slot#
  43  *           |
  44  *           |     0         1        2         3
  45  * ----------|---------------------------------------
  46  * config    |  0x21000   0x22000  0x23000   0x24000
  47  *           |
  48  * even rrb  |  0[0]      n/a      1[0]      n/a        [] == implied even/odd
  49  *           |
  50  * odd rrb   |  n/a       0[1]     n/a       1[1]
  51  *           |
  52  * int dev   |  00       01        10        11
  53  *           |
  54  * ext slot# |  1        2         3         4
  55  * ----------|---------------------------------------
  56  */
  57
  58 #define PIC_ATE_TARGETID_SHFT           8
  59 #define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFFUL
  60 #define PIC_PCI64_ATTR_TARG_SHFT        60
  61
  62
  63 /*****************************************************************************
  64  *********************** PIC MMR structure mapping ***************************
  65  *****************************************************************************/
  66
  67 /* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
  68  * of a 64-bit register.  When writing PIC registers, always write the
  69  * entire 64 bits.
  70  */
  71
  72 struct pic {
  73
  74     /* 0x000000-0x00FFFF -- Local Registers */
  75
  76     /* 0x000000-0x000057 -- Standard Widget Configuration */
  77     u64         p_wid_id;                       /* 0x000000 */
  78     u64         p_wid_stat;                     /* 0x000008 */
  79     u64         p_wid_err_upper;                /* 0x000010 */
  80     u64         p_wid_err_lower;                /* 0x000018 */
  81     #define p_wid_err p_wid_err_lower
  82     u64         p_wid_control;                  /* 0x000020 */
  83     u64         p_wid_req_timeout;              /* 0x000028 */
  84     u64         p_wid_int_upper;                /* 0x000030 */
  85     u64         p_wid_int_lower;                /* 0x000038 */
  86     #define p_wid_int p_wid_int_lower
  87     u64         p_wid_err_cmdword;              /* 0x000040 */
  88     u64         p_wid_llp;                      /* 0x000048 */
  89     u64         p_wid_tflush;                   /* 0x000050 */
  90
  91     /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
  92     u64         p_wid_aux_err;                  /* 0x000058 */
  93     u64         p_wid_resp_upper;               /* 0x000060 */
  94     u64         p_wid_resp_lower;               /* 0x000068 */
  95     #define p_wid_resp p_wid_resp_lower
  96     u64         p_wid_tst_pin_ctrl;             /* 0x000070 */
  97     u64         p_wid_addr_lkerr;               /* 0x000078 */
  98
  99     /* 0x000080-0x00008F -- PMU & MAP */
 100     u64         p_dir_map;                      /* 0x000080 */
 101     u64         _pad_000088;                    /* 0x000088 */
 102
 103     /* 0x000090-0x00009F -- SSRAM */
 104     u64         p_map_fault;                    /* 0x000090 */
 105     u64         _pad_000098;                    /* 0x000098 */
 106
 107     /* 0x0000A0-0x0000AF -- Arbitration */
 108     u64         p_arb;                          /* 0x0000A0 */
 109     u64         _pad_0000A8;                    /* 0x0000A8 */
 110
 111     /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
 112     u64         p_ate_parity_err;               /* 0x0000B0 */
 113     u64         _pad_0000B8;                    /* 0x0000B8 */
 114
 115     /* 0x0000C0-0x0000FF -- PCI/GIO */
 116     u64         p_bus_timeout;                  /* 0x0000C0 */
 117     u64         p_pci_cfg;                      /* 0x0000C8 */
 118     u64         p_pci_err_upper;                /* 0x0000D0 */
 119     u64         p_pci_err_lower;                /* 0x0000D8 */
 120     #define p_pci_err p_pci_err_lower
 121     u64         _pad_0000E0[4];                 /* 0x0000{E0..F8} */
 122
 123     /* 0x000100-0x0001FF -- Interrupt */
 124     u64         p_int_status;                   /* 0x000100 */
 125     u64         p_int_enable;                   /* 0x000108 */
 126     u64         p_int_rst_stat;                 /* 0x000110 */
 127     u64         p_int_mode;                     /* 0x000118 */
 128     u64         p_int_device;                   /* 0x000120 */
 129     u64         p_int_host_err;                 /* 0x000128 */
 130     u64         p_int_addr[8];                  /* 0x0001{30,,,68} */
 131     u64         p_err_int_view;                 /* 0x000170 */
 132     u64         p_mult_int;                     /* 0x000178 */
 133     u64         p_force_always[8];              /* 0x0001{80,,,B8} */
 134     u64         p_force_pin[8];                 /* 0x0001{C0,,,F8} */
 135
 136     /* 0x000200-0x000298 -- Device */
 137     u64         p_device[4];                    /* 0x0002{00,,,18} */
 138     u64         _pad_000220[4];                 /* 0x0002{20,,,38} */
 139     u64         p_wr_req_buf[4];                /* 0x0002{40,,,58} */
 140     u64         _pad_000260[4];                 /* 0x0002{60,,,78} */
 141     u64         p_rrb_map[2];                   /* 0x0002{80,,,88} */
 142     #define p_even_resp p_rrb_map[0]                    /* 0x000280 */
 143     #define p_odd_resp  p_rrb_map[1]                    /* 0x000288 */
 144     u64         p_resp_status;                  /* 0x000290 */
 145     u64         p_resp_clear;                   /* 0x000298 */
 146
 147     u64         _pad_0002A0[12];                /* 0x0002{A0..F8} */
 148
 149     /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
 150     struct {
 151         u64     upper;                          /* 0x0003{00,,,F0} */
 152         u64     lower;                          /* 0x0003{08,,,F8} */
 153     } p_buf_addr_match[16];
 154
 155     /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
 156     struct {
 157         u64     flush_w_touch;                  /* 0x000{400,,,5C0} */
 158         u64     flush_wo_touch;                 /* 0x000{408,,,5C8} */
 159         u64     inflight;                       /* 0x000{410,,,5D0} */
 160         u64     prefetch;                       /* 0x000{418,,,5D8} */
 161         u64     total_pci_retry;                /* 0x000{420,,,5E0} */
 162         u64     max_pci_retry;                  /* 0x000{428,,,5E8} */
 163         u64     max_latency;                    /* 0x000{430,,,5F0} */
 164         u64     clear_all;                      /* 0x000{438,,,5F8} */
 165     } p_buf_count[8];
 166
 167
 168     /* 0x000600-0x0009FF -- PCI/X registers */
 169     u64         p_pcix_bus_err_addr;            /* 0x000600 */
 170     u64         p_pcix_bus_err_attr;            /* 0x000608 */
 171     u64         p_pcix_bus_err_data;            /* 0x000610 */
 172     u64         p_pcix_pio_split_addr;          /* 0x000618 */
 173     u64         p_pcix_pio_split_attr;          /* 0x000620 */
 174     u64         p_pcix_dma_req_err_attr;        /* 0x000628 */
 175     u64         p_pcix_dma_req_err_addr;        /* 0x000630 */
 176     u64         p_pcix_timeout;                 /* 0x000638 */
 177
 178     u64         _pad_000640[120];               /* 0x000{640,,,9F8} */
 179
 180     /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
 181     struct {
 182         u64     p_buf_addr;                     /* 0x000{A00,,,AF0} */
 183         u64     p_buf_attr;                     /* 0X000{A08,,,AF8} */
 184     } p_pcix_read_buf_64[16];
 185
 186     struct {
 187         u64     p_buf_addr;                     /* 0x000{B00,,,BE0} */
 188         u64     p_buf_attr;                     /* 0x000{B08,,,BE8} */
 189         u64     p_buf_valid;                    /* 0x000{B10,,,BF0} */
 190         u64     __pad1;                         /* 0x000{B18,,,BF8} */
 191     } p_pcix_write_buf_64[8];
 192
 193     /* End of Local Registers -- Start of Address Map space */
 194
 195     char                _pad_000c00[0x010000 - 0x000c00];
 196
 197     /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
 198     u64         p_int_ate_ram[1024];            /* 0x010000-0x011fff */
 199
 200     /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
 201     u64         p_int_ate_ram_mp[1024];         /* 0x012000-0x013fff */
 202
 203     char                _pad_014000[0x18000 - 0x014000];
 204
 205     /* 0x18000-0x197F8 -- PIC Write Request Ram */
 206     u64         p_wr_req_lower[256];            /* 0x18000 - 0x187F8 */
 207     u64         p_wr_req_upper[256];            /* 0x18800 - 0x18FF8 */
 208     u64         p_wr_req_parity[256];           /* 0x19000 - 0x197F8 */
 209
 210     char                _pad_019800[0x20000 - 0x019800];
 211
 212     /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
 213     union {
 214         u8              c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
 215         u16     s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
 216         u32     l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
 217         u64     d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
 218         union {
 219             u8  c[0x100 / 1];
 220             u16 s[0x100 / 2];
 221             u32 l[0x100 / 4];
 222             u64 d[0x100 / 8];
 223         } f[8];
 224     } p_type0_cfg_dev[8];                               /* 0x02{0000,,,7FFF} */
 225
 226     /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
 227     union {
 228         u8              c[0x1000 / 1];                  /* 0x028000-0x029000 */
 229         u16     s[0x1000 / 2];                  /* 0x028000-0x029000 */
 230         u32     l[0x1000 / 4];                  /* 0x028000-0x029000 */
 231         u64     d[0x1000 / 8];                  /* 0x028000-0x029000 */
 232         union {
 233             u8  c[0x100 / 1];
 234             u16 s[0x100 / 2];
 235             u32 l[0x100 / 4];
 236             u64 d[0x100 / 8];
 237         } f[8];
 238     } p_type1_cfg;                                      /* 0x028000-0x029000 */
 239
 240     char                _pad_029000[0x030000-0x029000];
 241
 242     /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
 243     union {
 244         u8              c[8 / 1];
 245         u16     s[8 / 2];
 246         u32     l[8 / 4];
 247         u64     d[8 / 8];
 248     } p_pci_iack;                                       /* 0x030000-0x030007 */
 249
 250     char                _pad_030007[0x040000-0x030008];
 251
 252     /* 0x040000-0x030007 -- PCIX Special Cycle */
 253     union {
 254         u8              c[8 / 1];
 255         u16     s[8 / 2];
 256         u32     l[8 / 4];
 257         u64     d[8 / 8];
 258     } p_pcix_cycle;                                     /* 0x040000-0x040007 */
 259 };
 260
 261 #endif                          /* _ASM_IA64_SN_PCI_PIC_H */