release/src-rt-6.x.4708/linux/linux-2.6.36/arch/cris/arch-v32/kernel/kgdb.c

   1 /*
   2  *  arch/cris/arch-v32/kernel/kgdb.c
   3  *
   4  *  CRIS v32 version by Orjan Friberg, Axis Communications AB.
   5  *
   6  *  S390 version
   7  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   8  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
   9  *
  10  *  Originally written by Glenn Engel, Lake Stevens Instrument Division
  11  *
  12  *  Contributed by HP Systems
  13  *
  14  *  Modified for SPARC by Stu Grossman, Cygnus Support.
  15  *
  16  *  Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
  17  *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
  18  *
  19  *  Copyright (C) 1995 Andreas Busse
  20  */
  21
  22
  23
  24 /*
  25  *  To enable debugger support, two things need to happen.  One, a
  26  *  call to kgdb_init() is necessary in order to allow any breakpoints
  27  *  or error conditions to be properly intercepted and reported to gdb.
  28  *  Two, a breakpoint needs to be generated to begin communication.  This
  29  *  is most easily accomplished by a call to breakpoint().
  30  *
  31  *    The following gdb commands are supported:
  32  *
  33  * command          function                               Return value
  34  *
  35  *    g             return the value of the CPU registers  hex data or ENN
  36  *    G             set the value of the CPU registers     OK or ENN
  37  *
  38  *    mAA..AA,LLLL  Read LLLL bytes at address AA..AA      hex data or ENN
  39  *    MAA..AA,LLLL: Write LLLL bytes at address AA.AA      OK or ENN
  40  *
  41  *    c             Resume at current address              SNN   ( signal NN)
  42  *    cAA..AA       Continue at address AA..AA             SNN
  43  *
  44  *    s             Step one instruction                   SNN
  45  *    sAA..AA       Step one instruction from AA..AA       SNN
  46  *
  47  *    k             kill
  48  *
  49  *    ?             What was the last sigval ?             SNN   (signal NN)
  50  *
  51  *    bBB..BB       Set baud rate to BB..BB                OK or BNN, then sets
  52  *                                                         baud rate
  53  *
  54  * All commands and responses are sent with a packet which includes a
  55  * checksum.  A packet consists of
  56  *
  57  * $<packet info>#<checksum>.
  58  *
  59  * where
  60  * <packet info> :: <characters representing the command or response>
  61  * <checksum>    :: < two hex digits computed as modulo 256 sum of <packetinfo>>
  62  *
  63  * When a packet is received, it is first acknowledged with either '+' or '-'.
  64  * '+' indicates a successful transfer.  '-' indicates a failed transfer.
  65  *
  66  * Example:
  67  *
  68  * Host:                  Reply:
  69  * $m0,10#2a               +$00010203040506070809101112131415#42
  70  *
  71  */
  72
  73
  74 #include <linux/string.h>
  75 #include <linux/signal.h>
  76 #include <linux/kernel.h>
  77 #include <linux/delay.h>
  78 #include <linux/linkage.h>
  79 #include <linux/reboot.h>
  80
  81 #include <asm/setup.h>
  82 #include <asm/ptrace.h>
  83
  84 #include <asm/irq.h>
  85 #include <hwregs/reg_map.h>
  86 #include <hwregs/reg_rdwr.h>
  87 #include <hwregs/intr_vect_defs.h>
  88 #include <hwregs/ser_defs.h>
  89
  90 /* From entry.S. */
  91 extern void gdb_handle_exception(void);
  92 /* From kgdb_asm.S. */
  93 extern void kgdb_handle_exception(void);
  94
  95 static int kgdb_started = 0;
  96
  97 /********************************* Register image ****************************/
  98
  99 typedef
 100 struct register_image
 101 {
 102                               /* Offset */
 103         unsigned int   r0;    /* 0x00 */
 104         unsigned int   r1;    /* 0x04 */
 105         unsigned int   r2;    /* 0x08 */
 106         unsigned int   r3;    /* 0x0C */
 107         unsigned int   r4;    /* 0x10 */
 108         unsigned int   r5;    /* 0x14 */
 109         unsigned int   r6;    /* 0x18 */
 110         unsigned int   r7;    /* 0x1C */
 111         unsigned int   r8;    /* 0x20; Frame pointer (if any) */
 112         unsigned int   r9;    /* 0x24 */
 113         unsigned int   r10;   /* 0x28 */
 114         unsigned int   r11;   /* 0x2C */
 115         unsigned int   r12;   /* 0x30 */
 116         unsigned int   r13;   /* 0x34 */
 117         unsigned int   sp;    /* 0x38; R14, Stack pointer */
 118         unsigned int   acr;   /* 0x3C; R15, Address calculation register. */
 119
 120         unsigned char  bz;    /* 0x40; P0, 8-bit zero register */
 121         unsigned char  vr;    /* 0x41; P1, Version register (8-bit) */
 122         unsigned int   pid;   /* 0x42; P2, Process ID */
 123         unsigned char  srs;   /* 0x46; P3, Support register select (8-bit) */
 124         unsigned short wz;    /* 0x47; P4, 16-bit zero register */
 125         unsigned int   exs;   /* 0x49; P5, Exception status */
 126         unsigned int   eda;   /* 0x4D; P6, Exception data address */
 127         unsigned int   mof;   /* 0x51; P7, Multiply overflow register */
 128         unsigned int   dz;    /* 0x55; P8, 32-bit zero register */
 129         unsigned int   ebp;   /* 0x59; P9, Exception base pointer */
 130         unsigned int   erp;   /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
 131         unsigned int   srp;   /* 0x61; P11, Subroutine return pointer */
 132         unsigned int   nrp;   /* 0x65; P12, NMI return pointer */
 133         unsigned int   ccs;   /* 0x69; P13, Condition code stack */
 134         unsigned int   usp;   /* 0x6D; P14, User mode stack pointer */
 135         unsigned int   spc;   /* 0x71; P15, Single step PC */
 136         unsigned int   pc;    /* 0x75; Pseudo register (for the most part set to ERP). */
 137
 138 } registers;
 139
 140 typedef
 141 struct bp_register_image
 142 {
 143         /* Support register bank 0. */
 144         unsigned int   s0_0;
 145         unsigned int   s1_0;
 146         unsigned int   s2_0;
 147         unsigned int   s3_0;
 148         unsigned int   s4_0;
 149         unsigned int   s5_0;
 150         unsigned int   s6_0;
 151         unsigned int   s7_0;
 152         unsigned int   s8_0;
 153         unsigned int   s9_0;
 154         unsigned int   s10_0;
 155         unsigned int   s11_0;
 156         unsigned int   s12_0;
 157         unsigned int   s13_0;
 158         unsigned int   s14_0;
 159         unsigned int   s15_0;
 160
 161         /* Support register bank 1. */
 162         unsigned int   s0_1;
 163         unsigned int   s1_1;
 164         unsigned int   s2_1;
 165         unsigned int   s3_1;
 166         unsigned int   s4_1;
 167         unsigned int   s5_1;
 168         unsigned int   s6_1;
 169         unsigned int   s7_1;
 170         unsigned int   s8_1;
 171         unsigned int   s9_1;
 172         unsigned int   s10_1;
 173         unsigned int   s11_1;
 174         unsigned int   s12_1;
 175         unsigned int   s13_1;
 176         unsigned int   s14_1;
 177         unsigned int   s15_1;
 178
 179         /* Support register bank 2. */
 180         unsigned int   s0_2;
 181         unsigned int   s1_2;
 182         unsigned int   s2_2;
 183         unsigned int   s3_2;
 184         unsigned int   s4_2;
 185         unsigned int   s5_2;
 186         unsigned int   s6_2;
 187         unsigned int   s7_2;
 188         unsigned int   s8_2;
 189         unsigned int   s9_2;
 190         unsigned int   s10_2;
 191         unsigned int   s11_2;
 192         unsigned int   s12_2;
 193         unsigned int   s13_2;
 194         unsigned int   s14_2;
 195         unsigned int   s15_2;
 196
 197         /* Support register bank 3. */
 198         unsigned int   s0_3; /* BP_CTRL */
 199         unsigned int   s1_3; /* BP_I0_START */
 200         unsigned int   s2_3; /* BP_I0_END */
 201         unsigned int   s3_3; /* BP_D0_START */
 202         unsigned int   s4_3; /* BP_D0_END */
 203         unsigned int   s5_3; /* BP_D1_START */
 204         unsigned int   s6_3; /* BP_D1_END */
 205         unsigned int   s7_3; /* BP_D2_START */
 206         unsigned int   s8_3; /* BP_D2_END */
 207         unsigned int   s9_3; /* BP_D3_START */
 208         unsigned int   s10_3; /* BP_D3_END */
 209         unsigned int   s11_3; /* BP_D4_START */
 210         unsigned int   s12_3; /* BP_D4_END */
 211         unsigned int   s13_3; /* BP_D5_START */
 212         unsigned int   s14_3; /* BP_D5_END */
 213         unsigned int   s15_3; /* BP_RESERVED */
 214
 215 } support_registers;
 216
 217 enum register_name
 218 {
 219         R0,  R1,  R2,  R3,
 220         R4,  R5,  R6,  R7,
 221         R8,  R9,  R10, R11,
 222         R12, R13, SP,  ACR,
 223
 224         BZ,  VR,  PID, SRS,
 225         WZ,  EXS, EDA, MOF,
 226         DZ,  EBP, ERP, SRP,
 227         NRP, CCS, USP, SPC,
 228         PC,
 229
 230         S0,  S1,  S2,  S3,
 231         S4,  S5,  S6,  S7,
 232         S8,  S9,  S10, S11,
 233         S12, S13, S14, S15
 234
 235 };
 236
 237 /* The register sizes of the registers in register_name. An unimplemented register
 238    is designated by size 0 in this array. */
 239 static int register_size[] =
 240 {
 241         4, 4, 4, 4,
 242         4, 4, 4, 4,
 243         4, 4, 4, 4,
 244         4, 4, 4, 4,
 245
 246         1, 1, 4, 1,
 247         2, 4, 4, 4,
 248         4, 4, 4, 4,
 249         4, 4, 4, 4,
 250
 251         4,
 252
 253         4, 4, 4, 4,
 254         4, 4, 4, 4,
 255         4, 4, 4, 4,
 256         4, 4, 4
 257
 258 };
 259
 260 /* Contains the register image of the kernel.
 261    (Global so that they can be reached from assembler code.) */
 262 registers reg;
 263 support_registers sreg;
 264
 265 /************** Prototypes for local library functions ***********************/
 266
 267 /* Copy of strcpy from libc. */
 268 static char *gdb_cris_strcpy(char *s1, const char *s2);
 269
 270 /* Copy of strlen from libc. */
 271 static int gdb_cris_strlen(const char *s);
 272
 273 /* Copy of memchr from libc. */
 274 static void *gdb_cris_memchr(const void *s, int c, int n);
 275
 276 /* Copy of strtol from libc. Does only support base 16. */
 277 static int gdb_cris_strtol(const char *s, char **endptr, int base);
 278
 279 /********************** Prototypes for local functions. **********************/
 280
 281 /* Write a value to a specified register regno in the register image
 282    of the current thread. */
 283 static int write_register(int regno, char *val);
 284
 285 /* Read a value from a specified register in the register image. Returns the
 286    status of the read operation. The register value is returned in valptr. */
 287 static int read_register(char regno, unsigned int *valptr);
 288
 289 /* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
 290 int getDebugChar(void);
 291
 292 #ifdef CONFIG_ETRAX_VCS_SIM
 293 int getDebugChar(void)
 294 {
 295   return socketread();
 296 }
 297 #endif
 298
 299 /* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
 300 void putDebugChar(int val);
 301
 302 #ifdef CONFIG_ETRAX_VCS_SIM
 303 void putDebugChar(int val)
 304 {
 305   socketwrite((char *)&val, 1);
 306 }
 307 #endif
 308
 309 /* Returns the integer equivalent of a hexadecimal character. */
 310 static int hex(char ch);
 311
 312 /* Convert the memory, pointed to by mem into hexadecimal representation.
 313    Put the result in buf, and return a pointer to the last character
 314    in buf (null). */
 315 static char *mem2hex(char *buf, unsigned char *mem, int count);
 316
 317 /* Convert the array, in hexadecimal representation, pointed to by buf into
 318    binary representation. Put the result in mem, and return a pointer to
 319    the character after the last byte written. */
 320 static unsigned char *hex2mem(unsigned char *mem, char *buf, int count);
 321
 322 /* Put the content of the array, in binary representation, pointed to by buf
 323    into memory pointed to by mem, and return a pointer to
 324    the character after the last byte written. */
 325 static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
 326
 327 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
 328    returned. */
 329 static void getpacket(char *buffer);
 330
 331 /* Send $<data>#<checksum> from the <data> in the array buffer. */
 332 static void putpacket(char *buffer);
 333
 334 /* Build and send a response packet in order to inform the host the
 335    stub is stopped. */
 336 static void stub_is_stopped(int sigval);
 337
 338 /* All expected commands are sent from remote.c. Send a response according
 339    to the description in remote.c. Not static since it needs to be reached
 340    from assembler code. */
 341 void handle_exception(int sigval);
 342
 343 /* Performs a complete re-start from scratch. ETRAX specific. */
 344 static void kill_restart(void);
 345
 346 /******************** Prototypes for global functions. ***********************/
 347
 348 /* The string str is prepended with the GDB printout token and sent. */
 349 void putDebugString(const unsigned char *str, int len);
 350
 351 /* A static breakpoint to be used at startup. */
 352 void breakpoint(void);
 353
 354 /* Avoid warning as the internal_stack is not used in the C-code. */
 355 #define USEDVAR(name)    { if (name) { ; } }
 356 #define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
 357
 358 /********************************** Packet I/O ******************************/
 359 /* BUFMAX defines the maximum number of characters in
 360    inbound/outbound buffers */
 361 #define BUFMAX 512
 362
 363 /* Run-length encoding maximum length. Send 64 at most. */
 364 #define RUNLENMAX 64
 365
 366 /* The inbound/outbound buffers used in packet I/O */
 367 static char input_buffer[BUFMAX];
 368 static char output_buffer[BUFMAX];
 369
 370 /* Error and warning messages. */
 371 enum error_type
 372 {
 373         SUCCESS, E01, E02, E03, E04, E05, E06,
 374 };
 375
 376 static char *error_message[] =
 377 {
 378         "",
 379         "E01 Set current or general thread - H[c,g] - internal error.",
 380         "E02 Change register content - P - cannot change read-only register.",
 381         "E03 Thread is not alive.", /* T, not used. */
 382         "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
 383         "E05 Change register content - P - the register is not implemented..",
 384         "E06 Change memory content - M - internal error.",
 385 };
 386
 387 /********************************** Breakpoint *******************************/
 388 #define INTERNAL_STACK_SIZE 1024
 389 char internal_stack[INTERNAL_STACK_SIZE];
 390
 391 /* Due to the breakpoint return pointer, a state variable is needed to keep
 392    track of whether it is a static (compiled) or dynamic (gdb-invoked)
 393    breakpoint to be handled. A static breakpoint uses the content of register
 394    ERP as it is whereas a dynamic breakpoint requires subtraction with 2
 395    in order to execute the instruction. The first breakpoint is static; all
 396    following are assumed to be dynamic. */
 397 static int dynamic_bp = 0;
 398
 399 /********************************* String library ****************************/
 400 /* Single-step over library functions creates trap loops. */
 401
 402 /* Copy char s2[] to s1[]. */
 403 static char*
 404 gdb_cris_strcpy(char *s1, const char *s2)
 405 {
 406         char *s = s1;
 407
 408         for (s = s1; (*s++ = *s2++) != '\0'; )
 409                 ;
 410         return s1;
 411 }
 412
 413 /* Find length of s[]. */
 414 static int
 415 gdb_cris_strlen(const char *s)
 416 {
 417         const char *sc;
 418
 419         for (sc = s; *sc != '\0'; sc++)
 420                 ;
 421         return (sc - s);
 422 }
 423
 424 /* Find first occurrence of c in s[n]. */
 425 static void*
 426 gdb_cris_memchr(const void *s, int c, int n)
 427 {
 428         const unsigned char uc = c;
 429         const unsigned char *su;
 430
 431         for (su = s; 0 < n; ++su, --n)
 432                 if (*su == uc)
 433                         return (void *)su;
 434         return NULL;
 435 }
 436 /******************************* Standard library ****************************/
 437 /* Single-step over library functions creates trap loops. */
 438 /* Convert string to long. */
 439 static int
 440 gdb_cris_strtol(const char *s, char **endptr, int base)
 441 {
 442         char *s1;
 443         char *sd;
 444         int x = 0;
 445
 446         for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
 447                 x = x * base + (sd - hex_asc);
 448
 449         if (endptr) {
 450                 /* Unconverted suffix is stored in endptr unless endptr is NULL. */
 451                 *endptr = s1;
 452         }
 453
 454         return x;
 455 }
 456
 457 /********************************* Register image ****************************/
 458
 459 /* Write a value to a specified register in the register image of the current
 460    thread. Returns status code SUCCESS, E02 or E05. */
 461 static int
 462 write_register(int regno, char *val)
 463 {
 464         int status = SUCCESS;
 465
 466         if (regno >= R0 && regno <= ACR) {
 467                 /* Consecutive 32-bit registers. */
 468                 hex2mem((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
 469                         val, sizeof(unsigned int));
 470
 471         } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
 472                 /* Read-only registers. */
 473                 status = E02;
 474
 475         } else if (regno == PID) {
 476                 /* 32-bit register. (Even though we already checked SRS and WZ, we cannot
 477                    combine this with the EXS - SPC write since SRS and WZ have different size.) */
 478                 hex2mem((unsigned char *)&reg.pid, val, sizeof(unsigned int));
 479
 480         } else if (regno == SRS) {
 481                 /* 8-bit register. */
 482                 hex2mem((unsigned char *)&reg.srs, val, sizeof(unsigned char));
 483
 484         } else if (regno >= EXS && regno <= SPC) {
 485                 /* Consecutive 32-bit registers. */
 486                 hex2mem((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
 487                          val, sizeof(unsigned int));
 488
 489        } else if (regno == PC) {
 490                /* Pseudo-register. Treat as read-only. */
 491                status = E02;
 492
 493        } else if (regno >= S0 && regno <= S15) {
 494                /* 32-bit registers. */
 495                hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int));
 496         } else {
 497                 /* Non-existing register. */
 498                 status = E05;
 499         }
 500         return status;
 501 }
 502
 503 /* Read a value from a specified register in the register image. Returns the
 504    value in the register or -1 for non-implemented registers. */
 505 static int
 506 read_register(char regno, unsigned int *valptr)
 507 {
 508         int status = SUCCESS;
 509
 510         /* We read the zero registers from the register struct (instead of just returning 0)
 511            to catch errors. */
 512
 513         if (regno >= R0 && regno <= ACR) {
 514                 /* Consecutive 32-bit registers. */
 515                 *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
 516
 517         } else if (regno == BZ || regno == VR) {
 518                 /* Consecutive 8-bit registers. */
 519                 *valptr = (unsigned int)(*(unsigned char *)
 520                                          ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
 521
 522         } else if (regno == PID) {
 523                 /* 32-bit register. */
 524                 *valptr =  *(unsigned int *)((char *)&reg.pid);
 525
 526         } else if (regno == SRS) {
 527                 /* 8-bit register. */
 528                 *valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
 529
 530         } else if (regno == WZ) {
 531                 /* 16-bit register. */
 532                 *valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
 533
 534         } else if (regno >= EXS && regno <= PC) {
 535                 /* Consecutive 32-bit registers. */
 536                 *valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
 537
 538         } else if (regno >= S0 && regno <= S15) {
 539                 /* Consecutive 32-bit registers, located elsewhere. */
 540                 *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
 541
 542         } else {
 543                 /* Non-existing register. */
 544                 status = E05;
 545         }
 546         return status;
 547
 548 }
 549
 550 /********************************** Packet I/O ******************************/
 551 /* Returns the integer equivalent of a hexadecimal character. */
 552 static int
 553 hex(char ch)
 554 {
 555         if ((ch >= 'a') && (ch <= 'f'))
 556                 return (ch - 'a' + 10);
 557         if ((ch >= '0') && (ch <= '9'))
 558                 return (ch - '0');
 559         if ((ch >= 'A') && (ch <= 'F'))
 560                 return (ch - 'A' + 10);
 561         return -1;
 562 }
 563
 564 /* Convert the memory, pointed to by mem into hexadecimal representation.
 565    Put the result in buf, and return a pointer to the last character
 566    in buf (null). */
 567
 568 static char *
 569 mem2hex(char *buf, unsigned char *mem, int count)
 570 {
 571         int i;
 572         int ch;
 573
 574         if (mem == NULL) {
 575                 /* Invalid address, caught by 'm' packet handler. */
 576                 for (i = 0; i < count; i++) {
 577                         *buf++ = '0';
 578                         *buf++ = '0';
 579                 }
 580         } else {
 581                 /* Valid mem address. */
 582                 for (i = 0; i < count; i++) {
 583                         ch = *mem++;
 584                         buf = pack_hex_byte(buf, ch);
 585                 }
 586         }
 587         /* Terminate properly. */
 588         *buf = '\0';
 589         return buf;
 590 }
 591
 592 /* Same as mem2hex, but puts it in network byte order. */
 593 static char *
 594 mem2hex_nbo(char *buf, unsigned char *mem, int count)
 595 {
 596         int i;
 597         int ch;
 598
 599         mem += count - 1;
 600         for (i = 0; i < count; i++) {
 601                 ch = *mem--;
 602                 buf = pack_hex_byte(buf, ch);
 603         }
 604
 605         /* Terminate properly. */
 606         *buf = '\0';
 607         return buf;
 608 }
 609
 610 /* Convert the array, in hexadecimal representation, pointed to by buf into
 611    binary representation. Put the result in mem, and return a pointer to
 612    the character after the last byte written. */
 613 static unsigned char*
 614 hex2mem(unsigned char *mem, char *buf, int count)
 615 {
 616         int i;
 617         unsigned char ch;
 618         for (i = 0; i < count; i++) {
 619                 ch = hex (*buf++) << 4;
 620                 ch = ch + hex (*buf++);
 621                 *mem++ = ch;
 622         }
 623         return mem;
 624 }
 625
 626 /* Put the content of the array, in binary representation, pointed to by buf
 627    into memory pointed to by mem, and return a pointer to the character after
 628    the last byte written.
 629    Gdb will escape $, #, and the escape char (0x7d). */
 630 static unsigned char*
 631 bin2mem(unsigned char *mem, unsigned char *buf, int count)
 632 {
 633         int i;
 634         unsigned char *next;
 635         for (i = 0; i < count; i++) {
 636                 /* Check for any escaped characters. Be paranoid and
 637                    only unescape chars that should be escaped. */
 638                 if (*buf == 0x7d) {
 639                         next = buf + 1;
 640                         if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
 641                                  /* #, $, ESC */
 642                                 buf++;
 643                                 *buf += 0x20;
 644                         }
 645                 }
 646                 *mem++ = *buf++;
 647         }
 648         return mem;
 649 }
 650
 651 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
 652    returned. */
 653 static void
 654 getpacket(char *buffer)
 655 {
 656         unsigned char checksum;
 657         unsigned char xmitcsum;
 658         int i;
 659         int count;
 660         char ch;
 661
 662         do {
 663                 while((ch = getDebugChar ()) != '$')
 664                         /* Wait for the start character $ and ignore all other characters */;
 665                 checksum = 0;
 666                 xmitcsum = -1;
 667                 count = 0;
 668                 /* Read until a # or the end of the buffer is reached */
 669                 while (count < BUFMAX) {
 670                         ch = getDebugChar();
 671                         if (ch == '#')
 672                                 break;
 673                         checksum = checksum + ch;
 674                         buffer[count] = ch;
 675                         count = count + 1;
 676                 }
 677
 678                 if (count >= BUFMAX)
 679                         continue;
 680
 681                 buffer[count] = 0;
 682
 683                 if (ch == '#') {
 684                         xmitcsum = hex(getDebugChar()) << 4;
 685                         xmitcsum += hex(getDebugChar());
 686                         if (checksum != xmitcsum) {
 687                                 /* Wrong checksum */
 688                                 putDebugChar('-');
 689                         } else {
 690                                 /* Correct checksum */
 691                                 putDebugChar('+');
 692                                 /* If sequence characters are received, reply with them */
 693                                 if (buffer[2] == ':') {
 694                                         putDebugChar(buffer[0]);
 695                                         putDebugChar(buffer[1]);
 696                                         /* Remove the sequence characters from the buffer */
 697                                         count = gdb_cris_strlen(buffer);
 698                                         for (i = 3; i <= count; i++)
 699                                                 buffer[i - 3] = buffer[i];
 700                                 }
 701                         }
 702                 }
 703         } while (checksum != xmitcsum);
 704 }
 705
 706 /* Send $<data>#<checksum> from the <data> in the array buffer. */
 707
 708 static void
 709 putpacket(char *buffer)
 710 {
 711         int checksum;
 712         int runlen;
 713         int encode;
 714
 715         do {
 716                 char *src = buffer;
 717                 putDebugChar('$');
 718                 checksum = 0;
 719                 while (*src) {
 720                         /* Do run length encoding */
 721                         putDebugChar(*src);
 722                         checksum += *src;
 723                         runlen = 0;
 724                         while (runlen < RUNLENMAX && *src == src[runlen]) {
 725                                 runlen++;
 726                         }
 727                         if (runlen > 3) {
 728                                 /* Got a useful amount */
 729                                 putDebugChar ('*');
 730                                 checksum += '*';
 731                                 encode = runlen + ' ' - 4;
 732                                 putDebugChar(encode);
 733                                 checksum += encode;
 734                                 src += runlen;
 735                         } else {
 736                                 src++;
 737                         }
 738                 }
 739                 putDebugChar('#');
 740                 putDebugChar(hex_asc_hi(checksum));
 741                 putDebugChar(hex_asc_lo(checksum));
 742         } while(kgdb_started && (getDebugChar() != '+'));
 743 }
 744
 745 /* The string str is prepended with the GDB printout token and sent. Required
 746    in traditional implementations. */
 747 void
 748 putDebugString(const unsigned char *str, int len)
 749 {
 750         /* Move SPC forward if we are single-stepping. */
 751         asm("spchere:");
 752         asm("move $spc, $r10");
 753         asm("cmp.d spchere, $r10");
 754         asm("bne nosstep");
 755         asm("nop");
 756         asm("move.d spccont, $r10");
 757         asm("move $r10, $spc");
 758         asm("nosstep:");
 759
 760         output_buffer[0] = 'O';
 761         mem2hex(&output_buffer[1], (unsigned char *)str, len);
 762         putpacket(output_buffer);
 763
 764         asm("spccont:");
 765 }
 766
 767 /********************************** Handle exceptions ************************/
 768 /* Build and send a response packet in order to inform the host the
 769    stub is stopped. TAAn...:r...;n...:r...;n...:r...;
 770                     AA = signal number
 771                     n... = register number (hex)
 772                     r... = register contents
 773                     n... = `thread'
 774                     r... = thread process ID.  This is a hex integer.
 775                     n... = other string not starting with valid hex digit.
 776                     gdb should ignore this n,r pair and go on to the next.
 777                     This way we can extend the protocol. */
 778 static void
 779 stub_is_stopped(int sigval)
 780 {
 781         char *ptr = output_buffer;
 782         unsigned int reg_cont;
 783
 784         /* Send trap type (converted to signal) */
 785
 786         *ptr++ = 'T';
 787         ptr = pack_hex_byte(ptr, sigval);
 788
 789         if (((reg.exs & 0xff00) >> 8) == 0xc) {
 790
 791                 /* Some kind of hardware watchpoint triggered. Find which one
 792                    and determine its type (read/write/access).  */
 793                 int S, bp, trig_bits = 0, rw_bits = 0;
 794                 int trig_mask = 0;
 795                 unsigned int *bp_d_regs = &sreg.s3_3;
 796                 /* In a lot of cases, the stopped data address will simply be EDA.
 797                    In some cases, we adjust it to match the watched data range.
 798                    (We don't want to change the actual EDA though). */
 799                 unsigned int stopped_data_address;
 800                 /* The S field of EXS. */
 801                 S = (reg.exs & 0xffff0000) >> 16;
 802
 803                 if (S & 1) {
 804                         /* Instruction watchpoint. */
 805                 } else {
 806                         /* Data watchpoint.  Find the one that triggered. */
 807                         for (bp = 0; bp < 6; bp++) {
 808
 809                                 /* Dx_RD, Dx_WR in the S field of EXS for this BP. */
 810                                 int bitpos_trig = 1 + bp * 2;
 811                                 /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
 812                                 int bitpos_config = 2 + bp * 4;
 813
 814                                 /* Get read/write trig bits for this BP. */
 815                                 trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
 816
 817                                 /* Read/write config bits for this BP. */
 818                                 rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
 819                                 if (trig_bits) {
 820                                         /* Sanity check: the BP shouldn't trigger for accesses
 821                                            that it isn't configured for. */
 822                                         if ((rw_bits == 0x1 && trig_bits != 0x1) ||
 823                                             (rw_bits == 0x2 && trig_bits != 0x2))
 824                                                 panic("Invalid r/w trigging for this BP");
 825
 826                                         /* Mark this BP as trigged for future reference. */
 827                                         trig_mask |= (1 << bp);
 828
 829                                         if (reg.eda >= bp_d_regs[bp * 2] &&
 830                                             reg.eda <= bp_d_regs[bp * 2 + 1]) {
 831                                                 /* EDA withing range for this BP; it must be the one
 832                                                    we're looking for. */
 833                                                 stopped_data_address = reg.eda;
 834                                                 break;
 835                                         }
 836                                 }
 837                         }
 838                         if (bp < 6) {
 839                                 /* Found a trigged BP with EDA within its configured data range. */
 840                         } else if (trig_mask) {
 841                                 /* Something triggered, but EDA doesn't match any BP's range. */
 842                                 for (bp = 0; bp < 6; bp++) {
 843                                         /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
 844                                         int bitpos_config = 2 + bp * 4;
 845
 846                                         /* Read/write config bits for this BP (needed later). */
 847                                         rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
 848
 849                                         if (trig_mask & (1 << bp)) {
 850                                                 /* EDA within 31 bytes of the configured start address? */
 851                                                 if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
 852                                                         /* Changing the reported address to match
 853                                                            the start address of the first applicable BP. */
 854                                                         stopped_data_address = bp_d_regs[bp * 2];
 855                                                         break;
 856                                                 } else {
 857                                                         /* We continue since we might find another useful BP. */
 858                                                         printk("EDA doesn't match trigged BP's range");
 859                                                 }
 860                                         }
 861                                 }
 862                         }
 863
 864                         /* No match yet? */
 865                         BUG_ON(bp >= 6);
 866                         /* Note that we report the type according to what the BP is configured
 867                            for (otherwise we'd never report an 'awatch'), not according to how
 868                            it trigged. We did check that the trigged bits match what the BP is
 869                            configured for though. */
 870                         if (rw_bits == 0x1) {
 871                                 /* read */
 872                                 strncpy(ptr, "rwatch", 6);
 873                                 ptr += 6;
 874                         } else if (rw_bits == 0x2) {
 875                                 /* write */
 876                                 strncpy(ptr, "watch", 5);
 877                                 ptr += 5;
 878                         } else if (rw_bits == 0x3) {
 879                                 /* access */
 880                                 strncpy(ptr, "awatch", 6);
 881                                 ptr += 6;
 882                         } else {
 883                                 panic("Invalid r/w bits for this BP.");
 884                         }
 885
 886                         *ptr++ = ':';
 887                         /* Note that we don't read_register(EDA, ...) */
 888                         ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
 889                         *ptr++ = ';';
 890                 }
 891         }
 892         /* Only send PC, frame and stack pointer. */
 893         read_register(PC, &reg_cont);
 894         ptr = pack_hex_byte(ptr, PC);
 895         *ptr++ = ':';
 896         ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
 897         *ptr++ = ';';
 898
 899         read_register(R8, &reg_cont);
 900         ptr = pack_hex_byte(ptr, R8);
 901         *ptr++ = ':';
 902         ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
 903         *ptr++ = ';';
 904
 905         read_register(SP, &reg_cont);
 906         ptr = pack_hex_byte(ptr, SP);
 907         *ptr++ = ':';
 908         ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
 909         *ptr++ = ';';
 910
 911         /* Send ERP as well; this will save us an entire register fetch in some cases. */
 912         read_register(ERP, &reg_cont);
 913         ptr = pack_hex_byte(ptr, ERP);
 914         *ptr++ = ':';
 915         ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
 916         *ptr++ = ';';
 917
 918         /* null-terminate and send it off */
 919         *ptr = 0;
 920         putpacket(output_buffer);
 921 }
 922
 923 /* Returns the size of an instruction that has a delay slot. */
 924
 925 int insn_size(unsigned long pc)
 926 {
 927         unsigned short opcode = *(unsigned short *)pc;
 928         int size = 0;
 929
 930         switch ((opcode & 0x0f00) >> 8) {
 931         case 0x0:
 932         case 0x9:
 933         case 0xb:
 934                 size = 2;
 935                 break;
 936         case 0xe:
 937         case 0xf:
 938                 size = 6;
 939                 break;
 940         case 0xd:
 941                 /* Could be 4 or 6; check more bits. */
 942                 if ((opcode & 0xff) == 0xff)
 943                         size = 4;
 944                 else
 945                         size = 6;
 946                 break;
 947         default:
 948                 panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
 949         }
 950
 951         return size;
 952 }
 953
 954 void register_fixup(int sigval)
 955 {
 956         /* Compensate for ACR push at the beginning of exception handler. */
 957         reg.sp += 4;
 958
 959         /* Standard case. */
 960         reg.pc = reg.erp;
 961         if (reg.erp & 0x1) {
 962                 /* Delay slot bit set.  Report as stopped on proper instruction.  */
 963                 if (reg.spc) {
 964                         /* Rely on SPC if set. */
 965                         reg.pc = reg.spc;
 966                 } else {
 967                         /* Calculate the PC from the size of the instruction
 968                            that the delay slot we're in belongs to. */
 969                         reg.pc += insn_size(reg.erp & ~1) - 1 ;
 970                 }
 971         }
 972
 973         if ((reg.exs & 0x3) == 0x0) {
 974                 /* Bits 1 - 0 indicate the type of memory operation performed
 975                    by the interrupted instruction. 0 means no memory operation,
 976                    and EDA is undefined in that case. We zero it to avoid confusion. */
 977                 reg.eda = 0;
 978         }
 979
 980         if (sigval == SIGTRAP) {
 981                 /* Break 8, single step or hardware breakpoint exception. */
 982
 983                 /* Check IDX field of EXS. */
 984                 if (((reg.exs & 0xff00) >> 8) == 0x18) {
 985
 986                         /* Break 8. */
 987
 988                         /* Static (compiled) breakpoints must return to the next instruction
 989                            in order to avoid infinite loops (default value of ERP). Dynamic
 990                            (gdb-invoked) must subtract the size of the break instruction from
 991                            the ERP so that the instruction that was originally in the break
 992                            instruction's place will be run when we return from the exception. */
 993                         if (!dynamic_bp) {
 994                                 /* Assuming that all breakpoints are dynamic from now on. */
 995                                 dynamic_bp = 1;
 996                         } else {
 997
 998                                 /* Only if not in a delay slot. */
 999                                 if (!(reg.erp & 0x1)) {
1000                                         reg.erp -= 2;
1001                                         reg.pc -= 2;
1002                                 }
1003                         }
1004
1005                 } else if (((reg.exs & 0xff00) >> 8) == 0x3) {
1006                         /* Single step. */
1007                         /* Don't fiddle with S1. */
1008
1009                 } else if (((reg.exs & 0xff00) >> 8) == 0xc) {
1010
1011                         /* Hardware watchpoint exception. */
1012
1013                         /* SPC has been updated so that we will get a single step exception
1014                            when we return, but we don't want that. */
1015                         reg.spc = 0;
1016
1017                         /* Don't fiddle with S1. */
1018                 }
1019
1020         } else if (sigval == SIGINT) {
1021                 /* Nothing special. */
1022         }
1023 }
1024
1025 static void insert_watchpoint(char type, int addr, int len)
1026 {
1027         /* Breakpoint/watchpoint types (GDB terminology):
1028            0 = memory breakpoint for instructions
1029            (not supported; done via memory write instead)
1030            1 = hardware breakpoint for instructions (supported)
1031            2 = write watchpoint (supported)
1032            3 = read watchpoint (supported)
1033            4 = access watchpoint (supported) */
1034
1035         if (type < '1' || type > '4') {
1036                 output_buffer[0] = 0;
1037                 return;
1038         }
1039
1040         /* Read watchpoints are set as access watchpoints, because of GDB's
1041            inability to deal with pure read watchpoints. */
1042         if (type == '3')
1043                 type = '4';
1044
1045         if (type == '1') {
1046                 /* Hardware (instruction) breakpoint. */
1047                 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1048                 if (sreg.s0_3 & 0x1) {
1049                         /* Already in use. */
1050                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1051                         return;
1052                 }
1053                 /* Configure. */
1054                 sreg.s1_3 = addr;
1055                 sreg.s2_3 = (addr + len - 1);
1056                 sreg.s0_3 |= 1;
1057         } else {
1058                 int bp;
1059                 unsigned int *bp_d_regs = &sreg.s3_3;
1060
1061                 /* The watchpoint allocation scheme is the simplest possible.
1062                    For example, if a region is watched for read and
1063                    a write watch is requested, a new watchpoint will
1064                    be used. Also, if a watch for a region that is already
1065                    covered by one or more existing watchpoints, a new
1066                    watchpoint will be used. */
1067
1068                 /* First, find a free data watchpoint. */
1069                 for (bp = 0; bp < 6; bp++) {
1070                         /* Each data watchpoint's control registers occupy 2 bits
1071                            (hence the 3), starting at bit 2 for D0 (hence the 2)
1072                            with 4 bits between for each watchpoint (yes, the 4). */
1073                         if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
1074                                 break;
1075                         }
1076                 }
1077
1078                 if (bp > 5) {
1079                         /* We're out of watchpoints. */
1080                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1081                         return;
1082                 }
1083
1084                 /* Configure the control register first. */
1085                 if (type == '3' || type == '4') {
1086                         /* Trigger on read. */
1087                         sreg.s0_3 |= (1 << (2 + bp * 4));
1088                 }
1089                 if (type == '2' || type == '4') {
1090                         /* Trigger on write. */
1091                         sreg.s0_3 |= (2 << (2 + bp * 4));
1092                 }
1093
1094                 /* Ugly pointer arithmetics to configure the watched range. */
1095                 bp_d_regs[bp * 2] = addr;
1096                 bp_d_regs[bp * 2 + 1] = (addr + len - 1);
1097         }
1098
1099         /* Set the S1 flag to enable watchpoints. */
1100         reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1101         gdb_cris_strcpy(output_buffer, "OK");
1102 }
1103
1104 static void remove_watchpoint(char type, int addr, int len)
1105 {
1106         /* Breakpoint/watchpoint types:
1107            0 = memory breakpoint for instructions
1108            (not supported; done via memory write instead)
1109            1 = hardware breakpoint for instructions (supported)
1110            2 = write watchpoint (supported)
1111            3 = read watchpoint (supported)
1112            4 = access watchpoint (supported) */
1113         if (type < '1' || type > '4') {
1114                 output_buffer[0] = 0;
1115                 return;
1116         }
1117
1118         /* Read watchpoints are set as access watchpoints, because of GDB's
1119            inability to deal with pure read watchpoints. */
1120         if (type == '3')
1121                 type = '4';
1122
1123         if (type == '1') {
1124                 /* Hardware breakpoint. */
1125                 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1126                 if (!(sreg.s0_3 & 0x1)) {
1127                         /* Not in use. */
1128                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1129                         return;
1130                 }
1131                 /* Deconfigure. */
1132                 sreg.s1_3 = 0;
1133                 sreg.s2_3 = 0;
1134                 sreg.s0_3 &= ~1;
1135         } else {
1136                 int bp;
1137                 unsigned int *bp_d_regs = &sreg.s3_3;
1138                 /* Try to find a watchpoint that is configured for the
1139                    specified range, then check that read/write also matches. */
1140
1141                 /* Ugly pointer arithmetic, since I cannot rely on a
1142                    single switch (addr) as there may be several watchpoints with
1143                    the same start address for example. */
1144
1145                 for (bp = 0; bp < 6; bp++) {
1146                         if (bp_d_regs[bp * 2] == addr &&
1147                             bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
1148                                 /* Matching range. */
1149                                 int bitpos = 2 + bp * 4;
1150                                 int rw_bits;
1151
1152                                 /* Read/write bits for this BP. */
1153                                 rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
1154
1155                                 if ((type == '3' && rw_bits == 0x1) ||
1156                                     (type == '2' && rw_bits == 0x2) ||
1157                                     (type == '4' && rw_bits == 0x3)) {
1158                                         /* Read/write matched. */
1159                                         break;
1160                                 }
1161                         }
1162                 }
1163
1164                 if (bp > 5) {
1165                         /* No watchpoint matched. */
1166                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1167                         return;
1168                 }
1169
1170                 /* Found a matching watchpoint. Now, deconfigure it by
1171                    both disabling read/write in bp_ctrl and zeroing its
1172                    start/end addresses. */
1173                 sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
1174                 bp_d_regs[bp * 2] = 0;
1175                 bp_d_regs[bp * 2 + 1] = 0;
1176         }
1177
1178         /* Note that we don't clear the S1 flag here. It's done when continuing.  */
1179         gdb_cris_strcpy(output_buffer, "OK");
1180 }
1181
1182
1183
1184 /* All expected commands are sent from remote.c. Send a response according
1185    to the description in remote.c. */
1186 void
1187 handle_exception(int sigval)
1188 {
1189         /* Avoid warning of not used. */
1190
1191         USEDFUN(handle_exception);
1192         USEDVAR(internal_stack[0]);
1193
1194         register_fixup(sigval);
1195
1196         /* Send response. */
1197         stub_is_stopped(sigval);
1198
1199         for (;;) {
1200                 output_buffer[0] = '\0';
1201                 getpacket(input_buffer);
1202                 switch (input_buffer[0]) {
1203                         case 'g':
1204                                 /* Read registers: g
1205                                    Success: Each byte of register data is described by two hex digits.
1206                                    Registers are in the internal order for GDB, and the bytes
1207                                    in a register  are in the same order the machine uses.
1208                                    Failure: void. */
1209                         {
1210                                 char *buf;
1211                                 /* General and special registers. */
1212                                 buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
1213                                 /* Support registers. */
1214                                 /* -1 because of the null termination that mem2hex adds. */
1215                                 mem2hex(buf,
1216                                         (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1217                                         16 * sizeof(unsigned int));
1218                                 break;
1219                         }
1220                         case 'G':
1221                                 /* Write registers. GXX..XX
1222                                    Each byte of register data  is described by two hex digits.
1223                                    Success: OK
1224                                    Failure: void. */
1225                                 /* General and special registers. */
1226                                 hex2mem((char *)&reg, &input_buffer[1], sizeof(registers));
1227                                 /* Support registers. */
1228                                 hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1229                                         &input_buffer[1] + sizeof(registers),
1230                                         16 * sizeof(unsigned int));
1231                                 gdb_cris_strcpy(output_buffer, "OK");
1232                                 break;
1233
1234                         case 'P':
1235                                 /* Write register. Pn...=r...
1236                                    Write register n..., hex value without 0x, with value r...,
1237                                    which contains a hex value without 0x and two hex digits
1238                                    for each byte in the register (target byte order). P1f=11223344 means
1239                                    set register 31 to 44332211.
1240                                    Success: OK
1241                                    Failure: E02, E05 */
1242                                 {
1243                                         char *suffix;
1244                                         int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
1245                                         int status;
1246
1247                                         status = write_register(regno, suffix+1);
1248
1249                                         switch (status) {
1250                                                 case E02:
1251                                                         /* Do not support read-only registers. */
1252                                                         gdb_cris_strcpy(output_buffer, error_message[E02]);
1253                                                         break;
1254                                                 case E05:
1255                                                         /* Do not support non-existing registers. */
1256                                                         gdb_cris_strcpy(output_buffer, error_message[E05]);
1257                                                         break;
1258                                                 default:
1259                                                         /* Valid register number. */
1260                                                         gdb_cris_strcpy(output_buffer, "OK");
1261                                                         break;
1262                                         }
1263                                 }
1264                                 break;
1265
1266                         case 'm':
1267                                 /* Read from memory. mAA..AA,LLLL
1268                                    AA..AA is the address and LLLL is the length.
1269                                    Success: XX..XX is the memory content.  Can be fewer bytes than
1270                                    requested if only part of the data may be read. m6000120a,6c means
1271                                    retrieve 108 byte from base address 6000120a.
1272                                    Failure: void. */
1273                                 {
1274                                         char *suffix;
1275                                         unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1276                                                                                                &suffix, 16);
1277                                         int len = gdb_cris_strtol(suffix+1, 0, 16);
1278
1279                                         /* Bogus read (i.e. outside the kernel's
1280                                            segment)? . */
1281                                         if (!((unsigned int)addr >= 0xc0000000 &&
1282                                               (unsigned int)addr < 0xd0000000))
1283                                                 addr = NULL;
1284
1285                                         mem2hex(output_buffer, addr, len);
1286                                 }
1287                                 break;
1288
1289                         case 'X':
1290                                 /* Write to memory. XAA..AA,LLLL:XX..XX
1291                                    AA..AA is the start address,  LLLL is the number of bytes, and
1292                                    XX..XX is the binary data.
1293                                    Success: OK
1294                                    Failure: void. */
1295                         case 'M':
1296                                 /* Write to memory. MAA..AA,LLLL:XX..XX
1297                                    AA..AA is the start address,  LLLL is the number of bytes, and
1298                                    XX..XX is the hexadecimal data.
1299                                    Success: OK
1300                                    Failure: void. */
1301                                 {
1302                                         char *lenptr;
1303                                         char *dataptr;
1304                                         unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1305                                                                                       &lenptr, 16);
1306                                         int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
1307                                         if (*lenptr == ',' && *dataptr == ':') {
1308                                                 if (input_buffer[0] == 'M') {
1309                                                         hex2mem(addr, dataptr + 1, len);
1310                                                 } else /* X */ {
1311                                                         bin2mem(addr, dataptr + 1, len);
1312                                                 }
1313                                                 gdb_cris_strcpy(output_buffer, "OK");
1314                                         }
1315                                         else {
1316                                                 gdb_cris_strcpy(output_buffer, error_message[E06]);
1317                                         }
1318                                 }
1319                                 break;
1320
1321                         case 'c':
1322                                 /* Continue execution. cAA..AA
1323                                    AA..AA is the address where execution is resumed. If AA..AA is
1324                                    omitted, resume at the present address.
1325                                    Success: return to the executing thread.
1326                                    Failure: will never know. */
1327
1328                                 if (input_buffer[1] != '\0') {
1329                                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1330                                         break;
1331                                 }
1332
1333                                 /* Before continuing, make sure everything is set up correctly. */
1334
1335                                 /* Set the SPC to some unlikely value.  */
1336                                 reg.spc = 0;
1337                                 /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
1338                                    S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
1339                                    are reserved, so don't check against those). */
1340                                 if ((sreg.s0_3 & 0x3fff) == 0) {
1341                                         reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
1342                                 }
1343
1344                                 return;
1345
1346                         case 's':
1347                                 /* Step. sAA..AA
1348                                    AA..AA is the address where execution is resumed. If AA..AA is
1349                                    omitted, resume at the present address. Success: return to the
1350                                    executing thread. Failure: will never know. */
1351
1352                                 if (input_buffer[1] != '\0') {
1353                                         gdb_cris_strcpy(output_buffer, error_message[E04]);
1354                                         break;
1355                                 }
1356
1357                                 /* Set the SPC to PC, which is where we'll return
1358                                    (deduced previously). */
1359                                 reg.spc = reg.pc;
1360
1361                                 /* Set the S1 (first stacked, not current) flag, which will
1362                                    kick into action when we rfe. */
1363                                 reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1364                                 return;
1365
1366                        case 'Z':
1367
1368                                /* Insert breakpoint or watchpoint, Ztype,addr,length.
1369                                   Remote protocol says: A remote target shall return an empty string
1370                                   for an unrecognized breakpoint or watchpoint packet type. */
1371                                {
1372                                        char *lenptr;
1373                                        char *dataptr;
1374                                        int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1375                                        int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1376                                        char type = input_buffer[1];
1377
1378                                        insert_watchpoint(type, addr, len);
1379                                        break;
1380                                }
1381
1382                        case 'z':
1383                                /* Remove breakpoint or watchpoint, Ztype,addr,length.
1384                                   Remote protocol says: A remote target shall return an empty string
1385                                   for an unrecognized breakpoint or watchpoint packet type. */
1386                                {
1387                                        char *lenptr;
1388                                        char *dataptr;
1389                                        int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1390                                        int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1391                                        char type = input_buffer[1];
1392
1393                                        remove_watchpoint(type, addr, len);
1394                                        break;
1395                                }
1396
1397
1398                         case '?':
1399                                 /* The last signal which caused a stop. ?
1400                                    Success: SAA, where AA is the signal number.
1401                                    Failure: void. */
1402                                 output_buffer[0] = 'S';
1403                                 output_buffer[1] = hex_asc_hi(sigval);
1404                                 output_buffer[2] = hex_asc_lo(sigval);
1405                                 output_buffer[3] = 0;
1406                                 break;
1407
1408                         case 'D':
1409                                 /* Detach from host. D
1410                                    Success: OK, and return to the executing thread.
1411                                    Failure: will never know */
1412                                 putpacket("OK");
1413                                 return;
1414
1415                         case 'k':
1416                         case 'r':
1417                                 /* kill request or reset request.
1418                                    Success: restart of target.
1419                                    Failure: will never know. */
1420                                 kill_restart();
1421                                 break;
1422
1423                         case 'C':
1424                         case 'S':
1425                         case '!':
1426                         case 'R':
1427                         case 'd':
1428                                 /* Continue with signal sig. Csig;AA..AA
1429                                    Step with signal sig. Ssig;AA..AA
1430                                    Use the extended remote protocol. !
1431                                    Restart the target system. R0
1432                                    Toggle debug flag. d
1433                                    Search backwards. tAA:PP,MM
1434                                    Not supported: E04 */
1435
1436                                 gdb_cris_strcpy(output_buffer, error_message[E04]);
1437                                 break;
1438
1439                         default:
1440                                 /* The stub should ignore other request and send an empty
1441                                    response ($#<checksum>). This way we can extend the protocol and GDB
1442                                    can tell whether the stub it is talking to uses the old or the new. */
1443                                 output_buffer[0] = 0;
1444                                 break;
1445                 }
1446                 putpacket(output_buffer);
1447         }
1448 }
1449
1450 void
1451 kgdb_init(void)
1452 {
1453         reg_intr_vect_rw_mask intr_mask;
1454         reg_ser_rw_intr_mask ser_intr_mask;
1455
1456         /* Configure the kgdb serial port. */
1457 #if defined(CONFIG_ETRAX_KGDB_PORT0)
1458         /* Note: no shortcut registered (not handled by multiple_interrupt).
1459            See entry.S.  */
1460         set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
1461         /* Enable the ser irq in the global config. */
1462         intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1463         intr_mask.ser0 = 1;
1464         REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1465
1466         ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
1467         ser_intr_mask.dav = regk_ser_yes;
1468         REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
1469 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
1470         /* Note: no shortcut registered (not handled by multiple_interrupt).
1471            See entry.S.  */
1472         set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
1473         /* Enable the ser irq in the global config. */
1474         intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1475         intr_mask.ser1 = 1;
1476         REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1477
1478         ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
1479         ser_intr_mask.dav = regk_ser_yes;
1480         REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
1481 #elif defined(CONFIG_ETRAX_KGDB_PORT2)
1482         /* Note: no shortcut registered (not handled by multiple_interrupt).
1483            See entry.S.  */
1484         set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
1485         /* Enable the ser irq in the global config. */
1486         intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1487         intr_mask.ser2 = 1;
1488         REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1489
1490         ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
1491         ser_intr_mask.dav = regk_ser_yes;
1492         REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
1493 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
1494         /* Note: no shortcut registered (not handled by multiple_interrupt).
1495            See entry.S.  */
1496         set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
1497         /* Enable the ser irq in the global config. */
1498         intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1499         intr_mask.ser3 = 1;
1500         REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1501
1502         ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
1503         ser_intr_mask.dav = regk_ser_yes;
1504         REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
1505 #endif
1506
1507 }
1508 /* Performs a complete re-start from scratch. */
1509 static void
1510 kill_restart(void)
1511 {
1512         machine_restart("");
1513 }
1514
1515 /* Use this static breakpoint in the start-up only. */
1516
1517 void
1518 breakpoint(void)
1519 {
1520         kgdb_started = 1;
1521         dynamic_bp = 0;     /* This is a static, not a dynamic breakpoint. */
1522         __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
1523 }
1524
1525 /****************************** End of file **********************************/