release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/include/asm/cplb.h

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _CPLB_H
   8 #define _CPLB_H
   9
  10 #include <mach/anomaly.h>
  11
  12 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
  13 #define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
  14 #define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  15 #define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
  16
  17 #if ANOMALY_05000158
  18 #define ANOMALY_05000158_WORKAROUND             0x200
  19 #else
  20 #define ANOMALY_05000158_WORKAROUND             0x0
  21 #endif
  22
  23 #define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  24
  25 #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
  26 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
  27 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
  28 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
  29 #else
  30 #define SDRAM_DGENERIC   (CPLB_COMMON)
  31 #endif
  32
  33 #define SDRAM_DNON_CHBL  (CPLB_COMMON)
  34 #define SDRAM_EBIU       (CPLB_COMMON)
  35 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
  36
  37 #define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
  38
  39 #ifdef CONFIG_SMP
  40 #define L2_ATTR          (INITIAL_T | I_CPLB | D_CPLB)
  41 #define L2_IMEMORY       (CPLB_COMMON | PAGE_SIZE_1MB)
  42 #define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
  43
  44 #else
  45 #define L2_ATTR          (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
  46 # if defined(CONFIG_BFIN_L2_ICACHEABLE)
  47 # define L2_IMEMORY      (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
  48 # else
  49 # define L2_IMEMORY      (               CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
  50 # endif
  51
  52 # if defined(CONFIG_BFIN_L2_WRITEBACK)
  53 # define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
  54 # elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
  55 # define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
  56 # else
  57 # define L2_DMEMORY      (CPLB_COMMON | PAGE_SIZE_1MB)
  58 # endif
  59 #endif /* CONFIG_SMP */
  60
  61 #define SIZE_1K 0x00000400      /* 1K */
  62 #define SIZE_4K 0x00001000      /* 4K */
  63 #define SIZE_1M 0x00100000      /* 1M */
  64 #define SIZE_4M 0x00400000      /* 4M */
  65
  66 #define MAX_CPLBS 16
  67
  68 #define CPLB_ENABLE_ICACHE_P    0
  69 #define CPLB_ENABLE_DCACHE_P    1
  70 #define CPLB_ENABLE_DCACHE2_P   2
  71 #define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
  72 #define CPLB_ENABLE_ICPLBS_P    4
  73 #define CPLB_ENABLE_DCPLBS_P    5
  74
  75 #define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
  76 #define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
  77 #define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
  78 #define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
  79 #define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
  80 #define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
  81 #define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
  82                                 CPLB_ENABLE_ICPLBS | \
  83                                 CPLB_ENABLE_DCPLBS
  84
  85 #define CPLB_RELOADED           0x0000
  86 #define CPLB_NO_UNLOCKED        0x0001
  87 #define CPLB_NO_ADDR_MATCH      0x0002
  88 #define CPLB_PROT_VIOL          0x0003
  89 #define CPLB_UNKNOWN_ERR        0x0004
  90
  91 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
  92 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
  93
  94 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
  95 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
  96 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
  97 #define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
  98 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
  99 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
 100
 101 #define FAULT_RW        (1 << 16)
 102 #define FAULT_USERSUPV  (1 << 17)
 103 #define FAULT_CPLBBITS  0x0000ffff
 104
 105 #ifndef __ASSEMBLY__
 106
 107 static inline void _disable_cplb(u32 mmr, u32 mask)
 108 {
 109         u32 ctrl = bfin_read32(mmr) & ~mask;
 110         /* CSYNC to ensure load store ordering */
 111         __builtin_bfin_csync();
 112         bfin_write32(mmr, ctrl);
 113         __builtin_bfin_ssync();
 114 }
 115 static inline void disable_cplb(u32 mmr, u32 mask)
 116 {
 117         u32 ctrl = bfin_read32(mmr) & ~mask;
 118         CSYNC();
 119         bfin_write32(mmr, ctrl);
 120         SSYNC();
 121 }
 122 #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
 123 #define  disable_dcplb()  disable_cplb(DMEM_CONTROL, ENDCPLB)
 124 #define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
 125 #define  disable_icplb()  disable_cplb(IMEM_CONTROL, ENICPLB)
 126
 127 static inline void _enable_cplb(u32 mmr, u32 mask)
 128 {
 129         u32 ctrl = bfin_read32(mmr) | mask;
 130         /* CSYNC to ensure load store ordering */
 131         __builtin_bfin_csync();
 132         bfin_write32(mmr, ctrl);
 133         __builtin_bfin_ssync();
 134 }
 135 static inline void enable_cplb(u32 mmr, u32 mask)
 136 {
 137         u32 ctrl = bfin_read32(mmr) | mask;
 138         CSYNC();
 139         bfin_write32(mmr, ctrl);
 140         SSYNC();
 141 }
 142 #define _enable_dcplb()  _enable_cplb(DMEM_CONTROL, ENDCPLB)
 143 #define  enable_dcplb()   enable_cplb(DMEM_CONTROL, ENDCPLB)
 144 #define _enable_icplb()  _enable_cplb(IMEM_CONTROL, ENICPLB)
 145 #define  enable_icplb()   enable_cplb(IMEM_CONTROL, ENICPLB)
 146
 147 #endif          /* __ASSEMBLY__ */
 148
 149 #endif          /* _CPLB_H */