release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-samsung/include/plat/gpio-core.h

   1 /* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
   2  *
   3  * Copyright 2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C Platform - GPIO core
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #define GPIOCON_OFF     (0x00)
  15 #define GPIODAT_OFF     (0x04)
  16
  17 #define con_4bit_shift(__off) ((__off) * 4)
  18
  19 /* Define the core gpiolib support functions that the s3c platforms may
  20  * need to extend or change depending on the hardware and the s3c chip
  21  * selected at build or found at run time.
  22  *
  23  * These definitions are not intended for driver inclusion, there is
  24  * nothing here that should not live outside the platform and core
  25  * specific code.
  26 */
  27
  28 struct s3c_gpio_chip;
  29
  30 /**
  31  * struct s3c_gpio_pm - power management (suspend/resume) information
  32  * @save: Routine to save the state of the GPIO block
  33  * @resume: Routine to resume the GPIO block.
  34  */
  35 struct s3c_gpio_pm {
  36         void (*save)(struct s3c_gpio_chip *chip);
  37         void (*resume)(struct s3c_gpio_chip *chip);
  38 };
  39
  40 struct s3c_gpio_cfg;
  41
  42 /**
  43  * struct s3c_gpio_chip - wrapper for specific implementation of gpio
  44  * @chip: The chip structure to be exported via gpiolib.
  45  * @base: The base pointer to the gpio configuration registers.
  46  * @config: special function and pull-resistor control information.
  47  * @lock: Lock for exclusive access to this gpio bank.
  48  * @pm_save: Save information for suspend/resume support.
  49  *
  50  * This wrapper provides the necessary information for the Samsung
  51  * specific gpios being registered with gpiolib.
  52  *
  53  * The lock protects each gpio bank from multiple access of the shared
  54  * configuration registers, or from reading of data whilst another thread
  55  * is writing to the register set.
  56  *
  57  * Each chip has its own lock to avoid any  contention between different
  58  * CPU cores trying to get one lock for different GPIO banks, where each
  59  * bank of GPIO has its own register space and configuration registers.
  60  */
  61 struct s3c_gpio_chip {
  62         struct gpio_chip        chip;
  63         struct s3c_gpio_cfg     *config;
  64         struct s3c_gpio_pm      *pm;
  65         void __iomem            *base;
  66         spinlock_t               lock;
  67 #ifdef CONFIG_PM
  68         u32                     pm_save[4];
  69 #endif
  70 };
  71
  72 static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
  73 {
  74         return container_of(gpc, struct s3c_gpio_chip, chip);
  75 }
  76
  77 /** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
  78  * @chip: The chip to register
  79  *
  80  * This is a wrapper to gpiochip_add() that takes our specific gpio chip
  81  * information and makes the necessary alterations for the platform and
  82  * notes the information for use with the configuration systems and any
  83  * other parts of the system.
  84  */
  85 extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
  86
  87 /* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
  88  * for use with the configuration calls, and other parts of the s3c gpiolib
  89  * support code.
  90  *
  91  * Not all s3c support code will need this, as some configurations of cpu
  92  * may only support one or two different configuration options and have an
  93  * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
  94  * the machine support file should provide its own s3c_gpiolib_getchip()
  95  * and any other necessary functions.
  96  */
  97
  98 /**
  99  * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
 100  * @chip: The gpio chip that is being configured.
 101  * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
 102  *
 103  * This helper deal with the GPIO cases where the control register has 4 bits
 104  * of control per GPIO, generally in the form of:
 105  * 0000 = Input
 106  * 0001 = Output
 107  * others = Special functions (dependant on bank)
 108  *
 109  * Note, since the code to deal with the case where there are two control
 110  * registers instead of one, we do not have a separate set of function
 111  * (samsung_gpiolib_add_4bit2_chips)for each case.
 112  */
 113 extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
 114                                            int nr_chips);
 115 extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 116                                             int nr_chips);
 117
 118 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 119 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 120
 121 /* exported for core SoC support to change */
 122 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 123
 124 #ifdef CONFIG_S3C_GPIO_TRACK
 125 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 126
 127 static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
 128 {
 129         return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
 130 }
 131 #else
 132 /* machine specific code should provide s3c_gpiolib_getchip */
 133
 134 #include <mach/gpio-track.h>
 135
 136 static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
 137 #endif
 138
 139 #ifdef CONFIG_PM
 140 extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
 141 extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
 142 extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
 143 #define __gpio_pm(x) x
 144 #else
 145 #define s3c_gpio_pm_1bit NULL
 146 #define s3c_gpio_pm_2bit NULL
 147 #define s3c_gpio_pm_4bit NULL
 148 #define __gpio_pm(x) NULL
 149
 150 #endif /* CONFIG_PM */
 151
 152 /* locking wrappers to deal with multiple access to the same gpio bank */
 153 #define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
 154 #define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)