1 /* linux/arch/arm/plat-s3c24xx/dma.c
3 * Copyright 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
30 #include <asm/system.h>
32 #include <mach/hardware.h>
36 #include <plat/dma-s3c24xx.h>
37 #include <plat/regs-dma.h>
40 static void __iomem
*dma_base
;
41 static struct kmem_cache
*dma_kmem
;
43 static int dma_channels
;
45 static struct s3c24xx_dma_selection dma_sel
;
48 /* debugging functions */
50 #define BUF_MAGIC (0xcafebabe)
52 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
54 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
56 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
58 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
60 /* captured register state for debug */
62 struct s3c2410_dma_regstate
{
67 unsigned long dmsktrig
;
70 #ifdef CONFIG_S3C2410_DMA_DEBUG
74 * simple debug routine to print the current state of the dma registers
78 dmadbg_capture(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_regstate
*regs
)
80 regs
->dcsrc
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
81 regs
->disrc
= dma_rdreg(chan
, S3C2410_DMA_DISRC
);
82 regs
->dstat
= dma_rdreg(chan
, S3C2410_DMA_DSTAT
);
83 regs
->dcon
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
84 regs
->dmsktrig
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
88 dmadbg_dumpregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
,
89 struct s3c2410_dma_regstate
*regs
)
91 printk(KERN_DEBUG
"dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
92 chan
->number
, fname
, line
,
93 regs
->dcsrc
, regs
->disrc
, regs
->dstat
, regs
->dmsktrig
,
98 dmadbg_showchan(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
100 struct s3c2410_dma_regstate state
;
102 dmadbg_capture(chan
, &state
);
104 printk(KERN_DEBUG
"dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
105 chan
->number
, fname
, line
, chan
->load_state
,
106 chan
->curr
, chan
->next
, chan
->end
);
108 dmadbg_dumpregs(fname
, line
, chan
, &state
);
112 dmadbg_showregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
114 struct s3c2410_dma_regstate state
;
116 dmadbg_capture(chan
, &state
);
117 dmadbg_dumpregs(fname
, line
, chan
, &state
);
120 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
121 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
123 #define dbg_showregs(chan) do { } while(0)
124 #define dbg_showchan(chan) do { } while(0)
125 #endif /* CONFIG_S3C2410_DMA_DEBUG */
127 /* s3c2410_dma_stats_timeout
129 * Update DMA stats from timeout info
133 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats
*stats
, int val
)
138 if (val
> stats
->timeout_longest
)
139 stats
->timeout_longest
= val
;
140 if (val
< stats
->timeout_shortest
)
141 stats
->timeout_shortest
= val
;
143 stats
->timeout_avg
+= val
;
146 /* s3c2410_dma_waitforload
148 * wait for the DMA engine to load a buffer, and update the state accordingly
152 s3c2410_dma_waitforload(struct s3c2410_dma_chan
*chan
, int line
)
154 int timeout
= chan
->load_timeout
;
157 if (chan
->load_state
!= S3C2410_DMALOAD_1LOADED
) {
158 printk(KERN_ERR
"dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan
->number
, chan
->load_state
, line
);
162 if (chan
->stats
!= NULL
)
163 chan
->stats
->loads
++;
165 while (--timeout
> 0) {
166 if ((dma_rdreg(chan
, S3C2410_DMA_DSTAT
) << (32-20)) != 0) {
167 took
= chan
->load_timeout
- timeout
;
169 s3c2410_dma_stats_timeout(chan
->stats
, took
);
171 switch (chan
->load_state
) {
172 case S3C2410_DMALOAD_1LOADED
:
173 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
177 printk(KERN_ERR
"dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan
->number
, chan
->load_state
);
184 if (chan
->stats
!= NULL
) {
185 chan
->stats
->timeout_failed
++;
191 /* s3c2410_dma_loadbuffer
193 * load a buffer, and update the channel state
197 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan
*chan
,
198 struct s3c2410_dma_buf
*buf
)
200 unsigned long reload
;
203 dmawarn("buffer is NULL\n");
207 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
208 buf
, (unsigned long)buf
->data
, buf
->size
);
210 /* check the state of the channel before we do anything */
212 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
213 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
216 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED_1RUNNING
) {
217 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
220 /* it would seem sensible if we are the last buffer to not bother
221 * with the auto-reload bit, so that the DMA engine will not try
222 * and load another transfer after this one has finished...
224 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
225 pr_debug("load_state is none, checking for noreload (next=%p)\n",
227 reload
= (buf
->next
== NULL
) ? S3C2410_DCON_NORELOAD
: 0;
229 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
230 reload
= S3C2410_DCON_AUTORELOAD
;
233 if ((buf
->data
& 0xf0000000) != 0x30000000) {
234 dmawarn("dmaload: buffer is %p\n", (void *)buf
->data
);
237 writel(buf
->data
, chan
->addr_reg
);
239 dma_wrreg(chan
, S3C2410_DMA_DCON
,
240 chan
->dcon
| reload
| (buf
->size
/chan
->xfer_unit
));
242 chan
->next
= buf
->next
;
244 /* update the state of the channel */
246 switch (chan
->load_state
) {
247 case S3C2410_DMALOAD_NONE
:
248 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
251 case S3C2410_DMALOAD_1RUNNING
:
252 chan
->load_state
= S3C2410_DMALOAD_1LOADED_1RUNNING
;
256 dmawarn("dmaload: unknown state %d in loadbuffer\n",
264 /* s3c2410_dma_call_op
266 * small routine to call the op routine with the given op if it has been
271 s3c2410_dma_call_op(struct s3c2410_dma_chan
*chan
, enum s3c2410_chan_op op
)
273 if (chan
->op_fn
!= NULL
) {
274 (chan
->op_fn
)(chan
, op
);
278 /* s3c2410_dma_buffdone
280 * small wrapper to check if callback routine needs to be called, and
285 s3c2410_dma_buffdone(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_buf
*buf
,
286 enum s3c2410_dma_buffresult result
)
289 if (chan
->callback_fn
!= NULL
) {
290 (chan
->callback_fn
)(chan
, buf
->id
, buf
->size
, result
);
296 * start a dma channel going
299 static int s3c2410_dma_start(struct s3c2410_dma_chan
*chan
)
304 pr_debug("s3c2410_start_dma: channel=%d\n", chan
->number
);
306 local_irq_save(flags
);
308 if (chan
->state
== S3C2410_DMA_RUNNING
) {
309 pr_debug("s3c2410_start_dma: already running (%d)\n", chan
->state
);
310 local_irq_restore(flags
);
314 chan
->state
= S3C2410_DMA_RUNNING
;
316 /* check wether there is anything to load, and if not, see
317 * if we can find anything to load
320 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
321 if (chan
->next
== NULL
) {
322 printk(KERN_ERR
"dma%d: channel has nothing loaded\n",
324 chan
->state
= S3C2410_DMA_IDLE
;
325 local_irq_restore(flags
);
329 s3c2410_dma_loadbuffer(chan
, chan
->next
);
334 /* enable the channel */
336 if (!chan
->irq_enabled
) {
337 enable_irq(chan
->irq
);
338 chan
->irq_enabled
= 1;
341 /* start the channel going */
343 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
344 tmp
&= ~S3C2410_DMASKTRIG_STOP
;
345 tmp
|= S3C2410_DMASKTRIG_ON
;
346 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
348 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan
->number
, tmp
);
351 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_START
);
355 /* if we've only loaded one buffer onto the channel, then chec
356 * to see if we have another, and if so, try and load it so when
357 * the first buffer is finished, the new one will be loaded onto
360 if (chan
->next
!= NULL
) {
361 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
363 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
364 pr_debug("%s: buff not yet loaded, no more todo\n",
367 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
368 s3c2410_dma_loadbuffer(chan
, chan
->next
);
371 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
372 s3c2410_dma_loadbuffer(chan
, chan
->next
);
377 local_irq_restore(flags
);
382 /* s3c2410_dma_canload
384 * work out if we can queue another buffer into the DMA engine
388 s3c2410_dma_canload(struct s3c2410_dma_chan
*chan
)
390 if (chan
->load_state
== S3C2410_DMALOAD_NONE
||
391 chan
->load_state
== S3C2410_DMALOAD_1RUNNING
)
397 /* s3c2410_dma_enqueue
399 * queue an given buffer for dma transfer.
401 * id the device driver's id information for this buffer
402 * data the physical address of the buffer data
403 * size the size of the buffer in bytes
405 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
406 * is checked, and if set, the channel is started. If this flag isn't set,
407 * then an error will be returned.
409 * It is possible to queue more than one DMA buffer onto a channel at
410 * once, and the code will deal with the re-loading of the next buffer
414 int s3c2410_dma_enqueue(unsigned int channel
, void *id
,
415 dma_addr_t data
, int size
)
417 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
418 struct s3c2410_dma_buf
*buf
;
424 pr_debug("%s: id=%p, data=%08x, size=%d\n",
425 __func__
, id
, (unsigned int)data
, size
);
427 buf
= kmem_cache_alloc(dma_kmem
, GFP_ATOMIC
);
429 pr_debug("%s: out of memory (%ld alloc)\n",
430 __func__
, (long)sizeof(*buf
));
434 //pr_debug("%s: new buffer %p\n", __func__, buf);
435 //dbg_showchan(chan);
438 buf
->data
= buf
->ptr
= data
;
441 buf
->magic
= BUF_MAGIC
;
443 local_irq_save(flags
);
445 if (chan
->curr
== NULL
) {
446 /* we've got nothing loaded... */
447 pr_debug("%s: buffer %p queued onto empty channel\n",
454 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
455 chan
->number
, __func__
, buf
);
457 if (chan
->end
== NULL
)
458 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
459 chan
->number
, __func__
, chan
);
461 chan
->end
->next
= buf
;
465 /* if necessary, update the next buffer field */
466 if (chan
->next
== NULL
)
469 /* check to see if we can load a buffer */
470 if (chan
->state
== S3C2410_DMA_RUNNING
) {
471 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
&& 1) {
472 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
473 printk(KERN_ERR
"dma%d: loadbuffer:"
474 "timeout loading buffer\n",
477 local_irq_restore(flags
);
482 while (s3c2410_dma_canload(chan
) && chan
->next
!= NULL
) {
483 s3c2410_dma_loadbuffer(chan
, chan
->next
);
485 } else if (chan
->state
== S3C2410_DMA_IDLE
) {
486 if (chan
->flags
& S3C2410_DMAF_AUTOSTART
) {
487 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
488 S3C2410_DMAOP_START
);
492 local_irq_restore(flags
);
496 EXPORT_SYMBOL(s3c2410_dma_enqueue
);
499 s3c2410_dma_freebuf(struct s3c2410_dma_buf
*buf
)
501 int magicok
= (buf
->magic
== BUF_MAGIC
);
506 kmem_cache_free(dma_kmem
, buf
);
508 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf
);
512 /* s3c2410_dma_lastxfer
514 * called when the system is out of buffers, to ensure that the channel
515 * is prepared for shutdown.
519 s3c2410_dma_lastxfer(struct s3c2410_dma_chan
*chan
)
522 switch (chan
->load_state
) {
523 case S3C2410_DMALOAD_NONE
:
526 case S3C2410_DMALOAD_1LOADED
:
527 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
529 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
530 chan
->number
, __func__
);
535 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
536 /* I belive in this case we do not have anything to do
537 * until the next buffer comes along, and we turn off the
542 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
543 chan
->number
, chan
->load_state
);
548 /* hopefully this'll shut the damned thing up after the transfer... */
549 dma_wrreg(chan
, S3C2410_DMA_DCON
, chan
->dcon
| S3C2410_DCON_NORELOAD
);
553 #define dmadbg2(x...)
556 s3c2410_dma_irq(int irq
, void *devpw
)
558 struct s3c2410_dma_chan
*chan
= (struct s3c2410_dma_chan
*)devpw
;
559 struct s3c2410_dma_buf
*buf
;
565 /* modify the channel state */
567 switch (chan
->load_state
) {
568 case S3C2410_DMALOAD_1RUNNING
:
569 /* TODO - if we are running only one buffer, we probably
570 * want to reload here, and then worry about the buffer
573 chan
->load_state
= S3C2410_DMALOAD_NONE
;
576 case S3C2410_DMALOAD_1LOADED
:
577 /* iirc, we should go back to NONE loaded here, we
578 * had a buffer, and it was never verified as being
582 chan
->load_state
= S3C2410_DMALOAD_NONE
;
585 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
586 /* we'll worry about checking to see if another buffer is
587 * ready after we've called back the owner. This should
588 * ensure we do not wait around too long for the DMA
589 * engine to start the next transfer
592 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
595 case S3C2410_DMALOAD_NONE
:
596 printk(KERN_ERR
"dma%d: IRQ with no loaded buffer?\n",
601 printk(KERN_ERR
"dma%d: IRQ in invalid load_state %d\n",
602 chan
->number
, chan
->load_state
);
607 /* update the chain to make sure that if we load any more
608 * buffers when we call the callback function, things should
611 chan
->curr
= buf
->next
;
614 if (buf
->magic
!= BUF_MAGIC
) {
615 printk(KERN_ERR
"dma%d: %s: buf %p incorrect magic\n",
616 chan
->number
, __func__
, buf
);
620 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_OK
);
623 s3c2410_dma_freebuf(buf
);
627 /* only reload if the channel is still running... our buffer done
628 * routine may have altered the state by requesting the dma channel
629 * to stop or shutdown... */
631 /* todo: check that when the channel is shut-down from inside this
632 * function, we cope with unsetting reload, etc */
634 if (chan
->next
!= NULL
&& chan
->state
!= S3C2410_DMA_IDLE
) {
637 switch (chan
->load_state
) {
638 case S3C2410_DMALOAD_1RUNNING
:
639 /* don't need to do anything for this state */
642 case S3C2410_DMALOAD_NONE
:
643 /* can load buffer immediately */
646 case S3C2410_DMALOAD_1LOADED
:
647 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
649 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
650 chan
->number
, __func__
);
656 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
660 printk(KERN_ERR
"dma%d: unknown load_state in irq, %d\n",
661 chan
->number
, chan
->load_state
);
665 local_irq_save(flags
);
666 s3c2410_dma_loadbuffer(chan
, chan
->next
);
667 local_irq_restore(flags
);
669 s3c2410_dma_lastxfer(chan
);
671 /* see if we can stop this channel.. */
672 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
673 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
674 chan
->number
, jiffies
);
675 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
684 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
);
686 /* s3c2410_request_dma
688 * get control of an dma channel
691 int s3c2410_dma_request(unsigned int channel
,
692 struct s3c2410_dma_client
*client
,
695 struct s3c2410_dma_chan
*chan
;
699 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
700 channel
, client
->name
, dev
);
702 local_irq_save(flags
);
704 chan
= s3c2410_dma_map_channel(channel
);
706 local_irq_restore(flags
);
712 chan
->client
= client
;
715 if (!chan
->irq_claimed
) {
716 pr_debug("dma%d: %s : requesting irq %d\n",
717 channel
, __func__
, chan
->irq
);
719 chan
->irq_claimed
= 1;
720 local_irq_restore(flags
);
722 err
= request_irq(chan
->irq
, s3c2410_dma_irq
, IRQF_DISABLED
,
723 client
->name
, (void *)chan
);
725 local_irq_save(flags
);
729 chan
->irq_claimed
= 0;
730 local_irq_restore(flags
);
732 printk(KERN_ERR
"%s: cannot get IRQ %d for DMA %d\n",
733 client
->name
, chan
->irq
, chan
->number
);
737 chan
->irq_enabled
= 1;
740 local_irq_restore(flags
);
744 pr_debug("%s: channel initialised, %p\n", __func__
, chan
);
746 return chan
->number
| DMACH_LOW_LEVEL
;
749 EXPORT_SYMBOL(s3c2410_dma_request
);
753 * release the given channel back to the system, will stop and flush
754 * any outstanding transfers, and ensure the channel is ready for the
757 * Note, although a warning is currently printed if the freeing client
758 * info is not the same as the registrant's client info, the free is still
759 * allowed to go through.
762 int s3c2410_dma_free(unsigned int channel
, struct s3c2410_dma_client
*client
)
764 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
770 local_irq_save(flags
);
772 if (chan
->client
!= client
) {
773 printk(KERN_WARNING
"dma%d: possible free from different client (channel %p, passed %p)\n",
774 channel
, chan
->client
, client
);
777 /* sort out stopping and freeing the channel */
779 if (chan
->state
!= S3C2410_DMA_IDLE
) {
780 pr_debug("%s: need to stop dma channel %p\n",
783 /* possibly flush the channel */
784 s3c2410_dma_ctrl(channel
, S3C2410_DMAOP_STOP
);
790 if (chan
->irq_claimed
)
791 free_irq(chan
->irq
, (void *)chan
);
793 chan
->irq_claimed
= 0;
795 if (!(channel
& DMACH_LOW_LEVEL
))
796 s3c_dma_chan_map
[channel
] = NULL
;
798 local_irq_restore(flags
);
803 EXPORT_SYMBOL(s3c2410_dma_free
);
805 static int s3c2410_dma_dostop(struct s3c2410_dma_chan
*chan
)
810 pr_debug("%s:\n", __func__
);
814 local_irq_save(flags
);
816 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_STOP
);
818 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
819 tmp
|= S3C2410_DMASKTRIG_STOP
;
820 //tmp &= ~S3C2410_DMASKTRIG_ON;
821 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
824 /* should stop do this, or should we wait for flush? */
825 chan
->state
= S3C2410_DMA_IDLE
;
826 chan
->load_state
= S3C2410_DMALOAD_NONE
;
828 local_irq_restore(flags
);
833 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan
*chan
)
836 unsigned int timeout
= 0x10000;
838 while (timeout
-- > 0) {
839 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
841 if (!(tmp
& S3C2410_DMASKTRIG_ON
))
845 pr_debug("dma%d: failed to stop?\n", chan
->number
);
851 * stop the channel, and remove all current and pending transfers
854 static int s3c2410_dma_flush(struct s3c2410_dma_chan
*chan
)
856 struct s3c2410_dma_buf
*buf
, *next
;
859 pr_debug("%s: chan %p (%d)\n", __func__
, chan
, chan
->number
);
863 local_irq_save(flags
);
865 if (chan
->state
!= S3C2410_DMA_IDLE
) {
866 pr_debug("%s: stopping channel...\n", __func__
);
867 s3c2410_dma_ctrl(chan
->number
, S3C2410_DMAOP_STOP
);
874 chan
->curr
= chan
->next
= chan
->end
= NULL
;
877 for ( ; buf
!= NULL
; buf
= next
) {
880 pr_debug("%s: free buffer %p, next %p\n",
881 __func__
, buf
, buf
->next
);
883 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_ABORT
);
884 s3c2410_dma_freebuf(buf
);
890 s3c2410_dma_waitforstop(chan
);
895 local_irq_restore(flags
);
900 static int s3c2410_dma_started(struct s3c2410_dma_chan
*chan
)
904 local_irq_save(flags
);
908 /* if we've only loaded one buffer onto the channel, then chec
909 * to see if we have another, and if so, try and load it so when
910 * the first buffer is finished, the new one will be loaded onto
913 if (chan
->next
!= NULL
) {
914 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
916 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
917 pr_debug("%s: buff not yet loaded, no more todo\n",
920 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
921 s3c2410_dma_loadbuffer(chan
, chan
->next
);
924 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
925 s3c2410_dma_loadbuffer(chan
, chan
->next
);
930 local_irq_restore(flags
);
937 s3c2410_dma_ctrl(unsigned int channel
, enum s3c2410_chan_op op
)
939 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
945 case S3C2410_DMAOP_START
:
946 return s3c2410_dma_start(chan
);
948 case S3C2410_DMAOP_STOP
:
949 return s3c2410_dma_dostop(chan
);
951 case S3C2410_DMAOP_PAUSE
:
952 case S3C2410_DMAOP_RESUME
:
955 case S3C2410_DMAOP_FLUSH
:
956 return s3c2410_dma_flush(chan
);
958 case S3C2410_DMAOP_STARTED
:
959 return s3c2410_dma_started(chan
);
961 case S3C2410_DMAOP_TIMEOUT
:
966 return -ENOENT
; /* unknown, don't bother */
969 EXPORT_SYMBOL(s3c2410_dma_ctrl
);
971 /* DMA configuration for each channel
973 * DISRCC -> source of the DMA (AHB,APB)
974 * DISRC -> source address of the DMA
975 * DIDSTC -> destination of the DMA (AHB,APD)
976 * DIDST -> destination address of the DMA
979 /* s3c2410_dma_config
981 * xfersize: size of unit in bytes (1,2,4)
984 int s3c2410_dma_config(unsigned int channel
,
987 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
990 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
991 __func__
, channel
, xferunit
, dcon
);
996 pr_debug("%s: Initial dcon is %08x\n", __func__
, dcon
);
998 dcon
= chan
->dcon
& dma_sel
.dcon_mask
;
1000 pr_debug("%s: New dcon is %08x\n", __func__
, dcon
);
1002 switch (chan
->req_ch
) {
1009 dcon
|= S3C2410_DCON_HANDSHAKE
;
1010 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1014 /* note, ensure if need HANDSHAKE or not */
1015 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1020 dcon
|= S3C2410_DCON_HANDSHAKE
;
1021 dcon
|= S3C2410_DCON_SYNC_HCLK
;
1027 dcon
|= S3C2410_DCON_BYTE
;
1031 dcon
|= S3C2410_DCON_HALFWORD
;
1035 dcon
|= S3C2410_DCON_WORD
;
1039 pr_debug("%s: bad transfer size %d\n", __func__
, xferunit
);
1043 dcon
|= S3C2410_DCON_HWTRIG
;
1044 dcon
|= S3C2410_DCON_INTREQ
;
1046 pr_debug("%s: dcon now %08x\n", __func__
, dcon
);
1049 chan
->xfer_unit
= xferunit
;
1054 EXPORT_SYMBOL(s3c2410_dma_config
);
1057 /* s3c2410_dma_devconfig
1059 * configure the dma source/destination hardware type and address
1061 * source: S3C2410_DMASRC_HW: source is hardware
1062 * S3C2410_DMASRC_MEM: source is memory
1064 * devaddr: physical address of the source
1067 int s3c2410_dma_devconfig(unsigned int channel
,
1068 enum s3c2410_dmasrc source
,
1069 unsigned long devaddr
)
1071 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
1077 pr_debug("%s: source=%d, devaddr=%08lx\n",
1078 __func__
, (int)source
, devaddr
);
1080 chan
->source
= source
;
1081 chan
->dev_addr
= devaddr
;
1083 switch (chan
->req_ch
) {
1086 hwcfg
= 0; /* AHB */
1090 hwcfg
= S3C2410_DISRCC_APB
;
1093 /* always assume our peripheral desintation is a fixed
1094 * address in memory. */
1095 hwcfg
|= S3C2410_DISRCC_INC
;
1098 case S3C2410_DMASRC_HW
:
1099 /* source is hardware */
1100 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1101 __func__
, devaddr
, hwcfg
);
1102 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, hwcfg
& 3);
1103 dma_wrreg(chan
, S3C2410_DMA_DISRC
, devaddr
);
1104 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, (0<<1) | (0<<0));
1106 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DIDST
);
1109 case S3C2410_DMASRC_MEM
:
1110 /* source is memory */
1111 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1112 __func__
, devaddr
, hwcfg
);
1113 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, (0<<1) | (0<<0));
1114 dma_wrreg(chan
, S3C2410_DMA_DIDST
, devaddr
);
1115 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, hwcfg
& 3);
1117 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DISRC
);
1121 printk(KERN_ERR
"dma%d: invalid source type (%d)\n",
1127 if (dma_sel
.direction
!= NULL
)
1128 (dma_sel
.direction
)(chan
, chan
->map
, source
);
1133 EXPORT_SYMBOL(s3c2410_dma_devconfig
);
1135 /* s3c2410_dma_getposition
1137 * returns the current transfer points for the dma source and destination
1140 int s3c2410_dma_getposition(unsigned int channel
, dma_addr_t
*src
, dma_addr_t
*dst
)
1142 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
1148 *src
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
1151 *dst
= dma_rdreg(chan
, S3C2410_DMA_DCDST
);
1156 EXPORT_SYMBOL(s3c2410_dma_getposition
);
1158 static inline struct s3c2410_dma_chan
*to_dma_chan(struct sys_device
*dev
)
1160 return container_of(dev
, struct s3c2410_dma_chan
, dev
);
1163 /* system device class */
1167 static int s3c2410_dma_suspend(struct sys_device
*dev
, pm_message_t state
)
1169 struct s3c2410_dma_chan
*cp
= to_dma_chan(dev
);
1171 printk(KERN_DEBUG
"suspending dma channel %d\n", cp
->number
);
1173 if (dma_rdreg(cp
, S3C2410_DMA_DMASKTRIG
) & S3C2410_DMASKTRIG_ON
) {
1174 /* the dma channel is still working, which is probably
1175 * a bad thing to do over suspend/resume. We stop the
1176 * channel and assume that the client is either going to
1177 * retry after resume, or that it is broken.
1180 printk(KERN_INFO
"dma: stopping channel %d due to suspend\n",
1183 s3c2410_dma_dostop(cp
);
1189 static int s3c2410_dma_resume(struct sys_device
*dev
)
1191 struct s3c2410_dma_chan
*cp
= to_dma_chan(dev
);
1192 unsigned int no
= cp
->number
| DMACH_LOW_LEVEL
;
1194 /* restore channel's hardware configuration */
1199 printk(KERN_INFO
"dma%d: restoring configuration\n", cp
->number
);
1201 s3c2410_dma_config(no
, cp
->xfer_unit
);
1202 s3c2410_dma_devconfig(no
, cp
->source
, cp
->dev_addr
);
1204 /* re-select the dma source for this channel */
1206 if (cp
->map
!= NULL
)
1207 dma_sel
.select(cp
, cp
->map
);
1213 #define s3c2410_dma_suspend NULL
1214 #define s3c2410_dma_resume NULL
1215 #endif /* CONFIG_PM */
1217 struct sysdev_class dma_sysclass
= {
1218 .name
= "s3c24xx-dma",
1219 .suspend
= s3c2410_dma_suspend
,
1220 .resume
= s3c2410_dma_resume
,
1223 /* kmem cache implementation */
1225 static void s3c2410_dma_cache_ctor(void *p
)
1227 memset(p
, 0, sizeof(struct s3c2410_dma_buf
));
1230 /* initialisation code */
1232 static int __init
s3c24xx_dma_sysclass_init(void)
1234 int ret
= sysdev_class_register(&dma_sysclass
);
1237 printk(KERN_ERR
"dma sysclass registration failed\n");
1242 core_initcall(s3c24xx_dma_sysclass_init
);
1244 static int __init
s3c24xx_dma_sysdev_register(void)
1246 struct s3c2410_dma_chan
*cp
= s3c2410_chans
;
1249 for (channel
= 0; channel
< dma_channels
; cp
++, channel
++) {
1250 cp
->dev
.cls
= &dma_sysclass
;
1251 cp
->dev
.id
= channel
;
1252 ret
= sysdev_register(&cp
->dev
);
1255 printk(KERN_ERR
"error registering dev for dma %d\n",
1264 late_initcall(s3c24xx_dma_sysdev_register
);
1266 int __init
s3c24xx_dma_init(unsigned int channels
, unsigned int irq
,
1267 unsigned int stride
)
1269 struct s3c2410_dma_chan
*cp
;
1273 printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
1275 dma_channels
= channels
;
1277 dma_base
= ioremap(S3C24XX_PA_DMA
, stride
* channels
);
1278 if (dma_base
== NULL
) {
1279 printk(KERN_ERR
"dma failed to remap register block\n");
1283 dma_kmem
= kmem_cache_create("dma_desc",
1284 sizeof(struct s3c2410_dma_buf
), 0,
1286 s3c2410_dma_cache_ctor
);
1288 if (dma_kmem
== NULL
) {
1289 printk(KERN_ERR
"dma failed to make kmem cache\n");
1294 for (channel
= 0; channel
< channels
; channel
++) {
1295 cp
= &s3c2410_chans
[channel
];
1297 memset(cp
, 0, sizeof(struct s3c2410_dma_chan
));
1299 /* dma channel irqs are in order.. */
1300 cp
->number
= channel
;
1301 cp
->irq
= channel
+ irq
;
1302 cp
->regs
= dma_base
+ (channel
* stride
);
1304 /* point current stats somewhere */
1305 cp
->stats
= &cp
->stats_store
;
1306 cp
->stats_store
.timeout_shortest
= LONG_MAX
;
1308 /* basic channel configuration */
1310 cp
->load_timeout
= 1<<18;
1312 printk("DMA channel %d at %p, irq %d\n",
1313 cp
->number
, cp
->regs
, cp
->irq
);
1319 kmem_cache_destroy(dma_kmem
);
1325 int __init
s3c2410_dma_init(void)
1327 return s3c24xx_dma_init(4, IRQ_DMA0
, 0x40);
1330 static inline int is_channel_valid(unsigned int channel
)
1332 return (channel
& DMA_CH_VALID
);
1335 static struct s3c24xx_dma_order
*dma_order
;
1338 /* s3c2410_dma_map_channel()
1340 * turn the virtual channel number into a real, and un-used hardware
1343 * first, try the dma ordering given to us by either the relevant
1344 * dma code, or the board. Then just find the first usable free
1348 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
)
1350 struct s3c24xx_dma_order_ch
*ord
= NULL
;
1351 struct s3c24xx_dma_map
*ch_map
;
1352 struct s3c2410_dma_chan
*dmach
;
1355 if (dma_sel
.map
== NULL
|| channel
> dma_sel
.map_size
)
1358 ch_map
= dma_sel
.map
+ channel
;
1360 /* first, try the board mapping */
1363 ord
= &dma_order
->channels
[channel
];
1365 for (ch
= 0; ch
< dma_channels
; ch
++) {
1367 if (!is_channel_valid(ord
->list
[ch
]))
1370 tmp
= ord
->list
[ch
] & ~DMA_CH_VALID
;
1371 if (s3c2410_chans
[tmp
].in_use
== 0) {
1377 if (ord
->flags
& DMA_CH_NEVER
)
1381 /* second, search the channel map for first free */
1383 for (ch
= 0; ch
< dma_channels
; ch
++) {
1384 if (!is_channel_valid(ch_map
->channels
[ch
]))
1387 if (s3c2410_chans
[ch
].in_use
== 0) {
1388 printk("mapped channel %d to %d\n", channel
, ch
);
1393 if (ch
>= dma_channels
)
1396 /* update our channel mapping */
1399 dmach
= &s3c2410_chans
[ch
];
1400 dmach
->map
= ch_map
;
1401 dmach
->req_ch
= channel
;
1402 s3c_dma_chan_map
[channel
] = dmach
;
1404 /* select the channel */
1406 (dma_sel
.select
)(dmach
, ch_map
);
1411 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map
*map
, int ch
)
1416 int __init
s3c24xx_dma_init_map(struct s3c24xx_dma_selection
*sel
)
1418 struct s3c24xx_dma_map
*nmap
;
1419 size_t map_sz
= sizeof(*nmap
) * sel
->map_size
;
1422 nmap
= kmalloc(map_sz
, GFP_KERNEL
);
1426 memcpy(nmap
, sel
->map
, map_sz
);
1427 memcpy(&dma_sel
, sel
, sizeof(*sel
));
1431 for (ptr
= 0; ptr
< sel
->map_size
; ptr
++)
1432 s3c24xx_dma_check_entry(nmap
+ptr
, ptr
);
1437 int __init
s3c24xx_dma_order_set(struct s3c24xx_dma_order
*ord
)
1439 struct s3c24xx_dma_order
*nord
= dma_order
;
1442 nord
= kmalloc(sizeof(struct s3c24xx_dma_order
), GFP_KERNEL
);
1445 printk(KERN_ERR
"no memory to store dma channel order\n");
1450 memcpy(nord
, ord
, sizeof(struct s3c24xx_dma_order
));