release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-pxa/include/plat/ssp.h

   1 /*
   2  *  ssp.h
   3  *
   4  *  Copyright (C) 2003 Russell King, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This driver supports the following PXA CPU/SSP ports:-
  11  *
  12  *       PXA250     SSP
  13  *       PXA255     SSP, NSSP
  14  *       PXA26x     SSP, NSSP, ASSP
  15  *       PXA27x     SSP1, SSP2, SSP3
  16  *       PXA3xx     SSP1, SSP2, SSP3, SSP4
  17  */
  18
  19 #ifndef __ASM_ARCH_SSP_H
  20 #define __ASM_ARCH_SSP_H
  21
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24
  25 /*
  26  * SSP Serial Port Registers
  27  * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
  28  * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
  29  */
  30
  31 #define SSCR0           (0x00)  /* SSP Control Register 0 */
  32 #define SSCR1           (0x04)  /* SSP Control Register 1 */
  33 #define SSSR            (0x08)  /* SSP Status Register */
  34 #define SSITR           (0x0C)  /* SSP Interrupt Test Register */
  35 #define SSDR            (0x10)  /* SSP Data Write/Data Read Register */
  36
  37 #define SSTO            (0x28)  /* SSP Time Out Register */
  38 #define SSPSP           (0x2C)  /* SSP Programmable Serial Protocol */
  39 #define SSTSA           (0x30)  /* SSP Tx Timeslot Active */
  40 #define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
  41 #define SSTSS           (0x38)  /* SSP Timeslot Status */
  42 #define SSACD           (0x3C)  /* SSP Audio Clock Divider */
  43 #define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
  44
  45 /* Common PXA2xx bits first */
  46 #define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
  47 #define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
  48 #define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
  49 #define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
  50 #define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
  51 #define SSCR0_National  (0x2 << 4)      /* National Microwire */
  52 #define SSCR0_ECS       (1 << 6)        /* External clock select */
  53 #define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
  54 #define SSCR0_SCR(x)    ((x) << 8)      /* Serial Clock Rate (mask) */
  55
  56 /* PXA27x, PXA3xx */
  57 #define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
  58 #define SSCR0_NCS       (1 << 21)       /* Network clock select */
  59 #define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
  60 #define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
  61 #define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
  62 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
  63 #define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
  64 #define SSCR0_ACS       (1 << 30)       /* Audio clock select */
  65 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
  66
  67
  68 #define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
  69 #define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
  70 #define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
  71 #define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
  72 #define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
  73 #define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
  74 #define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
  75 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
  76 #define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
  77 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
  78
  79 #define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
  80 #define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
  81 #define SSSR_BSY        (1 << 4)        /* SSP Busy */
  82 #define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
  83 #define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
  84 #define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
  85
  86
  87 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
  88 #define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
  89 #define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
  90 #define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
  91 #define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
  92 #define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
  93 #define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
  94 #define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
  95 #define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
  96 #define SSCR1_SCLKDIR           (1 << 25)       /* Serial Bit Rate Clock Direction */
  97 #define SSCR1_SFRMDIR           (1 << 24)       /* Frame Direction */
  98 #define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
  99 #define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
 100 #define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
 101 #define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
 102 #define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
 103 #define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
 104 #define SSCR1_IFS               (1 << 16)       /* Invert Frame Signal */
 105 #define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
 106 #define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
 107
 108 #define SSSR_BCE                (1 << 23)       /* Bit Count Error */
 109 #define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
 110 #define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
 111 #define SSSR_EOC                (1 << 20)       /* End Of Chain */
 112 #define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
 113 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 114
 115
 116 #define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
 117 #define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
 118 #define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
 119 #define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
 120 #define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
 121 #define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
 122 #define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
 123 #define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
 124 #define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
 125
 126 /* PXA3xx */
 127 #define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
 128 #define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
 129 #define SSPSP_TIMING_MASK       (0x7f8001f0)
 130
 131 #define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
 132 #define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
 133 #define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
 134 #define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
 135
 136 enum pxa_ssp_type {
 137         SSP_UNDEFINED = 0,
 138         PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
 139         PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
 140         PXA27x_SSP,
 141         PXA168_SSP,
 142 };
 143
 144 struct ssp_device {
 145         struct platform_device *pdev;
 146         struct list_head        node;
 147
 148         struct clk      *clk;
 149         void __iomem    *mmio_base;
 150         unsigned long   phys_base;
 151
 152         const char      *label;
 153         int             port_id;
 154         int             type;
 155         int             use_count;
 156         int             irq;
 157         int             drcmr_rx;
 158         int             drcmr_tx;
 159 };
 160
 161 /**
 162  * pxa_ssp_write_reg - Write to a SSP register
 163  *
 164  * @dev: SSP device to access
 165  * @reg: Register to write to
 166  * @val: Value to be written.
 167  */
 168 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
 169 {
 170         __raw_writel(val, dev->mmio_base + reg);
 171 }
 172
 173 /**
 174  * pxa_ssp_read_reg - Read from a SSP register
 175  *
 176  * @dev: SSP device to access
 177  * @reg: Register to read from
 178  */
 179 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
 180 {
 181         return __raw_readl(dev->mmio_base + reg);
 182 }
 183
 184 struct ssp_device *pxa_ssp_request(int port, const char *label);
 185 void pxa_ssp_free(struct ssp_device *);
 186 #endif /* __ASM_ARCH_SSP_H */