release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/fpga.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/fpga.h
   3  *
   4  * Interrupt handler for OMAP-1510 FPGA
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc.
   7  * Author: Greg Lonnon <glonnon@ridgerun.com>
   8  *
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  *
  11  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
  12  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #ifndef __ASM_ARCH_OMAP_FPGA_H
  20 #define __ASM_ARCH_OMAP_FPGA_H
  21
  22 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
  23 extern void omap1510_fpga_init_irq(void);
  24 #else
  25 #define omap1510_fpga_init_irq()        (0)
  26 #endif
  27
  28 #define fpga_read(reg)                  __raw_readb(reg)
  29 #define fpga_write(val, reg)            __raw_writeb(val, reg)
  30
  31 /*
  32  * ---------------------------------------------------------------------------
  33  *  H2/P2 Debug board FPGA
  34  * ---------------------------------------------------------------------------
  35  */
  36 /* maps in the FPGA registers and the ETHR registers */
  37 #define H2P2_DBG_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
  38 #define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
  39 #define H2P2_DBG_FPGA_START             0x04000000              /* PA */
  40
  41 #define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
  42 #define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
  43 #define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
  44 #define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
  45 #define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
  46 #define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
  47 #define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
  48 #define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
  49
  50 /* NOTE:  most boards don't have a static mapping for the FPGA ... */
  51 struct h2p2_dbg_fpga {
  52         /* offset 0x00 */
  53         u16             smc91x[8];
  54         /* offset 0x10 */
  55         u16             fpga_rev;
  56         u16             board_rev;
  57         u16             gpio_outputs;
  58         u16             leds;
  59         /* offset 0x18 */
  60         u16             misc_inputs;
  61         u16             lan_status;
  62         u16             lan_reset;
  63         u16             reserved0;
  64         /* offset 0x20 */
  65         u16             ps2_data;
  66         u16             ps2_ctrl;
  67         /* plus also 4 rs232 ports ... */
  68 };
  69
  70 /* LEDs definition on debug board (16 LEDs, all physically green) */
  71 #define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
  72 #define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
  73 #define H2P2_DBG_FPGA_LED_RED           (1 << 13)
  74 #define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
  75 /*  cpu0 load-meter LEDs */
  76 #define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
  77 #define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
  78 #define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
  79
  80 #define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
  81 #define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
  82
  83 /*
  84  * ---------------------------------------------------------------------------
  85  *  OMAP-1510 FPGA
  86  * ---------------------------------------------------------------------------
  87  */
  88 #define OMAP1510_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
  89 #define OMAP1510_FPGA_SIZE              SZ_4K
  90 #define OMAP1510_FPGA_START             0x08000000              /* PA */
  91
  92 /* Revision */
  93 #define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
  94 #define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
  95
  96 #define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
  97 #define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
  98 #define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
  99 #define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
 100
 101 /* Interrupt status */
 102 #define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
 103 #define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
 104
 105 /* Interrupt mask */
 106 #define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
 107 #define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
 108
 109 /* Reset registers */
 110 #define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
 111 #define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
 112
 113 #define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
 114 #define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
 115 #define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
 116 #define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
 117 #define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
 118 #define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
 119 #define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
 120 #define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
 121 #define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
 122 #define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
 123
 124 #define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
 125
 126 #define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
 127 #define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
 128 #define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
 129 #define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
 130 #define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
 131 #define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
 132 #define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
 133 #define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
 134 #define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
 135 #define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
 136 #define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
 137
 138 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
 139
 140 /*
 141  * Power up Giga UART driver, turn on HID clock.
 142  * Turn off BT power, since we're not using it and it
 143  * draws power.
 144  */
 145 #define OMAP1510_FPGA_RESET_VALUE               0x42
 146
 147 #define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
 148 #define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
 149 #define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
 150 #define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
 151 #define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
 152 #define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
 153 #define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
 154 #define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
 155
 156 /*
 157  * Innovator/OMAP1510 FPGA HID register bit definitions
 158  */
 159 #define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
 160 #define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
 161 #define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
 162 #define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
 163 #define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
 164 #define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
 165 #define OMAP1510_FPGA_HID_rsrvd (1<<6)
 166 #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
 167
 168 /* The FPGA IRQ is cascaded through GPIO_13 */
 169 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 170
 171 /* IRQ Numbers for interrupts muxed through the FPGA */
 172 #define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
 173 #define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
 174 #define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
 175 #define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
 176 #define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
 177 #define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
 178 #define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
 179 #define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
 180 #define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
 181 #define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
 182 #define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
 183 #define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
 184 #define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
 185 #define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
 186 #define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
 187 #define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
 188 #define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
 189 #define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
 190 #define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
 191 #define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
 192 #define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
 193 #define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
 194 #define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
 195 #define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
 196
 197 #endif