release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-brcm/include/plat/plat-bcm5301x.h

   1
   2 /*
   3  * iProc/iHost hardware rlated constants
   4  */
   5
   6 #define SOC_CHIPCOMON_A_BASE_PA 0x18000000
   7 #define SOC_CHIPCOMON_B_BASE_PA 0x18001000
   8
   9 #define SOC_SDOM_BASE_PA        0x18130000      /* System discover ROM */
  10
  11 #define SOC_DMU_BASE_PA         0x1800c000      /* Power, Clock controls */
  12
  13 /*
  14  * UART Enumaration -
  15  * ChipcommonB UART0 : ttyS0
  16  * ChipcommonA UART0-1: ttyS1-ttyS3
  17  * TBD: which UARTs chare the I/O pins and are thus mutually exclusive ?!
  18  */
  19 #define PLAT_UART0_PA   0x18008000      /* ChipcommonB UART0 */
  20 #define IRQ_UART0       (32+85)
  21
  22 #define PLAT_UART1_PA   (SOC_CHIPCOMON_A_BASE_PA+0x300)
  23 #define PLAT_UART2_PA   (SOC_CHIPCOMON_A_BASE_PA+0x400)
  24 #define IRQ_CCA         117
  25
  26
  27 /* PL310 L2 Cache Controller base address */
  28 #define L2CC_BASE_PA            0x19022000      /* Verified */
  29 /* L2 is 16-ways 256KByte w/ Parity */
  30
  31 /*
  32  * There is a 1KB LUT located at 0xFFFF0400-0xFFFFFFFF, and its first entry
  33  * is where the secondary entry point needs to be written
  34 */
  35 #define SOC_ROM_BASE_PA         0xffff0000
  36 #define SOC_ROM_LUT_OFF         0x400
  37
  38 /*
  39  * DRAM begins at 0x8000000 and can be 128MiB, 512MiB or 1GiB continous,
  40  * but first 128MiB is also aliased at address 0x0.
  41  */
  42 #define DRAM_LARGE_REGION_BASE  0x80000000
  43 #define DRAM_MEMORY_REGION_BASE 0x00000000
  44 #define DRAM_MEMORY_REGION_SIZE SZ_128M