release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-brcm/include/mach/uncompress.h

   1 /*
   2  * These are macros and inlines needed for the kernel decompressor
   3  * prinarily for debugging messages.
   4  *
   5  * The NorthStar chip has two UART channels in ChipcommonA which are
   6  * byte-spaced and must be byte addressed, while the UART in ChipcommonB
   7  * is 32-bit word spaced and addressed.
   8  */
   9
  10
  11 #ifndef    __ASM_ARCH_UNCOMPRESS_H
  12 #define __ASM_ARCH_UNCOMPRESS_H
  13
  14 #ifndef CONFIG_DEBUG_LL             /* Enable debug UART offset calculations */
  15 #define CONFIG_DEBUG_LL
  16 #endif
  17
  18 #include <linux/io.h>
  19 #include <mach/io_map.h>
  20
  21 #define PLAT_LLDEBUG_UART_PA    CONFIG_DEBUG_UART_ADDR
  22
  23 #ifndef PLAT_LLDEBUG_UART_SH
  24 #error  Internal header error
  25 #endif
  26
  27 #define UART_BASE_ADDR           PLAT_LLDEBUG_UART_PA
  28 #define UART_RBR_THR_DLL_OFFSET 0x00
  29 #define UART_LSR_OFFSET         (0x14 >> 2 << PLAT_LLDEBUG_UART_SH)
  30 #define UART_LSR_THRE_MASK      0x60
  31 #define UART_LSR_TEMT_MASK      0x40
  32
  33 #if PLAT_LLDEBUG_UART_SH == 2
  34 #define UART_READ_REG   __raw_readl
  35 #define UART_WRITE_REG  __raw_writel
  36 #elif PLAT_LLDEBUG_UART_SH == 0
  37 #define UART_READ_REG   __raw_readb
  38 #define UART_WRITE_REG  __raw_writeb
  39 #else
  40 #error  UART register shift value unsupported
  41 #endif
  42
  43 static inline void putc(int c)
  44 {
  45         unsigned count = 1 << 20;
  46
  47         /*
  48         * data should be written to THR register only
  49         * if THRE (LSR bit5) is set)
  50         */
  51         while (0 == (UART_READ_REG( UART_BASE_ADDR + UART_LSR_OFFSET)
  52                 & UART_LSR_THRE_MASK ))
  53                 {
  54                 if( --count == 0 ) break;
  55                 }
  56
  57         UART_WRITE_REG(c, UART_BASE_ADDR + UART_RBR_THR_DLL_OFFSET);
  58 }
  59
  60 static inline void flush(void)
  61 {
  62         unsigned count = 1 << 20;
  63         /* Wait for the tx fifo to be empty and last char to be sent */
  64         while (0 == (UART_READ_REG(UART_BASE_ADDR + UART_LSR_OFFSET)
  65                 & UART_LSR_TEMT_MASK ))
  66                 {
  67                 if( --count == 0 ) break;
  68                 }
  69 }
  70
  71 static inline void arch_decomp_setup(void)
  72 {
  73 }
  74
  75 #define arch_decomp_wdog()
  76
  77 #endif /* __ASM_ARCH_UNCOMPRESS_H */