release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mm/fault-armv.c

   1 /*
   2  *  linux/arch/arm/mm/fault-armv.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Modifications for ARM processor (c) 1995-2002 Russell King
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/init.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/gfp.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/cachetype.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/tlbflush.h>
  26
  27 #include "mm.h"
  28
  29 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
  30
  31 /*
  32  * We take the easy way out of this problem - we make the
  33  * PTE uncacheable.  However, we leave the write buffer on.
  34  *
  35  * Note that the pte lock held when calling update_mmu_cache must also
  36  * guard the pte (somewhere else in the same mm) that we modify here.
  37  * Therefore those configurations which might call adjust_pte (those
  38  * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
  39  */
  40 static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
  41         unsigned long pfn, pte_t *ptep)
  42 {
  43         pte_t entry = *ptep;
  44         int ret;
  45
  46         /*
  47          * If this page is present, it's actually being shared.
  48          */
  49         ret = pte_present(entry);
  50
  51         /*
  52          * If this page isn't present, or is already setup to
  53          * fault (ie, is old), we can safely ignore any issues.
  54          */
  55         if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
  56                 flush_cache_page(vma, address, pfn);
  57                 outer_flush_range((pfn << PAGE_SHIFT),
  58                                   (pfn << PAGE_SHIFT) + PAGE_SIZE);
  59                 pte_val(entry) &= ~L_PTE_MT_MASK;
  60                 pte_val(entry) |= shared_pte_mask;
  61                 set_pte_at(vma->vm_mm, address, ptep, entry);
  62                 flush_tlb_page(vma, address);
  63         }
  64
  65         return ret;
  66 }
  67
  68 #if USE_SPLIT_PTLOCKS
  69 /*
  70  * If we are using split PTE locks, then we need to take the page
  71  * lock here.  Otherwise we are using shared mm->page_table_lock
  72  * which is already locked, thus cannot take it.
  73  */
  74 static inline void do_pte_lock(spinlock_t *ptl)
  75 {
  76         /*
  77          * Use nested version here to indicate that we are already
  78          * holding one similar spinlock.
  79          */
  80         spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
  81 }
  82
  83 static inline void do_pte_unlock(spinlock_t *ptl)
  84 {
  85         spin_unlock(ptl);
  86 }
  87 #else /* !USE_SPLIT_PTLOCKS */
  88 static inline void do_pte_lock(spinlock_t *ptl) {}
  89 static inline void do_pte_unlock(spinlock_t *ptl) {}
  90 #endif /* USE_SPLIT_PTLOCKS */
  91
  92 static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
  93         unsigned long pfn)
  94 {
  95         spinlock_t *ptl;
  96         pgd_t *pgd;
  97         pmd_t *pmd;
  98         pte_t *pte;
  99         int ret;
 100
 101         pgd = pgd_offset(vma->vm_mm, address);
 102         if (pgd_none_or_clear_bad(pgd))
 103                 return 0;
 104
 105         pmd = pmd_offset(pgd, address);
 106         if (pmd_none_or_clear_bad(pmd))
 107                 return 0;
 108
 109         /*
 110          * This is called while another page table is mapped, so we
 111          * must use the nested version.  This also means we need to
 112          * open-code the spin-locking.
 113          */
 114         ptl = pte_lockptr(vma->vm_mm, pmd);
 115         pte = pte_offset_map_nested(pmd, address);
 116         do_pte_lock(ptl);
 117
 118         ret = do_adjust_pte(vma, address, pfn, pte);
 119
 120         do_pte_unlock(ptl);
 121         pte_unmap_nested(pte);
 122
 123         return ret;
 124 }
 125
 126 static void
 127 make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
 128         unsigned long addr, pte_t *ptep, unsigned long pfn)
 129 {
 130         struct mm_struct *mm = vma->vm_mm;
 131         struct vm_area_struct *mpnt;
 132         struct prio_tree_iter iter;
 133         unsigned long offset;
 134         pgoff_t pgoff;
 135         int aliases = 0;
 136
 137         pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
 138
 139         /*
 140          * If we have any shared mappings that are in the same mm
 141          * space, then we need to handle them specially to maintain
 142          * cache coherency.
 143          */
 144         flush_dcache_mmap_lock(mapping);
 145         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 146                 /*
 147                  * If this VMA is not in our MM, we can ignore it.
 148                  * Note that we intentionally mask out the VMA
 149                  * that we are fixing up.
 150                  */
 151                 if (mpnt->vm_mm != mm || mpnt == vma)
 152                         continue;
 153                 if (!(mpnt->vm_flags & VM_MAYSHARE))
 154                         continue;
 155                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 156                 aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
 157         }
 158         flush_dcache_mmap_unlock(mapping);
 159         if (aliases)
 160                 do_adjust_pte(vma, addr, pfn, ptep);
 161 }
 162
 163 /*
 164  * Take care of architecture specific things when placing a new PTE into
 165  * a page table, or changing an existing PTE.  Basically, there are two
 166  * things that we need to take care of:
 167  *
 168  *  1. If PG_dcache_dirty is set for the page, we need to ensure
 169  *     that any cache entries for the kernels virtual memory
 170  *     range are written back to the page.
 171  *  2. If we have multiple shared mappings of the same space in
 172  *     an object, we need to deal with the cache aliasing issues.
 173  *
 174  * Note that the pte lock will be held.
 175  */
 176 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 177         pte_t *ptep)
 178 {
 179         unsigned long pfn = pte_pfn(*ptep);
 180         struct address_space *mapping;
 181         struct page *page;
 182
 183         if (!pfn_valid(pfn))
 184                 return;
 185
 186         /*
 187          * The zero page is never written to, so never has any dirty
 188          * cache lines, and therefore never needs to be flushed.
 189          */
 190         page = pfn_to_page(pfn);
 191         if (page == ZERO_PAGE(0))
 192                 return;
 193
 194         mapping = page_mapping(page);
 195 #ifndef CONFIG_SMP
 196         if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
 197                 __flush_dcache_page(mapping, page);
 198 #endif
 199         if (mapping) {
 200                 if (cache_is_vivt())
 201                         make_coherent(mapping, vma, addr, ptep, pfn);
 202                 else if (vma->vm_flags & VM_EXEC)
 203                         __flush_icache_all();
 204         }
 205 }
 206
 207 /*
 208  * Check whether the write buffer has physical address aliasing
 209  * issues.  If it has, we need to avoid them for the case where
 210  * we have several shared mappings of the same object in user
 211  * space.
 212  */
 213 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
 214 {
 215         register unsigned long zero = 0, one = 1, val;
 216
 217         local_irq_disable();
 218         mb();
 219         *p1 = one;
 220         mb();
 221         *p2 = zero;
 222         mb();
 223         val = *p1;
 224         mb();
 225         local_irq_enable();
 226         return val != zero;
 227 }
 228
 229 void __init check_writebuffer_bugs(void)
 230 {
 231         struct page *page;
 232         const char *reason;
 233         unsigned long v = 1;
 234
 235         printk(KERN_INFO "CPU: Testing write buffer coherency: ");
 236
 237         page = alloc_page(GFP_KERNEL);
 238         if (page) {
 239                 unsigned long *p1, *p2;
 240                 pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
 241                                         L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
 242
 243                 p1 = vmap(&page, 1, VM_IOREMAP, prot);
 244                 p2 = vmap(&page, 1, VM_IOREMAP, prot);
 245
 246                 if (p1 && p2) {
 247                         v = check_writebuffer(p1, p2);
 248                         reason = "enabling work-around";
 249                 } else {
 250                         reason = "unable to map memory\n";
 251                 }
 252
 253                 vunmap(p1);
 254                 vunmap(p2);
 255                 put_page(page);
 256         } else {
 257                 reason = "unable to grab page\n";
 258         }
 259
 260         if (v) {
 261                 printk("failed, %s\n", reason);
 262                 shared_pte_mask = L_PTE_MT_UNCACHED;
 263         } else {
 264                 printk("ok\n");
 265         }
 266 }