release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h

   1 /*
   2  * stmp37xx: SSP register definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21 #define REGS_SSP_BASE   (STMP3XXX_REGS_BASE + 0x10000)
  22 #define REGS_SSP1_PHYS  0x80010000
  23 #define REGS_SSP2_PHYS  0x80034000
  24 #define REGS_SSP_SIZE   0x2000
  25
  26 #define HW_SSP_CTRL0            0x0
  27 #define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
  28 #define BP_SSP_CTRL0_XFER_COUNT 0
  29 #define BM_SSP_CTRL0_ENABLE     0x00010000
  30 #define BM_SSP_CTRL0_GET_RESP   0x00020000
  31 #define BM_SSP_CTRL0_LONG_RESP  0x00080000
  32 #define BM_SSP_CTRL0_WAIT_FOR_CMD       0x00100000
  33 #define BM_SSP_CTRL0_WAIT_FOR_IRQ       0x00200000
  34 #define BM_SSP_CTRL0_BUS_WIDTH  0x00C00000
  35 #define BP_SSP_CTRL0_BUS_WIDTH  22
  36 #define BM_SSP_CTRL0_DATA_XFER  0x01000000
  37 #define BM_SSP_CTRL0_READ       0x02000000
  38 #define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
  39 #define BM_SSP_CTRL0_LOCK_CS    0x08000000
  40 #define BM_SSP_CTRL0_RUN        0x20000000
  41 #define BM_SSP_CTRL0_CLKGATE    0x40000000
  42 #define BM_SSP_CTRL0_SFTRST     0x80000000
  43
  44 #define HW_SSP_CMD0             0x10
  45 #define BM_SSP_CMD0_CMD         0x000000FF
  46 #define BP_SSP_CMD0_CMD         0
  47 #define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
  48 #define BP_SSP_CMD0_BLOCK_COUNT 8
  49 #define BM_SSP_CMD0_BLOCK_SIZE  0x000F0000
  50 #define BP_SSP_CMD0_BLOCK_SIZE  16
  51 #define BM_SSP_CMD0_APPEND_8CYC 0x00100000
  52 #define BM_SSP_CMD1_CMD_ARG     0xFFFFFFFF
  53 #define BP_SSP_CMD1_CMD_ARG     0
  54
  55 #define HW_SSP_TIMING           0x50
  56 #define BM_SSP_TIMING_CLOCK_RATE        0x000000FF
  57 #define BP_SSP_TIMING_CLOCK_RATE        0
  58 #define BM_SSP_TIMING_CLOCK_DIVIDE      0x0000FF00
  59 #define BP_SSP_TIMING_CLOCK_DIVIDE      8
  60 #define BM_SSP_TIMING_TIMEOUT   0xFFFF0000
  61 #define BP_SSP_TIMING_TIMEOUT   16
  62
  63 #define HW_SSP_CTRL1            0x60
  64 #define BM_SSP_CTRL1_SSP_MODE   0x0000000F
  65 #define BP_SSP_CTRL1_SSP_MODE   0
  66 #define BM_SSP_CTRL1_WORD_LENGTH        0x000000F0
  67 #define BP_SSP_CTRL1_WORD_LENGTH        4
  68 #define BM_SSP_CTRL1_POLARITY   0x00000200
  69 #define BM_SSP_CTRL1_PHASE      0x00000400
  70 #define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
  71 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ   0x00008000
  72 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x00010000
  73 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   0x00020000
  74 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ  0x00200000
  75 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN    0x00400000
  76 #define BM_SSP_CTRL1_DATA_CRC_IRQ       0x00800000
  77 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x01000000
  78 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ   0x02000000
  79 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x04000000
  80 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ   0x08000000
  81 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN    0x10000000
  82 #define BM_SSP_CTRL1_RESP_ERR_IRQ       0x20000000
  83 #define BM_SSP_CTRL1_SDIO_IRQ   0x80000000
  84
  85 #define HW_SSP_DATA             0x70
  86
  87 #define HW_SSP_SDRESP0          0x80
  88
  89 #define HW_SSP_SDRESP1          0x90
  90
  91 #define HW_SSP_SDRESP2          0xA0
  92
  93 #define HW_SSP_SDRESP3          0xB0
  94
  95 #define HW_SSP_STATUS           0xC0
  96 #define BM_SSP_STATUS_FIFO_EMPTY        0x00000020
  97 #define BM_SSP_STATUS_TIMEOUT   0x00001000
  98 #define BM_SSP_STATUS_RESP_TIMEOUT      0x00004000
  99 #define BM_SSP_STATUS_RESP_ERR  0x00008000
 100 #define BM_SSP_STATUS_RESP_CRC_ERR      0x00010000
 101 #define BM_SSP_STATUS_CARD_DETECT       0x10000000