release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h

   1 /*
   2  * stmp378x: GPMI register definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21 #define REGS_GPMI_BASE  (STMP3XXX_REGS_BASE + 0xC000)
  22 #define REGS_GPMI_PHYS  0x8000C000
  23 #define REGS_GPMI_SIZE  0x2000
  24
  25 #define HW_GPMI_CTRL0           0x0
  26 #define BM_GPMI_CTRL0_XFER_COUNT        0x0000FFFF
  27 #define BP_GPMI_CTRL0_XFER_COUNT        0
  28 #define BM_GPMI_CTRL0_CS        0x00300000
  29 #define BP_GPMI_CTRL0_CS        20
  30 #define BM_GPMI_CTRL0_LOCK_CS   0x00400000
  31 #define BM_GPMI_CTRL0_WORD_LENGTH       0x00800000
  32 #define BM_GPMI_CTRL0_ADDRESS      0x000E0000
  33 #define BP_GPMI_CTRL0_ADDRESS      17
  34 #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA  0x0
  35 #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE   0x1
  36 #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE   0x2
  37 #define BM_GPMI_CTRL0_ADDRESS_INCREMENT      0x00010000
  38 #define BM_GPMI_CTRL0_COMMAND_MODE      0x03000000
  39 #define BP_GPMI_CTRL0_COMMAND_MODE      24
  40 #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE           0x0
  41 #define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
  42 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
  43 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
  44 #define BM_GPMI_CTRL0_RUN       0x20000000
  45 #define BM_GPMI_CTRL0_CLKGATE   0x40000000
  46 #define BM_GPMI_CTRL0_SFTRST    0x80000000
  47 #define BM_GPMI_ECCCTRL_BUFFER_MASK     0x000001FF
  48 #define BP_GPMI_ECCCTRL_BUFFER_MASK     0
  49 #define BM_GPMI_ECCCTRL_ENABLE_ECC      0x00001000
  50 #define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
  51 #define BP_GPMI_ECCCTRL_ECC_CMD 13
  52 #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT                   0
  53 #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT                   1
  54 #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT                   2
  55 #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT                   3
  56
  57 #define HW_GPMI_CTRL1           0x60
  58 #define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
  59 #define BP_GPMI_CTRL1_GPMI_MODE 0
  60 #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY       0x00000004
  61 #define BM_GPMI_CTRL1_DEV_RESET 0x00000008
  62 #define BM_GPMI_CTRL1_TIMEOUT_IRQ       0x00000200
  63 #define BM_GPMI_CTRL1_DEV_IRQ   0x00000400
  64 #define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
  65 #define BP_GPMI_CTRL1_RDN_DELAY 12
  66 #define BM_GPMI_CTRL1_BCH_MODE  0x00040000
  67
  68 #define HW_GPMI_TIMING0         0x70
  69 #define BM_GPMI_TIMING0_DATA_SETUP      0x000000FF
  70 #define BP_GPMI_TIMING0_DATA_SETUP      0
  71 #define BM_GPMI_TIMING0_DATA_HOLD       0x0000FF00
  72 #define BP_GPMI_TIMING0_DATA_HOLD       8
  73 #define BM_GPMI_TIMING0_ADDRESS_SETUP   0x00FF0000
  74 #define BP_GPMI_TIMING0_ADDRESS_SETUP   16
  75
  76 #define HW_GPMI_TIMING1         0x80
  77 #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xFFFF0000
  78 #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16