2 * SA11x0 Assembler Sleep/WakeUp Management Routines
4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
11 * 2001-02-06: Cliff Brake Initial code
13 * 2001-08-29: Nicolas Pitre Simplified.
15 * 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
16 * Storage is on the stack now.
19 #include <linux/linkage.h>
20 #include <asm/assembler.h>
21 #include <mach/hardware.h>
30 * sa1100_cpu_suspend()
32 * Causes sa11x0 to enter sleep state
36 ENTRY(sa1100_cpu_suspend)
38 stmfd sp!, {r4 - r12, lr} @ save registers on stack
40 @ get coprocessor registers
41 mrc p15, 0, r4, c3, c0, 0 @ domain ID
42 mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
43 mrc p15, 0, r6, c13, c0, 0 @ PID
44 mrc p15, 0, r7, c1, c0, 0 @ control reg
46 @ store them plus current virtual stack ptr on stack
50 @ preserve phys address of stack
53 ldr r1, =sleep_save_sp
56 @ clean data cache and invalidate WB
57 bl v4wb_flush_kern_cache_all
59 @ disable clock switching
60 mcr p15, 0, r1, c15, c2, 2
62 @ Adjust memory timing before lowering CPU clock
63 @ Clock speed adjustment without changing memory timing makes
64 @ CPU hang in some cases
67 orr r1, r1, #MDREFR_K1DB2
70 @ delay 90us and set CPU PLL to lowest speed
71 @ fixes resume problem on high speed SA1110
86 bic r3, r3, #FMsk(MSC_RT)
87 bic r3, r3, #FMsk(MSC_RT)<<16
90 bic r4, r4, #FMsk(MSC_RT)
91 bic r4, r4, #FMsk(MSC_RT)<<16
94 bic r5, r5, #FMsk(MSC_RT)
95 bic r5, r5, #FMsk(MSC_RT)<<16
100 bic r7, r7, #0x0000FF00
101 bic r7, r7, #0x000000F0
102 orr r8, r7, #MDREFR_SLFRSH
106 bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
107 bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
109 bic r11, r8, #MDREFR_SLFRSH
110 bic r11, r11, #MDREFR_E1PIN
116 b sa1110_sdram_controller_fix
119 sa1110_sdram_controller_fix:
121 @ Step 1 clear RT field of all MSCx registers
126 @ Step 2 clear DRI field in MDREFR
129 @ Step 3 set SLFRSH bit in MDREFR
132 @ Step 4 clear DE bis in MDCNFG
135 @ Step 5 clear DRAM refresh control register
138 @ Wow, now the hardware suspend request pins can be used, that makes them functional for
139 @ about 7 ns out of the entire time that the CPU is running!
141 @ Step 6 set force sleep bit in PMCR
145 20: b 20b @ loop waiting for sleep
148 * cpu_sa1100_resume()
150 * entry point from bootloader into kernel during resume
152 * Note: Yes, part of the following code is located into the .data section.
153 * This is to allow sleep_save_sp to be accessed with a relative load
154 * while we can't rely on any MMU translation. We could have put
155 * sleep_save_sp in the .text section as well, but some setups might
156 * insist on it to be truly read-only.
161 ENTRY(sa1100_cpu_resume)
162 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
163 msr cpsr_c, r0 @ set SVC, irqs off
165 ldr r0, sleep_save_sp @ stack phys addr
166 ldr r2, =resume_after_mmu @ its absolute virtual address
167 ldmfd r0, {r4 - r7, sp} @ CP regs + virt stack ptr
170 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
171 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
172 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
173 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
175 mcr p15, 0, r4, c3, c0, 0 @ domain ID
176 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
177 mcr p15, 0, r6, c13, c0, 0 @ PID
178 b resume_turn_on_mmu @ cache align execution
182 mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, caches, etc.
184 mov pc, r2 @ jump to virtual addr
190 .word 0 @ preserve stack phys ptr here
194 mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
195 ldmfd sp!, {r4 - r12, pc} @ return to caller