release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c64xx/s3c6400.c

   1 /* linux/arch/arm/mach-s3c64xx/cpu.c
   2  *
   3  * Copyright 2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/irq.h>
  27
  28 #include <mach/hardware.h>
  29 #include <asm/irq.h>
  30
  31 #include <plat/cpu-freq.h>
  32 #include <plat/regs-serial.h>
  33 #include <mach/regs-clock.h>
  34
  35 #include <plat/cpu.h>
  36 #include <plat/devs.h>
  37 #include <plat/clock.h>
  38 #include <plat/sdhci.h>
  39 #include <plat/iic-core.h>
  40 #include <plat/onenand-core.h>
  41 #include <mach/s3c6400.h>
  42
  43 void __init s3c6400_map_io(void)
  44 {
  45         /* setup SDHCI */
  46
  47         s3c6400_default_sdhci0();
  48         s3c6400_default_sdhci1();
  49         s3c6400_default_sdhci2();
  50
  51         /* the i2c devices are directly compatible with s3c2440 */
  52         s3c_i2c0_setname("s3c2440-i2c");
  53
  54         s3c_device_nand.name = "s3c6400-nand";
  55
  56         s3c_onenand_setname("s3c6400-onenand");
  57         s3c64xx_onenand1_setname("s3c6400-onenand");
  58 }
  59
  60 void __init s3c6400_init_clocks(int xtal)
  61 {
  62         s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
  63         s3c6400_setup_clocks();
  64 }
  65
  66 void __init s3c6400_init_irq(void)
  67 {
  68         /* VIC0 does not have IRQS 5..7,
  69          * VIC1 is fully populated. */
  70         s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
  71 }
  72
  73 struct sysdev_class s3c6400_sysclass = {
  74         .name   = "s3c6400-core",
  75 };
  76
  77 static struct sys_device s3c6400_sysdev = {
  78         .cls    = &s3c6400_sysclass,
  79 };
  80
  81 static int __init s3c6400_core_init(void)
  82 {
  83         return sysdev_class_register(&s3c6400_sysclass);
  84 }
  85
  86 core_initcall(s3c6400_core_init);
  87
  88 int __init s3c6400_init(void)
  89 {
  90         printk("S3C6400: Initialising architecture\n");
  91
  92         return sysdev_register(&s3c6400_sysdev);
  93 }