release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h

   1 /* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * GPIO Bank D register and configuration definitions
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #define S3C64XX_GPDCON                  (S3C64XX_GPD_BASE + 0x00)
  16 #define S3C64XX_GPDDAT                  (S3C64XX_GPD_BASE + 0x04)
  17 #define S3C64XX_GPDPUD                  (S3C64XX_GPD_BASE + 0x08)
  18 #define S3C64XX_GPDCONSLP               (S3C64XX_GPD_BASE + 0x0c)
  19 #define S3C64XX_GPDPUDSLP               (S3C64XX_GPD_BASE + 0x10)
  20
  21 #define S3C64XX_GPD_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
  22 #define S3C64XX_GPD_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
  23 #define S3C64XX_GPD_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
  24
  25 #define S3C64XX_GPD0_PCM0_SCLK          (0x02 << 0)
  26 #define S3C64XX_GPD0_I2S0_CLK           (0x03 << 0)
  27 #define S3C64XX_GPD0_AC97_BITCLK        (0x04 << 0)
  28 #define S3C64XX_GPD0_EINT_G3_0          (0x07 << 0)
  29
  30 #define S3C64XX_GPD1_PCM0_EXTCLK        (0x02 << 4)
  31 #define S3C64XX_GPD1_I2S0_CDCLK         (0x03 << 4)
  32 #define S3C64XX_GPD1_AC97_nRESET        (0x04 << 4)
  33 #define S3C64XX_GPD1_EINT_G3_1          (0x07 << 4)
  34
  35 #define S3C64XX_GPD2_PCM0_FSYNC         (0x02 << 8)
  36 #define S3C64XX_GPD2_I2S0_LRCLK         (0x03 << 8)
  37 #define S3C64XX_GPD2_AC97_SYNC          (0x04 << 8)
  38 #define S3C64XX_GPD2_EINT_G3_2          (0x07 << 8)
  39
  40 #define S3C64XX_GPD3_PCM0_SIN           (0x02 << 12)
  41 #define S3C64XX_GPD3_I2S0_DI            (0x03 << 12)
  42 #define S3C64XX_GPD3_AC97_SDI           (0x04 << 12)
  43 #define S3C64XX_GPD3_EINT_G3_3          (0x07 << 12)
  44
  45 #define S3C64XX_GPD4_PCM0_SOUT          (0x02 << 16)
  46 #define S3C64XX_GPD4_I2S0_D0            (0x03 << 16)
  47 #define S3C64XX_GPD4_AC97_SDO           (0x04 << 16)
  48 #define S3C64XX_GPD4_EINT_G3_4          (0x07 << 16)