release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/irqs.h

   1 /*
   2  *  arch/arm/mach-pxa/include/mach/irqs.h
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef __ASM_MACH_IRQS_H
  13 #define __ASM_MACH_IRQS_H
  14
  15 #ifdef CONFIG_PXA_HAVE_ISA_IRQS
  16 #define PXA_ISA_IRQ(x)  (x)
  17 #define PXA_ISA_IRQ_NUM (16)
  18 #else
  19 #define PXA_ISA_IRQ_NUM (0)
  20 #endif
  21
  22 #define PXA_IRQ(x)      (PXA_ISA_IRQ_NUM + (x))
  23
  24 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  25 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
  26 #define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
  27 #define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
  28 #define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
  29 #define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
  30 #define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
  31 #define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
  32 #endif
  33
  34 #define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
  35 #define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
  36 #define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
  37 #define IRQ_GPIO1       PXA_IRQ(9)      /* GPIO1 Edge Detect */
  38 #define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
  39 #define IRQ_USB         PXA_IRQ(11)     /* USB Service */
  40 #define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
  41 #define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
  42 #define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
  43 #define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
  44 #define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
  45 #define IRQ_NSSP        PXA_IRQ(16)     /* Network SSP Service Request (PXA25x) */
  46 #define IRQ_SSP2        PXA_IRQ(16)     /* SSP2 interrupt (PXA27x) */
  47 #define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
  48 #define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
  49 #define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
  50 #define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
  51 #define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
  52 #define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
  53 #define IRQ_MMC         PXA_IRQ(23)     /* MMC Status/Error Detection */
  54 #define IRQ_SSP         PXA_IRQ(24)     /* SSP Service Request */
  55 #define IRQ_DMA         PXA_IRQ(25)     /* DMA Channel Service Request */
  56 #define IRQ_OST0        PXA_IRQ(26)     /* OS Timer match 0 */
  57 #define IRQ_OST1        PXA_IRQ(27)     /* OS Timer match 1 */
  58 #define IRQ_OST2        PXA_IRQ(28)     /* OS Timer match 2 */
  59 #define IRQ_OST3        PXA_IRQ(29)     /* OS Timer match 3 */
  60 #define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
  61 #define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
  62
  63 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  64 #define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
  65 #define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
  66 #endif
  67
  68 #ifdef CONFIG_PXA3xx
  69 #define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
  70 #define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
  71 #define IRQ_COMM_WDT    PXA_IRQ(35)     /* Comm WDT interrupt */
  72 #define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
  73 #define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
  74 #define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller */
  75 #define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
  76 #define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
  77 #define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
  78 #define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
  79 #define IRQ_WAKEUP0     PXA_IRQ(49)     /* EXT_WAKEUP0 */
  80 #define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
  81 #define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
  82 #define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
  83 #endif
  84
  85 #ifdef CONFIG_CPU_PXA935
  86 #define IRQ_U2O         PXA_IRQ(64)     /* USB OTG 2.0 Controller (PXA935) */
  87 #define IRQ_U2H         PXA_IRQ(65)     /* USB Host 2.0 Controller (PXA935) */
  88
  89 #define IRQ_MMC3_PXA935 PXA_IRQ(72)     /* MMC3 Controller (PXA935) */
  90 #define IRQ_MMC4_PXA935 PXA_IRQ(73)     /* MMC4 Controller (PXA935) */
  91 #define IRQ_MMC5_PXA935 PXA_IRQ(74)     /* MMC5 Controller (PXA935) */
  92
  93 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
  94 #endif
  95
  96 #ifdef CONFIG_CPU_PXA930
  97 #define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
  98 #define IRQ_ACIPC0      PXA_IRQ(5)
  99 #define IRQ_ACIPC1      PXA_IRQ(40)
 100 #define IRQ_ACIPC2      PXA_IRQ(19)
 101 #define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball */
 102 #endif
 103
 104 #ifdef CONFIG_CPU_PXA950
 105 #define IRQ_GC500       PXA_IRQ(70)     /* Graphics Controller (PXA950) */
 106 #endif
 107
 108 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
 109 #define PXA_GPIO_IRQ_NUM        (192)
 110
 111 #define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
 112 #define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
 113
 114 #define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
 115 #define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
 116
 117 /*
 118  * The following interrupts are for board specific purposes. Since
 119  * the kernel can only run on one machine at a time, we can re-use
 120  * these.  There will be 16 IRQs by default.  If it is not enough,
 121  * IRQ_BOARD_END is allowed be customized for each board, but keep
 122  * the numbers within sensible limits and in descending order, so
 123  * when multiple config options are selected, the maximum will be
 124  * used.
 125  */
 126 #define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
 127
 128 #if defined(CONFIG_MACH_H4700)
 129 #define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
 130 #elif defined(CONFIG_MACH_ZYLONITE)
 131 #define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
 132 #elif defined(CONFIG_PXA_EZX)
 133 #define IRQ_BOARD_END           (IRQ_BOARD_START + 23)
 134 #else
 135 #define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
 136 #endif
 137
 138 /*
 139  * Figure out the MAX IRQ number.
 140  *
 141  * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
 142  * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
 143  * Otherwise, we have the standard IRQs only.
 144  */
 145 #ifdef CONFIG_SA1111
 146 #define NR_IRQS                 (IRQ_BOARD_END + 55)
 147 #elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
 148 #define NR_IRQS                 (IRQ_BOARD_END)
 149 #else
 150 #define NR_IRQS                 (IRQ_BOARD_START)
 151 #endif
 152
 153 /* add IT8152 IRQs beyond BOARD_END */
 154 #ifdef CONFIG_PCI_HOST_ITE8152
 155 #define IT8152_LAST_IRQ         (IRQ_BOARD_END + 40)
 156
 157 #if NR_IRQS < (IT8152_LAST_IRQ+1)
 158 #undef NR_IRQS
 159 #define NR_IRQS (IT8152_LAST_IRQ+1)
 160 #endif
 161
 162 #endif /* CONFIG_PCI_HOST_ITE8152 */
 163
 164 #endif /* __ASM_MACH_IRQS_H */